1 ; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s 2 3 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) { 4 entry: 5 ; CHECK-LABEL: add_h: 6 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h 7 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h 8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]] 9 ; CHECK: fcvtn v0.4h, [[RES]] 10 %0 = fadd <4 x half> %a, %b 11 ret <4 x half> %0 12 } 13 14 15 define <4 x half> @build_h4(<4 x half> %a) { 16 entry: 17 ; CHECK-LABEL: build_h4: 18 ; CHECK: mov [[GPR:w[0-9]+]], #15565 19 ; CHECK: dup v0.4h, [[GPR]] 20 ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD> 21 } 22 23 24 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) { 25 entry: 26 ; CHECK-LABEL: sub_h: 27 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h 28 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h 29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]] 30 ; CHECK: fcvtn v0.4h, [[RES]] 31 %0 = fsub <4 x half> %a, %b 32 ret <4 x half> %0 33 } 34 35 36 define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) { 37 entry: 38 ; CHECK-LABEL: mul_h: 39 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h 40 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h 41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]] 42 ; CHECK: fcvtn v0.4h, [[RES]] 43 %0 = fmul <4 x half> %a, %b 44 ret <4 x half> %0 45 } 46 47 48 define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) { 49 entry: 50 ; CHECK-LABEL: div_h: 51 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h 52 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h 53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]] 54 ; CHECK: fcvtn v0.4h, [[RES]] 55 %0 = fdiv <4 x half> %a, %b 56 ret <4 x half> %0 57 } 58 59 60 define <4 x half> @load_h(<4 x half>* %a) { 61 entry: 62 ; CHECK-LABEL: load_h: 63 ; CHECK: ldr d0, [x0] 64 %0 = load <4 x half>, <4 x half>* %a, align 4 65 ret <4 x half> %0 66 } 67 68 69 define void @store_h(<4 x half>* %a, <4 x half> %b) { 70 entry: 71 ; CHECK-LABEL: store_h: 72 ; CHECK: str d0, [x0] 73 store <4 x half> %b, <4 x half>* %a, align 4 74 ret void 75 } 76 77 define <4 x half> @s_to_h(<4 x float> %a) { 78 ; CHECK-LABEL: s_to_h: 79 ; CHECK: fcvtn v0.4h, v0.4s 80 %1 = fptrunc <4 x float> %a to <4 x half> 81 ret <4 x half> %1 82 } 83 84 define <4 x half> @d_to_h(<4 x double> %a) { 85 ; CHECK-LABEL: d_to_h: 86 ; CHECK-DAG: fcvt 87 ; CHECK-DAG: fcvt 88 ; CHECK-DAG: fcvt 89 ; CHECK-DAG: fcvt 90 ; CHECK-DAG: ins 91 ; CHECK-DAG: ins 92 ; CHECK-DAG: ins 93 ; CHECK-DAG: ins 94 %1 = fptrunc <4 x double> %a to <4 x half> 95 ret <4 x half> %1 96 } 97 98 define <4 x float> @h_to_s(<4 x half> %a) { 99 ; CHECK-LABEL: h_to_s: 100 ; CHECK: fcvtl v0.4s, v0.4h 101 %1 = fpext <4 x half> %a to <4 x float> 102 ret <4 x float> %1 103 } 104 105 define <4 x double> @h_to_d(<4 x half> %a) { 106 ; CHECK-LABEL: h_to_d: 107 ; CHECK-DAG: fcvt 108 ; CHECK-DAG: fcvt 109 ; CHECK-DAG: fcvt 110 ; CHECK-DAG: fcvt 111 ; CHECK-DAG: ins 112 ; CHECK-DAG: ins 113 ; CHECK-DAG: ins 114 ; CHECK-DAG: ins 115 %1 = fpext <4 x half> %a to <4 x double> 116 ret <4 x double> %1 117 } 118 119 define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) { 120 ; CHECK-LABEL: bitcast_i_to_h: 121 ; CHECK: mov v0.16b, v1.16b 122 %2 = bitcast <4 x i16> %a to <4 x half> 123 ret <4 x half> %2 124 } 125 126 define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) { 127 ; CHECK-LABEL: bitcast_h_to_i: 128 ; CHECK: mov v0.16b, v1.16b 129 %2 = bitcast <4 x half> %a to <4 x i16> 130 ret <4 x i16> %2 131 } 132 133 define <4 x half> @sitofp_i8(<4 x i8> %a) #0 { 134 ; CHECK-LABEL: sitofp_i8: 135 ; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8 136 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8 137 ; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0 138 ; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]] 139 ; CHECK-NEXT: fcvtn v0.4h, [[OP4]] 140 ; CHECK-NEXT: ret 141 %1 = sitofp <4 x i8> %a to <4 x half> 142 ret <4 x half> %1 143 } 144 145 146 define <4 x half> @sitofp_i16(<4 x i16> %a) #0 { 147 ; CHECK-LABEL: sitofp_i16: 148 ; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0 149 ; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]] 150 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]] 151 ; CHECK-NEXT: ret 152 %1 = sitofp <4 x i16> %a to <4 x half> 153 ret <4 x half> %1 154 } 155 156 157 define <4 x half> @sitofp_i32(<4 x i32> %a) #0 { 158 ; CHECK-LABEL: sitofp_i32: 159 ; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s 160 ; CHECK-NEXT: fcvtn v0.4h, [[OP1]] 161 %1 = sitofp <4 x i32> %a to <4 x half> 162 ret <4 x half> %1 163 } 164 165 166 define <4 x half> @sitofp_i64(<4 x i64> %a) #0 { 167 ; CHECK-LABEL: sitofp_i64: 168 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d 169 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d 170 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] 171 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]] 172 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s 173 %1 = sitofp <4 x i64> %a to <4 x half> 174 ret <4 x half> %1 175 } 176 177 define <4 x half> @uitofp_i8(<4 x i8> %a) #0 { 178 ; CHECK-LABEL: uitofp_i8: 179 ; CHECK-NEXT: bic v0.4h, #255, lsl #8 180 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0 181 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]] 182 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]] 183 ; CHECK-NEXT: ret 184 %1 = uitofp <4 x i8> %a to <4 x half> 185 ret <4 x half> %1 186 } 187 188 189 define <4 x half> @uitofp_i16(<4 x i16> %a) #0 { 190 ; CHECK-LABEL: uitofp_i16: 191 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0 192 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]] 193 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]] 194 ; CHECK-NEXT: ret 195 %1 = uitofp <4 x i16> %a to <4 x half> 196 ret <4 x half> %1 197 } 198 199 200 define <4 x half> @uitofp_i32(<4 x i32> %a) #0 { 201 ; CHECK-LABEL: uitofp_i32: 202 ; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s 203 ; CHECK-NEXT: fcvtn v0.4h, [[OP1]] 204 %1 = uitofp <4 x i32> %a to <4 x half> 205 ret <4 x half> %1 206 } 207 208 209 define <4 x half> @uitofp_i64(<4 x i64> %a) #0 { 210 ; CHECK-LABEL: uitofp_i64: 211 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d 212 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d 213 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] 214 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]] 215 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s 216 %1 = uitofp <4 x i64> %a to <4 x half> 217 ret <4 x half> %1 218 } 219 220 define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 { 221 ; CHECK-LABEL: test_insert_at_zero: 222 ; CHECK-NEXT: str d0, [x0] 223 ; CHECK-NEXT: ret 224 %1 = insertelement <4 x half> undef, half %a, i64 0 225 store <4 x half> %1, <4 x half>* %b, align 4 226 ret void 227 } 228 229 define <4 x i8> @fptosi_i8(<4 x half> %a) #0 { 230 ; CHECK-LABEL: fptosi_i8: 231 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h 232 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]] 233 ; CHECK-NEXT: xtn v0.4h, [[REG2]] 234 ; CHECK-NEXT: ret 235 %1 = fptosi<4 x half> %a to <4 x i8> 236 ret <4 x i8> %1 237 } 238 239 define <4 x i16> @fptosi_i16(<4 x half> %a) #0 { 240 ; CHECK-LABEL: fptosi_i16: 241 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h 242 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]] 243 ; CHECK-NEXT: xtn v0.4h, [[REG2]] 244 ; CHECK-NEXT: ret 245 %1 = fptosi<4 x half> %a to <4 x i16> 246 ret <4 x i16> %1 247 } 248 249 define <4 x i8> @fptoui_i8(<4 x half> %a) #0 { 250 ; CHECK-LABEL: fptoui_i8: 251 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h 252 ; NOTE: fcvtzs selected here because the xtn shaves the sign bit 253 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]] 254 ; CHECK-NEXT: xtn v0.4h, [[REG2]] 255 ; CHECK-NEXT: ret 256 %1 = fptoui<4 x half> %a to <4 x i8> 257 ret <4 x i8> %1 258 } 259 260 define <4 x i16> @fptoui_i16(<4 x half> %a) #0 { 261 ; CHECK-LABEL: fptoui_i16: 262 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h 263 ; CHECK-NEXT: fcvtzu [[REG2:v[0-9]+\.4s]], [[REG1]] 264 ; CHECK-NEXT: xtn v0.4h, [[REG2]] 265 ; CHECK-NEXT: ret 266 %1 = fptoui<4 x half> %a to <4 x i16> 267 ret <4 x i16> %1 268 } 269 270 ; Function Attrs: nounwind readnone 271 ; CHECK-LABEL: test_fcmp_une: 272 ; CHECK-DAG: fcvt 273 ; CHECK-DAG: fcvt 274 ; CHECK-DAG: fcvt 275 ; CHECK-DAG: fcvt 276 ; CHECK-DAG: fcvt 277 ; CHECK-DAG: fcvt 278 ; CHECK-DAG: fcvt 279 ; CHECK-DAG: fcvt 280 ; CHECK-DAG: csetm {{.*}}, ne 281 ; CHECK-DAG: csetm {{.*}}, ne 282 ; CHECK-DAG: csetm {{.*}}, ne 283 ; CHECK-DAG: csetm {{.*}}, ne 284 define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 { 285 %1 = fcmp une <4 x half> %a, %b 286 ret <4 x i1> %1 287 } 288 289 ; Function Attrs: nounwind readnone 290 ; CHECK-LABEL: test_fcmp_ueq: 291 ; CHECK-DAG: fcvt 292 ; CHECK-DAG: fcvt 293 ; CHECK-DAG: fcvt 294 ; CHECK-DAG: fcvt 295 ; CHECK-DAG: fcvt 296 ; CHECK-DAG: fcvt 297 ; CHECK-DAG: fcvt 298 ; CHECK-DAG: fcvt 299 ; CHECK-DAG: csetm [[REG1:w[0-9]+]], eq 300 ; CHECK-DAG: csetm [[REG2:w[0-9]+]], eq 301 ; CHECK-DAG: csetm [[REG3:w[0-9]+]], eq 302 ; CHECK-DAG: csetm [[REG4:w[0-9]+]], eq 303 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc 304 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc 305 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc 306 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc 307 define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 { 308 %1 = fcmp ueq <4 x half> %a, %b 309 ret <4 x i1> %1 310 } 311 312 ; Function Attrs: nounwind readnone 313 ; CHECK-LABEL: test_fcmp_ugt: 314 ; CHECK-DAG: fcvt 315 ; CHECK-DAG: fcvt 316 ; CHECK-DAG: fcvt 317 ; CHECK-DAG: fcvt 318 ; CHECK-DAG: fcvt 319 ; CHECK-DAG: fcvt 320 ; CHECK-DAG: fcvt 321 ; CHECK-DAG: fcvt 322 ; CHECK-DAG: csetm {{.*}}, hi 323 ; CHECK-DAG: csetm {{.*}}, hi 324 ; CHECK-DAG: csetm {{.*}}, hi 325 ; CHECK-DAG: csetm {{.*}}, hi 326 define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 { 327 %1 = fcmp ugt <4 x half> %a, %b 328 ret <4 x i1> %1 329 } 330 331 ; Function Attrs: nounwind readnone 332 ; CHECK-LABEL: test_fcmp_uge: 333 ; CHECK-DAG: fcvt 334 ; CHECK-DAG: fcvt 335 ; CHECK-DAG: fcvt 336 ; CHECK-DAG: fcvt 337 ; CHECK-DAG: fcvt 338 ; CHECK-DAG: fcvt 339 ; CHECK-DAG: fcvt 340 ; CHECK-DAG: fcvt 341 ; CHECK-DAG: csetm {{.*}}, pl 342 ; CHECK-DAG: csetm {{.*}}, pl 343 ; CHECK-DAG: csetm {{.*}}, pl 344 ; CHECK-DAG: csetm {{.*}}, pl 345 define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 { 346 %1 = fcmp uge <4 x half> %a, %b 347 ret <4 x i1> %1 348 } 349 350 ; Function Attrs: nounwind readnone 351 ; CHECK-LABEL: test_fcmp_ult: 352 ; CHECK-DAG: fcvt 353 ; CHECK-DAG: fcvt 354 ; CHECK-DAG: fcvt 355 ; CHECK-DAG: fcvt 356 ; CHECK-DAG: fcvt 357 ; CHECK-DAG: fcvt 358 ; CHECK-DAG: fcvt 359 ; CHECK-DAG: fcvt 360 ; CHECK-DAG: csetm {{.*}}, lt 361 ; CHECK-DAG: csetm {{.*}}, lt 362 ; CHECK-DAG: csetm {{.*}}, lt 363 ; CHECK-DAG: csetm {{.*}}, lt 364 define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 { 365 %1 = fcmp ult <4 x half> %a, %b 366 ret <4 x i1> %1 367 } 368 369 ; Function Attrs: nounwind readnone 370 ; CHECK-LABEL: test_fcmp_ule: 371 ; CHECK-DAG: fcvt 372 ; CHECK-DAG: fcvt 373 ; CHECK-DAG: fcvt 374 ; CHECK-DAG: fcvt 375 ; CHECK-DAG: fcvt 376 ; CHECK-DAG: fcvt 377 ; CHECK-DAG: fcvt 378 ; CHECK-DAG: fcvt 379 ; CHECK-DAG: csetm {{.*}}, le 380 ; CHECK-DAG: csetm {{.*}}, le 381 ; CHECK-DAG: csetm {{.*}}, le 382 ; CHECK-DAG: csetm {{.*}}, le 383 define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 { 384 %1 = fcmp ule <4 x half> %a, %b 385 ret <4 x i1> %1 386 } 387 388 ; Function Attrs: nounwind readnone 389 ; CHECK-LABEL: test_fcmp_uno: 390 ; CHECK-DAG: fcvt 391 ; CHECK-DAG: fcvt 392 ; CHECK-DAG: fcvt 393 ; CHECK-DAG: fcvt 394 ; CHECK-DAG: fcvt 395 ; CHECK-DAG: fcvt 396 ; CHECK-DAG: fcvt 397 ; CHECK-DAG: fcvt 398 ; CHECK-DAG: csetm {{.*}}, vs 399 ; CHECK-DAG: csetm {{.*}}, vs 400 ; CHECK-DAG: csetm {{.*}}, vs 401 ; CHECK-DAG: csetm {{.*}}, vs 402 define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 { 403 %1 = fcmp uno <4 x half> %a, %b 404 ret <4 x i1> %1 405 } 406 407 ; Function Attrs: nounwind readnone 408 ; CHECK-LABEL: test_fcmp_one: 409 ; CHECK-DAG: fcvt 410 ; CHECK-DAG: fcvt 411 ; CHECK-DAG: fcvt 412 ; CHECK-DAG: fcvt 413 ; CHECK-DAG: fcvt 414 ; CHECK-DAG: fcvt 415 ; CHECK-DAG: fcvt 416 ; CHECK-DAG: fcvt 417 ; CHECK-DAG: csetm [[REG1:w[0-9]+]], mi 418 ; CHECK-DAG: csetm [[REG2:w[0-9]+]], mi 419 ; CHECK-DAG: csetm [[REG3:w[0-9]+]], mi 420 ; CHECK-DAG: csetm [[REG4:w[0-9]+]], mi 421 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le 422 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le 423 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le 424 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le 425 426 define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 { 427 %1 = fcmp one <4 x half> %a, %b 428 ret <4 x i1> %1 429 } 430 431 ; Function Attrs: nounwind readnone 432 ; CHECK-LABEL: test_fcmp_oeq: 433 ; CHECK-DAG: fcvt 434 ; CHECK-DAG: fcvt 435 ; CHECK-DAG: fcvt 436 ; CHECK-DAG: fcvt 437 ; CHECK-DAG: fcvt 438 ; CHECK-DAG: fcvt 439 ; CHECK-DAG: fcvt 440 ; CHECK-DAG: fcvt 441 ; CHECK-DAG: csetm {{.*}}, eq 442 ; CHECK-DAG: csetm {{.*}}, eq 443 ; CHECK-DAG: csetm {{.*}}, eq 444 ; CHECK-DAG: csetm {{.*}}, eq 445 define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 { 446 %1 = fcmp oeq <4 x half> %a, %b 447 ret <4 x i1> %1 448 } 449 450 ; Function Attrs: nounwind readnone 451 ; CHECK-LABEL: test_fcmp_ogt: 452 ; CHECK-DAG: fcvt 453 ; CHECK-DAG: fcvt 454 ; CHECK-DAG: fcvt 455 ; CHECK-DAG: fcvt 456 ; CHECK-DAG: fcvt 457 ; CHECK-DAG: fcvt 458 ; CHECK-DAG: fcvt 459 ; CHECK-DAG: fcvt 460 ; CHECK-DAG: csetm {{.*}}, gt 461 ; CHECK-DAG: csetm {{.*}}, gt 462 ; CHECK-DAG: csetm {{.*}}, gt 463 ; CHECK-DAG: csetm {{.*}}, gt 464 define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 { 465 %1 = fcmp ogt <4 x half> %a, %b 466 ret <4 x i1> %1 467 } 468 469 ; Function Attrs: nounwind readnone 470 ; CHECK-LABEL: test_fcmp_oge: 471 ; CHECK-DAG: fcvt 472 ; CHECK-DAG: fcvt 473 ; CHECK-DAG: fcvt 474 ; CHECK-DAG: fcvt 475 ; CHECK-DAG: fcvt 476 ; CHECK-DAG: fcvt 477 ; CHECK-DAG: fcvt 478 ; CHECK-DAG: fcvt 479 ; CHECK-DAG: csetm {{.*}}, ge 480 ; CHECK-DAG: csetm {{.*}}, ge 481 ; CHECK-DAG: csetm {{.*}}, ge 482 ; CHECK-DAG: csetm {{.*}}, ge 483 define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 { 484 %1 = fcmp oge <4 x half> %a, %b 485 ret <4 x i1> %1 486 } 487 488 ; Function Attrs: nounwind readnone 489 ; CHECK-LABEL: test_fcmp_olt: 490 ; CHECK-DAG: fcvt 491 ; CHECK-DAG: fcvt 492 ; CHECK-DAG: fcvt 493 ; CHECK-DAG: fcvt 494 ; CHECK-DAG: fcvt 495 ; CHECK-DAG: fcvt 496 ; CHECK-DAG: fcvt 497 ; CHECK-DAG: fcvt 498 ; CHECK-DAG: csetm {{.*}}, mi 499 ; CHECK-DAG: csetm {{.*}}, mi 500 ; CHECK-DAG: csetm {{.*}}, mi 501 ; CHECK-DAG: csetm {{.*}}, mi 502 define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 { 503 %1 = fcmp olt <4 x half> %a, %b 504 ret <4 x i1> %1 505 } 506 507 ; Function Attrs: nounwind readnone 508 ; CHECK-LABEL: test_fcmp_ole: 509 ; CHECK-DAG: fcvt 510 ; CHECK-DAG: fcvt 511 ; CHECK-DAG: fcvt 512 ; CHECK-DAG: fcvt 513 ; CHECK-DAG: fcvt 514 ; CHECK-DAG: fcvt 515 ; CHECK-DAG: fcvt 516 ; CHECK-DAG: fcvt 517 ; CHECK-DAG: csetm {{.*}}, ls 518 ; CHECK-DAG: csetm {{.*}}, ls 519 ; CHECK-DAG: csetm {{.*}}, ls 520 ; CHECK-DAG: csetm {{.*}}, ls 521 define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 { 522 %1 = fcmp ole <4 x half> %a, %b 523 ret <4 x i1> %1 524 } 525 526 ; Function Attrs: nounwind readnone 527 ; CHECK-LABEL: test_fcmp_ord: 528 ; CHECK-DAG: fcvt 529 ; CHECK-DAG: fcvt 530 ; CHECK-DAG: fcvt 531 ; CHECK-DAG: fcvt 532 ; CHECK-DAG: fcvt 533 ; CHECK-DAG: fcvt 534 ; CHECK-DAG: fcvt 535 ; CHECK-DAG: fcvt 536 ; CHECK-DAG: csetm {{.*}}, vc 537 ; CHECK-DAG: csetm {{.*}}, vc 538 ; CHECK-DAG: csetm {{.*}}, vc 539 ; CHECK-DAG: csetm {{.*}}, vc 540 define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 { 541 %1 = fcmp ord <4 x half> %a, %b 542 ret <4 x i1> %1 543 } 544 545 attributes #0 = { nounwind } 546
