1 ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s 2 3 define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 { 4 ; CHECK-LABEL: v4f16_to_v4i16: 5 ; CHECK: mov v0.16b, v1.16b 6 entry: 7 %1 = bitcast <4 x half> %a to <4 x i16> 8 ret <4 x i16> %1 9 } 10 11 define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 { 12 ; CHECK-LABEL: v4f16_to_v2i32: 13 ; CHECK: mov v0.16b, v1.16b 14 entry: 15 %1 = bitcast <4 x half> %a to <2 x i32> 16 ret <2 x i32> %1 17 } 18 19 define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 { 20 ; CHECK-LABEL: v4f16_to_v1i64: 21 ; CHECK: mov v0.16b, v1.16b 22 entry: 23 %1 = bitcast <4 x half> %a to <1 x i64> 24 ret <1 x i64> %1 25 } 26 27 define i64 @v4f16_to_i64(float, <4 x half> %a) #0 { 28 ; CHECK-LABEL: v4f16_to_i64: 29 ; CHECK: fmov x0, d1 30 entry: 31 %1 = bitcast <4 x half> %a to i64 32 ret i64 %1 33 } 34 35 define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 { 36 ; CHECK-LABEL: v4f16_to_v2float: 37 ; CHECK: mov v0.16b, v1.16b 38 entry: 39 %1 = bitcast <4 x half> %a to <2 x float> 40 ret <2 x float> %1 41 } 42 43 define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 { 44 ; CHECK-LABEL: v4f16_to_v1double: 45 ; CHECK: mov v0.16b, v1.16b 46 entry: 47 %1 = bitcast <4 x half> %a to <1 x double> 48 ret <1 x double> %1 49 } 50 51 define double @v4f16_to_double(float, <4 x half> %a) #0 { 52 ; CHECK-LABEL: v4f16_to_double: 53 ; CHECK: mov v0.16b, v1.16b 54 entry: 55 %1 = bitcast <4 x half> %a to double 56 ret double %1 57 } 58 59 60 define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 { 61 ; CHECK-LABEL: v4i16_to_v4f16: 62 ; CHECK: mov v0.16b, v1.16b 63 entry: 64 %1 = bitcast <4 x i16> %a to <4 x half> 65 ret <4 x half> %1 66 } 67 68 define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 { 69 ; CHECK-LABEL: v2i32_to_v4f16: 70 ; CHECK: mov v0.16b, v1.16b 71 entry: 72 %1 = bitcast <2 x i32> %a to <4 x half> 73 ret <4 x half> %1 74 } 75 76 define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 { 77 ; CHECK-LABEL: v1i64_to_v4f16: 78 ; CHECK: mov v0.16b, v1.16b 79 entry: 80 %1 = bitcast <1 x i64> %a to <4 x half> 81 ret <4 x half> %1 82 } 83 84 define <4 x half> @i64_to_v4f16(float, i64 %a) #0 { 85 ; CHECK-LABEL: i64_to_v4f16: 86 ; CHECK: fmov d0, x0 87 entry: 88 %1 = bitcast i64 %a to <4 x half> 89 ret <4 x half> %1 90 } 91 92 define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 { 93 ; CHECK-LABEL: v2float_to_v4f16: 94 ; CHECK: mov v0.16b, v1.16b 95 entry: 96 %1 = bitcast <2 x float> %a to <4 x half> 97 ret <4 x half> %1 98 } 99 100 define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 { 101 ; CHECK-LABEL: v1double_to_v4f16: 102 ; CHECK: mov v0.16b, v1.16b 103 entry: 104 %1 = bitcast <1 x double> %a to <4 x half> 105 ret <4 x half> %1 106 } 107 108 define <4 x half> @double_to_v4f16(float, double %a) #0 { 109 ; CHECK-LABEL: double_to_v4f16: 110 ; CHECK: mov v0.16b, v1.16b 111 entry: 112 %1 = bitcast double %a to <4 x half> 113 ret <4 x half> %1 114 } 115 116 117 118 119 120 121 122 123 124 125 define <8 x i16> @v8f16_to_v8i16(float, <8 x half> %a) #0 { 126 ; CHECK-LABEL: v8f16_to_v8i16: 127 ; CHECK: mov v0.16b, v1.16b 128 entry: 129 %1 = bitcast <8 x half> %a to <8 x i16> 130 ret <8 x i16> %1 131 } 132 133 define <4 x i32> @v8f16_to_v4i32(float, <8 x half> %a) #0 { 134 ; CHECK-LABEL: v8f16_to_v4i32: 135 ; CHECK: mov v0.16b, v1.16b 136 entry: 137 %1 = bitcast <8 x half> %a to <4 x i32> 138 ret <4 x i32> %1 139 } 140 141 define <2 x i64> @v8f16_to_v2i64(float, <8 x half> %a) #0 { 142 ; CHECK-LABEL: v8f16_to_v2i64: 143 ; CHECK: mov v0.16b, v1.16b 144 entry: 145 %1 = bitcast <8 x half> %a to <2 x i64> 146 ret <2 x i64> %1 147 } 148 149 define <4 x float> @v8f16_to_v4float(float, <8 x half> %a) #0 { 150 ; CHECK-LABEL: v8f16_to_v4float: 151 ; CHECK: mov v0.16b, v1.16b 152 entry: 153 %1 = bitcast <8 x half> %a to <4 x float> 154 ret <4 x float> %1 155 } 156 157 define <2 x double> @v8f16_to_v2double(float, <8 x half> %a) #0 { 158 ; CHECK-LABEL: v8f16_to_v2double: 159 ; CHECK: mov v0.16b, v1.16b 160 entry: 161 %1 = bitcast <8 x half> %a to <2 x double> 162 ret <2 x double> %1 163 } 164 165 define <8 x half> @v8i16_to_v8f16(float, <8 x i16> %a) #0 { 166 ; CHECK-LABEL: v8i16_to_v8f16: 167 ; CHECK: mov v0.16b, v1.16b 168 entry: 169 %1 = bitcast <8 x i16> %a to <8 x half> 170 ret <8 x half> %1 171 } 172 173 define <8 x half> @v4i32_to_v8f16(float, <4 x i32> %a) #0 { 174 ; CHECK-LABEL: v4i32_to_v8f16: 175 ; CHECK: mov v0.16b, v1.16b 176 entry: 177 %1 = bitcast <4 x i32> %a to <8 x half> 178 ret <8 x half> %1 179 } 180 181 define <8 x half> @v2i64_to_v8f16(float, <2 x i64> %a) #0 { 182 ; CHECK-LABEL: v2i64_to_v8f16: 183 ; CHECK: mov v0.16b, v1.16b 184 entry: 185 %1 = bitcast <2 x i64> %a to <8 x half> 186 ret <8 x half> %1 187 } 188 189 define <8 x half> @v4float_to_v8f16(float, <4 x float> %a) #0 { 190 ; CHECK-LABEL: v4float_to_v8f16: 191 ; CHECK: mov v0.16b, v1.16b 192 entry: 193 %1 = bitcast <4 x float> %a to <8 x half> 194 ret <8 x half> %1 195 } 196 197 define <8 x half> @v2double_to_v8f16(float, <2 x double> %a) #0 { 198 ; CHECK-LABEL: v2double_to_v8f16: 199 ; CHECK: mov v0.16b, v1.16b 200 entry: 201 %1 = bitcast <2 x double> %a to <8 x half> 202 ret <8 x half> %1 203 } 204
