1 ; RUN: llc -mtriple=aarch64-unknown-unknown %s -mcpu=cyclone -o - | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK 2 ; RUN: llc -march aarch64 %s -mattr=-slow-misaligned-128store -o - | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK 3 4 @g0 = external global <3 x float>, align 16 5 @g1 = external global <3 x float>, align 4 6 7 ; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4 8 ; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}} 9 ; CHECK: str d[[R0]] 10 11 define void @blam() { 12 %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0 13 %tmp5 = load <3 x float>, <3 x float>* @g0, align 16 14 %tmp6 = extractelement <3 x float> %tmp5, i64 0 15 store float %tmp6, float* %tmp4 16 %tmp7 = getelementptr inbounds float, float* %tmp4, i64 1 17 %tmp8 = load <3 x float>, <3 x float>* @g0, align 16 18 %tmp9 = extractelement <3 x float> %tmp8, i64 1 19 store float %tmp9, float* %tmp7 20 ret void; 21 } 22 23 24 ; PR21711 - Merge vector stores into wider vector stores. 25 26 ; On Cyclone, the stores should not get merged into a 16-byte store because 27 ; unaligned 16-byte stores are slow. This test would infinite loop when 28 ; the fastness of unaligned accesses was not specified correctly. 29 30 define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) { 31 %idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3 32 %idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4 33 34 %shuffle0 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 0, i32 1> 35 %shuffle1 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 2, i32 3> 36 37 store <2 x float> %shuffle0, <2 x float>* %idx0, align 8 38 store <2 x float> %shuffle1, <2 x float>* %idx1, align 8 39 ret void 40 41 ; MISALIGNED-LABEL: merge_vec_extract_stores 42 ; MISALIGNED: stur q0, [x0, #24] 43 ; MISALIGNED-NEXT: ret 44 45 ; FIXME: Ideally we would like to use a generic target for this test, but this relies 46 ; on suppressing store pairs. 47 48 ; CYCLONE-LABEL: merge_vec_extract_stores 49 ; CYCLONE: ext v1.16b, v0.16b, v0.16b, #8 50 ; CYCLONE-NEXT: str d0, [x0, #24] 51 ; CYCLONE-NEXT: str d1, [x0, #32] 52 ; CYCLONE-NEXT: ret 53 } 54
