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      1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
      2 
      3 ; From <8 x i8>
      4 
      5 define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
      6 ; CHECK: test_v8i8_to_v1i64:
      7 ; CHECK-NEXT: // BB#0:
      8 ; CHECK-NEXT: ret
      9 
     10   %val = bitcast <8 x i8> %in to <1 x i64>
     11   ret <1 x i64> %val
     12 }
     13 
     14 define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
     15 ; CHECK: test_v8i8_to_v2i32:
     16 ; CHECK-NEXT: // BB#0:
     17 ; CHECK-NEXT: ret
     18 
     19   %val = bitcast <8 x i8> %in to <2 x i32>
     20   ret <2 x i32> %val
     21 }
     22 
     23 define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{
     24 ; CHECK: test_v8i8_to_v2f32:
     25 ; CHECK-NEXT: // BB#0:
     26 ; CHECK-NEXT: ret
     27 
     28   %val = bitcast <8 x i8> %in to <2 x float>
     29   ret <2 x float> %val
     30 }
     31 
     32 define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{
     33 ; CHECK: test_v8i8_to_v4i16:
     34 ; CHECK-NEXT: // BB#0:
     35 ; CHECK-NEXT: ret
     36 
     37   %val = bitcast <8 x i8> %in to <4 x i16>
     38   ret <4 x i16> %val
     39 }
     40 
     41 define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{
     42 ; CHECK: test_v8i8_to_v8i8:
     43 ; CHECK-NEXT: // BB#0:
     44 ; CHECK-NEXT: ret
     45 
     46   %val = bitcast <8 x i8> %in to <8 x i8>
     47   ret <8 x i8> %val
     48 }
     49 
     50 ; From <4 x i16>
     51 
     52 define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind {
     53 ; CHECK: test_v4i16_to_v1i64:
     54 ; CHECK-NEXT: // BB#0:
     55 ; CHECK-NEXT: ret
     56 
     57   %val = bitcast <4 x i16> %in to <1 x i64>
     58   ret <1 x i64> %val
     59 }
     60 
     61 define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
     62 ; CHECK: test_v4i16_to_v2i32:
     63 ; CHECK-NEXT: // BB#0:
     64 ; CHECK-NEXT: ret
     65 
     66   %val = bitcast <4 x i16> %in to <2 x i32>
     67   ret <2 x i32> %val
     68 }
     69 
     70 define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{
     71 ; CHECK: test_v4i16_to_v2f32:
     72 ; CHECK-NEXT: // BB#0:
     73 ; CHECK-NEXT: ret
     74 
     75   %val = bitcast <4 x i16> %in to <2 x float>
     76   ret <2 x float> %val
     77 }
     78 
     79 define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{
     80 ; CHECK: test_v4i16_to_v4i16:
     81 ; CHECK-NEXT: // BB#0:
     82 ; CHECK-NEXT: ret
     83 
     84   %val = bitcast <4 x i16> %in to <4 x i16>
     85   ret <4 x i16> %val
     86 }
     87 
     88 define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{
     89 ; CHECK: test_v4i16_to_v8i8:
     90 ; CHECK-NEXT: // BB#0:
     91 ; CHECK-NEXT: ret
     92 
     93   %val = bitcast <4 x i16> %in to <8 x i8>
     94   ret <8 x i8> %val
     95 }
     96 
     97 ; From <2 x i32>
     98 
     99 define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind {
    100 ; CHECK: test_v2i32_to_v1i64:
    101 ; CHECK-NEXT: // BB#0:
    102 ; CHECK-NEXT: ret
    103 
    104   %val = bitcast <2 x i32> %in to <1 x i64>
    105   ret <1 x i64> %val
    106 }
    107 
    108 define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
    109 ; CHECK: test_v2i32_to_v2i32:
    110 ; CHECK-NEXT: // BB#0:
    111 ; CHECK-NEXT: ret
    112 
    113   %val = bitcast <2 x i32> %in to <2 x i32>
    114   ret <2 x i32> %val
    115 }
    116 
    117 define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{
    118 ; CHECK: test_v2i32_to_v2f32:
    119 ; CHECK-NEXT: // BB#0:
    120 ; CHECK-NEXT: ret
    121 
    122   %val = bitcast <2 x i32> %in to <2 x float>
    123   ret <2 x float> %val
    124 }
    125 
    126 define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{
    127 ; CHECK: test_v2i32_to_v4i16:
    128 ; CHECK-NEXT: // BB#0:
    129 ; CHECK-NEXT: ret
    130 
    131   %val = bitcast <2 x i32> %in to <4 x i16>
    132   ret <4 x i16> %val
    133 }
    134 
    135 define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{
    136 ; CHECK: test_v2i32_to_v8i8:
    137 ; CHECK-NEXT: // BB#0:
    138 ; CHECK-NEXT: ret
    139 
    140   %val = bitcast <2 x i32> %in to <8 x i8>
    141   ret <8 x i8> %val
    142 }
    143 
    144 ; From <2 x float>
    145 
    146 define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind {
    147 ; CHECK: test_v2f32_to_v1i64:
    148 ; CHECK-NEXT: // BB#0:
    149 ; CHECK-NEXT: ret
    150 
    151   %val = bitcast <2 x float> %in to <1 x i64>
    152   ret <1 x i64> %val
    153 }
    154 
    155 define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind {
    156 ; CHECK: test_v2f32_to_v2i32:
    157 ; CHECK-NEXT: // BB#0:
    158 ; CHECK-NEXT: ret
    159 
    160   %val = bitcast <2 x float> %in to <2 x i32>
    161   ret <2 x i32> %val
    162 }
    163 
    164 define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{
    165 ; CHECK: test_v2f32_to_v2f32:
    166 ; CHECK-NEXT: // BB#0:
    167 ; CHECK-NEXT: ret
    168 
    169   %val = bitcast <2 x float> %in to <2 x float>
    170   ret <2 x float> %val
    171 }
    172 
    173 define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{
    174 ; CHECK: test_v2f32_to_v4i16:
    175 ; CHECK-NEXT: // BB#0:
    176 ; CHECK-NEXT: ret
    177 
    178   %val = bitcast <2 x float> %in to <4 x i16>
    179   ret <4 x i16> %val
    180 }
    181 
    182 define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{
    183 ; CHECK: test_v2f32_to_v8i8:
    184 ; CHECK-NEXT: // BB#0:
    185 ; CHECK-NEXT: ret
    186 
    187   %val = bitcast <2 x float> %in to <8 x i8>
    188   ret <8 x i8> %val
    189 }
    190 
    191 ; From <1 x i64>
    192 
    193 define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind {
    194 ; CHECK: test_v1i64_to_v1i64:
    195 ; CHECK-NEXT: // BB#0:
    196 ; CHECK-NEXT: ret
    197 
    198   %val = bitcast <1 x i64> %in to <1 x i64>
    199   ret <1 x i64> %val
    200 }
    201 
    202 define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind {
    203 ; CHECK: test_v1i64_to_v2i32:
    204 ; CHECK-NEXT: // BB#0:
    205 ; CHECK-NEXT: ret
    206 
    207   %val = bitcast <1 x i64> %in to <2 x i32>
    208   ret <2 x i32> %val
    209 }
    210 
    211 define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{
    212 ; CHECK: test_v1i64_to_v2f32:
    213 ; CHECK-NEXT: // BB#0:
    214 ; CHECK-NEXT: ret
    215 
    216   %val = bitcast <1 x i64> %in to <2 x float>
    217   ret <2 x float> %val
    218 }
    219 
    220 define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{
    221 ; CHECK: test_v1i64_to_v4i16:
    222 ; CHECK-NEXT: // BB#0:
    223 ; CHECK-NEXT: ret
    224 
    225   %val = bitcast <1 x i64> %in to <4 x i16>
    226   ret <4 x i16> %val
    227 }
    228 
    229 define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{
    230 ; CHECK: test_v1i64_to_v8i8:
    231 ; CHECK-NEXT: // BB#0:
    232 ; CHECK-NEXT: ret
    233 
    234   %val = bitcast <1 x i64> %in to <8 x i8>
    235   ret <8 x i8> %val
    236 }
    237 
    238 
    239 ; From <16 x i8>
    240 
    241 define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind {
    242 ; CHECK: test_v16i8_to_v2f64:
    243 ; CHECK-NEXT: // BB#0:
    244 ; CHECK-NEXT: ret
    245 
    246   %val = bitcast <16 x i8> %in to <2 x double>
    247   ret <2 x double> %val
    248 }
    249 
    250 define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind {
    251 ; CHECK: test_v16i8_to_v2i64:
    252 ; CHECK-NEXT: // BB#0:
    253 ; CHECK-NEXT: ret
    254 
    255   %val = bitcast <16 x i8> %in to <2 x i64>
    256   ret <2 x i64> %val
    257 }
    258 
    259 define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind {
    260 ; CHECK: test_v16i8_to_v4i32:
    261 ; CHECK-NEXT: // BB#0:
    262 ; CHECK-NEXT: ret
    263 
    264   %val = bitcast <16 x i8> %in to <4 x i32>
    265   ret <4 x i32> %val
    266 }
    267 
    268 define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{
    269 ; CHECK: test_v16i8_to_v2f32:
    270 ; CHECK-NEXT: // BB#0:
    271 ; CHECK-NEXT: ret
    272 
    273   %val = bitcast <16 x i8> %in to <4 x float>
    274   ret <4 x float> %val
    275 }
    276 
    277 define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{
    278 ; CHECK: test_v16i8_to_v8i16:
    279 ; CHECK-NEXT: // BB#0:
    280 ; CHECK-NEXT: ret
    281 
    282   %val = bitcast <16 x i8> %in to <8 x i16>
    283   ret <8 x i16> %val
    284 }
    285 
    286 define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{
    287 ; CHECK: test_v16i8_to_v16i8:
    288 ; CHECK-NEXT: // BB#0:
    289 ; CHECK-NEXT: ret
    290 
    291   %val = bitcast <16 x i8> %in to <16 x i8>
    292   ret <16 x i8> %val
    293 }
    294 
    295 ; From <8 x i16>
    296 
    297 define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind {
    298 ; CHECK: test_v8i16_to_v2f64:
    299 ; CHECK-NEXT: // BB#0:
    300 ; CHECK-NEXT: ret
    301 
    302   %val = bitcast <8 x i16> %in to <2 x double>
    303   ret <2 x double> %val
    304 }
    305 
    306 define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind {
    307 ; CHECK: test_v8i16_to_v2i64:
    308 ; CHECK-NEXT: // BB#0:
    309 ; CHECK-NEXT: ret
    310 
    311   %val = bitcast <8 x i16> %in to <2 x i64>
    312   ret <2 x i64> %val
    313 }
    314 
    315 define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind {
    316 ; CHECK: test_v8i16_to_v4i32:
    317 ; CHECK-NEXT: // BB#0:
    318 ; CHECK-NEXT: ret
    319 
    320   %val = bitcast <8 x i16> %in to <4 x i32>
    321   ret <4 x i32> %val
    322 }
    323 
    324 define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{
    325 ; CHECK: test_v8i16_to_v2f32:
    326 ; CHECK-NEXT: // BB#0:
    327 ; CHECK-NEXT: ret
    328 
    329   %val = bitcast <8 x i16> %in to <4 x float>
    330   ret <4 x float> %val
    331 }
    332 
    333 define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{
    334 ; CHECK: test_v8i16_to_v8i16:
    335 ; CHECK-NEXT: // BB#0:
    336 ; CHECK-NEXT: ret
    337 
    338   %val = bitcast <8 x i16> %in to <8 x i16>
    339   ret <8 x i16> %val
    340 }
    341 
    342 define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{
    343 ; CHECK: test_v8i16_to_v16i8:
    344 ; CHECK-NEXT: // BB#0:
    345 ; CHECK-NEXT: ret
    346 
    347   %val = bitcast <8 x i16> %in to <16 x i8>
    348   ret <16 x i8> %val
    349 }
    350 
    351 ; From <4 x i32>
    352 
    353 define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind {
    354 ; CHECK: test_v4i32_to_v2f64:
    355 ; CHECK-NEXT: // BB#0:
    356 ; CHECK-NEXT: ret
    357 
    358   %val = bitcast <4 x i32> %in to <2 x double>
    359   ret <2 x double> %val
    360 }
    361 
    362 define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind {
    363 ; CHECK: test_v4i32_to_v2i64:
    364 ; CHECK-NEXT: // BB#0:
    365 ; CHECK-NEXT: ret
    366 
    367   %val = bitcast <4 x i32> %in to <2 x i64>
    368   ret <2 x i64> %val
    369 }
    370 
    371 define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind {
    372 ; CHECK: test_v4i32_to_v4i32:
    373 ; CHECK-NEXT: // BB#0:
    374 ; CHECK-NEXT: ret
    375 
    376   %val = bitcast <4 x i32> %in to <4 x i32>
    377   ret <4 x i32> %val
    378 }
    379 
    380 define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{
    381 ; CHECK: test_v4i32_to_v2f32:
    382 ; CHECK-NEXT: // BB#0:
    383 ; CHECK-NEXT: ret
    384 
    385   %val = bitcast <4 x i32> %in to <4 x float>
    386   ret <4 x float> %val
    387 }
    388 
    389 define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{
    390 ; CHECK: test_v4i32_to_v8i16:
    391 ; CHECK-NEXT: // BB#0:
    392 ; CHECK-NEXT: ret
    393 
    394   %val = bitcast <4 x i32> %in to <8 x i16>
    395   ret <8 x i16> %val
    396 }
    397 
    398 define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{
    399 ; CHECK: test_v4i32_to_v16i8:
    400 ; CHECK-NEXT: // BB#0:
    401 ; CHECK-NEXT: ret
    402 
    403   %val = bitcast <4 x i32> %in to <16 x i8>
    404   ret <16 x i8> %val
    405 }
    406 
    407 ; From <4 x float>
    408 
    409 define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind {
    410 ; CHECK: test_v4f32_to_v2f64:
    411 ; CHECK-NEXT: // BB#0:
    412 ; CHECK-NEXT: ret
    413 
    414   %val = bitcast <4 x float> %in to <2 x double>
    415   ret <2 x double> %val
    416 }
    417 
    418 define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind {
    419 ; CHECK: test_v4f32_to_v2i64:
    420 ; CHECK-NEXT: // BB#0:
    421 ; CHECK-NEXT: ret
    422 
    423   %val = bitcast <4 x float> %in to <2 x i64>
    424   ret <2 x i64> %val
    425 }
    426 
    427 define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind {
    428 ; CHECK: test_v4f32_to_v4i32:
    429 ; CHECK-NEXT: // BB#0:
    430 ; CHECK-NEXT: ret
    431 
    432   %val = bitcast <4 x float> %in to <4 x i32>
    433   ret <4 x i32> %val
    434 }
    435 
    436 define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{
    437 ; CHECK: test_v4f32_to_v4f32:
    438 ; CHECK-NEXT: // BB#0:
    439 ; CHECK-NEXT: ret
    440 
    441   %val = bitcast <4 x float> %in to <4 x float>
    442   ret <4 x float> %val
    443 }
    444 
    445 define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{
    446 ; CHECK: test_v4f32_to_v8i16:
    447 ; CHECK-NEXT: // BB#0:
    448 ; CHECK-NEXT: ret
    449 
    450   %val = bitcast <4 x float> %in to <8 x i16>
    451   ret <8 x i16> %val
    452 }
    453 
    454 define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{
    455 ; CHECK: test_v4f32_to_v16i8:
    456 ; CHECK-NEXT: // BB#0:
    457 ; CHECK-NEXT: ret
    458 
    459   %val = bitcast <4 x float> %in to <16 x i8>
    460   ret <16 x i8> %val
    461 }
    462 
    463 ; From <2 x i64>
    464 
    465 define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind {
    466 ; CHECK: test_v2i64_to_v2f64:
    467 ; CHECK-NEXT: // BB#0:
    468 ; CHECK-NEXT: ret
    469 
    470   %val = bitcast <2 x i64> %in to <2 x double>
    471   ret <2 x double> %val
    472 }
    473 
    474 define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind {
    475 ; CHECK: test_v2i64_to_v2i64:
    476 ; CHECK-NEXT: // BB#0:
    477 ; CHECK-NEXT: ret
    478 
    479   %val = bitcast <2 x i64> %in to <2 x i64>
    480   ret <2 x i64> %val
    481 }
    482 
    483 define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind {
    484 ; CHECK: test_v2i64_to_v4i32:
    485 ; CHECK-NEXT: // BB#0:
    486 ; CHECK-NEXT: ret
    487 
    488   %val = bitcast <2 x i64> %in to <4 x i32>
    489   ret <4 x i32> %val
    490 }
    491 
    492 define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{
    493 ; CHECK: test_v2i64_to_v4f32:
    494 ; CHECK-NEXT: // BB#0:
    495 ; CHECK-NEXT: ret
    496 
    497   %val = bitcast <2 x i64> %in to <4 x float>
    498   ret <4 x float> %val
    499 }
    500 
    501 define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{
    502 ; CHECK: test_v2i64_to_v8i16:
    503 ; CHECK-NEXT: // BB#0:
    504 ; CHECK-NEXT: ret
    505 
    506   %val = bitcast <2 x i64> %in to <8 x i16>
    507   ret <8 x i16> %val
    508 }
    509 
    510 define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{
    511 ; CHECK: test_v2i64_to_v16i8:
    512 ; CHECK-NEXT: // BB#0:
    513 ; CHECK-NEXT: ret
    514 
    515   %val = bitcast <2 x i64> %in to <16 x i8>
    516   ret <16 x i8> %val
    517 }
    518 
    519 ; From <2 x double>
    520 
    521 define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind {
    522 ; CHECK: test_v2f64_to_v2f64:
    523 ; CHECK-NEXT: // BB#0:
    524 ; CHECK-NEXT: ret
    525 
    526   %val = bitcast <2 x double> %in to <2 x double>
    527   ret <2 x double> %val
    528 }
    529 
    530 define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind {
    531 ; CHECK: test_v2f64_to_v2i64:
    532 ; CHECK-NEXT: // BB#0:
    533 ; CHECK-NEXT: ret
    534 
    535   %val = bitcast <2 x double> %in to <2 x i64>
    536   ret <2 x i64> %val
    537 }
    538 
    539 define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind {
    540 ; CHECK: test_v2f64_to_v4i32:
    541 ; CHECK-NEXT: // BB#0:
    542 ; CHECK-NEXT: ret
    543 
    544   %val = bitcast <2 x double> %in to <4 x i32>
    545   ret <4 x i32> %val
    546 }
    547 
    548 define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{
    549 ; CHECK: test_v2f64_to_v4f32:
    550 ; CHECK-NEXT: // BB#0:
    551 ; CHECK-NEXT: ret
    552 
    553   %val = bitcast <2 x double> %in to <4 x float>
    554   ret <4 x float> %val
    555 }
    556 
    557 define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{
    558 ; CHECK: test_v2f64_to_v8i16:
    559 ; CHECK-NEXT: // BB#0:
    560 ; CHECK-NEXT: ret
    561 
    562   %val = bitcast <2 x double> %in to <8 x i16>
    563   ret <8 x i16> %val
    564 }
    565 
    566 define <16 x i8> @test_v2f64_to_v16i8(<2 x double> %in) nounwind{
    567 ; CHECK: test_v2f64_to_v16i8:
    568 ; CHECK-NEXT: // BB#0:
    569 ; CHECK-NEXT: ret
    570 
    571   %val = bitcast <2 x double> %in to <16 x i8>
    572   ret <16 x i8> %val
    573 }
    574 
    575