1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) { 4 ; CHECK-LABEL: test_vext_s8: 5 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}} 6 entry: 7 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> 8 ret <8 x i8> %vext 9 } 10 11 define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) { 12 ; CHECK-LABEL: test_vext_s16: 13 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}} 14 entry: 15 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 16 ret <4 x i16> %vext 17 } 18 19 define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) { 20 ; CHECK-LABEL: test_vext_s32: 21 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}} 22 entry: 23 %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2> 24 ret <2 x i32> %vext 25 } 26 27 define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) { 28 ; CHECK-LABEL: test_vext_s64: 29 entry: 30 %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0> 31 ret <1 x i64> %vext 32 } 33 34 define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) { 35 ; CHECK-LABEL: test_vextq_s8: 36 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}} 37 entry: 38 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> 39 ret <16 x i8> %vext 40 } 41 42 define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) { 43 ; CHECK-LABEL: test_vextq_s16: 44 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}} 45 entry: 46 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> 47 ret <8 x i16> %vext 48 } 49 50 define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) { 51 ; CHECK-LABEL: test_vextq_s32: 52 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}} 53 entry: 54 %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4> 55 ret <4 x i32> %vext 56 } 57 58 define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) { 59 ; CHECK-LABEL: test_vextq_s64: 60 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}} 61 entry: 62 %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2> 63 ret <2 x i64> %vext 64 } 65 66 define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) { 67 ; CHECK-LABEL: test_vext_u8: 68 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}} 69 entry: 70 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> 71 ret <8 x i8> %vext 72 } 73 74 define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) { 75 ; CHECK-LABEL: test_vext_u16: 76 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}} 77 entry: 78 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 79 ret <4 x i16> %vext 80 } 81 82 define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) { 83 ; CHECK-LABEL: test_vext_u32: 84 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}} 85 entry: 86 %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2> 87 ret <2 x i32> %vext 88 } 89 90 define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) { 91 ; CHECK-LABEL: test_vext_u64: 92 entry: 93 %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0> 94 ret <1 x i64> %vext 95 } 96 97 define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) { 98 ; CHECK-LABEL: test_vextq_u8: 99 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}} 100 entry: 101 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> 102 ret <16 x i8> %vext 103 } 104 105 define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) { 106 ; CHECK-LABEL: test_vextq_u16: 107 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}} 108 entry: 109 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> 110 ret <8 x i16> %vext 111 } 112 113 define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) { 114 ; CHECK-LABEL: test_vextq_u32: 115 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}} 116 entry: 117 %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4> 118 ret <4 x i32> %vext 119 } 120 121 define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) { 122 ; CHECK-LABEL: test_vextq_u64: 123 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}} 124 entry: 125 %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2> 126 ret <2 x i64> %vext 127 } 128 129 define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) { 130 ; CHECK-LABEL: test_vext_f32: 131 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}} 132 entry: 133 %vext = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 2> 134 ret <2 x float> %vext 135 } 136 137 define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) { 138 ; CHECK-LABEL: test_vext_f64: 139 entry: 140 %vext = shufflevector <1 x double> %a, <1 x double> %b, <1 x i32> <i32 0> 141 ret <1 x double> %vext 142 } 143 144 define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) { 145 ; CHECK-LABEL: test_vextq_f32: 146 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}} 147 entry: 148 %vext = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4> 149 ret <4 x float> %vext 150 } 151 152 define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) { 153 ; CHECK-LABEL: test_vextq_f64: 154 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}} 155 entry: 156 %vext = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2> 157 ret <2 x double> %vext 158 } 159 160 define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) { 161 ; CHECK-LABEL: test_vext_p8: 162 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}} 163 entry: 164 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> 165 ret <8 x i8> %vext 166 } 167 168 define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) { 169 ; CHECK-LABEL: test_vext_p16: 170 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}} 171 entry: 172 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 173 ret <4 x i16> %vext 174 } 175 176 define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) { 177 ; CHECK-LABEL: test_vextq_p8: 178 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}} 179 entry: 180 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> 181 ret <16 x i8> %vext 182 } 183 184 define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) { 185 ; CHECK-LABEL: test_vextq_p16: 186 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}} 187 entry: 188 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> 189 ret <8 x i16> %vext 190 } 191 192 define <8 x i8> @test_undef_vext_s8(<8 x i8> %a) { 193 ; CHECK-LABEL: test_undef_vext_s8: 194 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}} 195 entry: 196 %vext = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 10, i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> 197 ret <8 x i8> %vext 198 } 199 200 define <16 x i8> @test_undef_vextq_s8(<16 x i8> %a) { 201 ; CHECK-LABEL: test_undef_vextq_s8: 202 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}} 203 entry: 204 %vext = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 20, i32 20, i32 20, i32 20, i32 20> 205 ret <16 x i8> %vext 206 } 207 208 define <4 x i16> @test_undef_vext_s16(<4 x i16> %a) { 209 ; CHECK-LABEL: test_undef_vext_s16: 210 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}} 211 entry: 212 %vext = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5> 213 ret <4 x i16> %vext 214 } 215 216 define <8 x i16> @test_undef_vextq_s16(<8 x i16> %a) { 217 ; CHECK-LABEL: test_undef_vextq_s16: 218 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}} 219 entry: 220 %vext = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> 221 ret <8 x i16> %vext 222 } 223
