1 ; RUN: llc -mcpu=cyclone -debug-only=misched < %s 2>&1 | FileCheck %s 2 3 ; REQUIRES: asserts 4 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6 target triple = "arm64-apple-ios7.0.0" 7 8 define void @caller2(i8* %a0, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9) { 9 entry: 10 tail call void @callee2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a0) 11 ret void 12 } 13 14 declare void @callee2(i8*, i8*, i8*, i8*, i8*, 15 i8*, i8*, i8*, i8*, i8*) 16 17 ; Make sure there is a dependence between the load and store to the same stack 18 ; location during a tail call. Tail calls clobber the incoming argument area and 19 ; therefore it is not safe to assume argument locations are invariant. 20 ; PR23459 has a test case that we where miscompiling because of this at the 21 ; time. 22 23 ; CHECK: Frame Objects 24 ; CHECK: fi#-4: {{.*}} fixed, at location [SP+8] 25 ; CHECK: fi#-3: {{.*}} fixed, at location [SP] 26 ; CHECK: fi#-2: {{.*}} fixed, at location [SP+8] 27 ; CHECK: fi#-1: {{.*}} fixed, at location [SP] 28 29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1> 30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2> 31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4> 32 ; CHECK: STRXui [[VRB]], <fi#-3> 33 34 ; Make sure that there is an dependence edge between fi#-2 and fi#-4. 35 ; Without this edge the scheduler would be free to move the store accross the load. 36 37 ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2> 38 ; CHECK-NOT: SU 39 ; CHECK: Successors: 40 ; CHECK: ch SU([[DEPSTOREB:.*]]): Latency=0 41 ; CHECK: ch SU([[DEPSTOREA:.*]]): Latency=0 42 43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4> 44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3> 45
