1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI 3 4 ;CHECK-LABEL: {{^}}buffer_load: 5 ;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 6 ;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc 7 ;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc 8 ;CHECK: s_waitcnt 9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { 10 main_body: 11 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0) 12 %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0) 13 %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1) 14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 15 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 16 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 17 ret {<4 x float>, <4 x float>, <4 x float>} %r2 18 } 19 20 ;CHECK-LABEL: {{^}}buffer_load_immoffs: 21 ;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:42 22 ;CHECK: s_waitcnt 23 define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { 24 main_body: 25 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0) 26 ret <4 x float> %data 27 } 28 29 ;CHECK-LABEL: {{^}}buffer_load_immoffs_large: 30 ;SICI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 offen 31 ;VI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1fff 32 ;VI: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:1 33 ;CHECK: s_waitcnt 34 define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { 35 main_body: 36 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0) 37 ret <4 x float> %data 38 } 39 40 ;CHECK-LABEL: {{^}}buffer_load_idx: 41 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen 42 ;CHECK: s_waitcnt 43 define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) { 44 main_body: 45 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0) 46 ret <4 x float> %data 47 } 48 49 ;CHECK-LABEL: {{^}}buffer_load_ofs: 50 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen 51 ;CHECK: s_waitcnt 52 define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { 53 main_body: 54 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0) 55 ret <4 x float> %data 56 } 57 58 ;CHECK-LABEL: {{^}}buffer_load_ofs_imm: 59 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:58 60 ;CHECK: s_waitcnt 61 define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { 62 main_body: 63 %ofs = add i32 %1, 58 64 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0) 65 ret <4 x float> %data 66 } 67 68 ;CHECK-LABEL: {{^}}buffer_load_both: 69 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen 70 ;CHECK: s_waitcnt 71 define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) { 72 main_body: 73 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0) 74 ret <4 x float> %data 75 } 76 77 ;CHECK-LABEL: {{^}}buffer_load_both_reversed: 78 ;CHECK: v_mov_b32_e32 v2, v0 79 ;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen 80 ;CHECK: s_waitcnt 81 define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) { 82 main_body: 83 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0) 84 ret <4 x float> %data 85 } 86 87 ;CHECK-LABEL: {{^}}buffer_load_x1: 88 ;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen 89 ;CHECK: s_waitcnt 90 define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 91 main_body: 92 %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) 93 ret float %data 94 } 95 96 ;CHECK-LABEL: {{^}}buffer_load_x2: 97 ;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen 98 ;CHECK: s_waitcnt 99 define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 100 main_body: 101 %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) 102 ret <2 x float> %data 103 } 104 105 ;CHECK-LABEL: {{^}}buffer_load_negative_offset: 106 ;CHECK: v_add_i32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0 107 ;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen 108 define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) { 109 main_body: 110 %ofs.1 = add i32 %ofs, -16 111 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i1 0, i1 0) 112 ret <4 x float> %data 113 } 114 115 declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 116 declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0 117 declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0 118 119 attributes #0 = { nounwind readonly } 120
