1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s 2 ; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s 3 4 ; FIXME: The register allocator / scheduler should be able to avoid these hazards. 5 6 ; VI-LABEL: {{^}}dpp_test: 7 ; VI: v_mov_b32_e32 v0, s{{[0-9]+}} 8 ; VI: s_nop 1 9 ; VI: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11] 10 define void @dpp_test(i32 addrspace(1)* %out, i32 %in) { 11 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0 12 store i32 %tmp0, i32 addrspace(1)* %out 13 ret void 14 } 15 16 ; VI-LABEL: {{^}}dpp_wait_states: 17 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}} 18 ; VI: s_nop 1 19 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 20 ; VI: s_nop 1 21 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 22 define void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) { 23 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0 24 %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0 25 store i32 %tmp1, i32 addrspace(1)* %out 26 ret void 27 } 28 29 ; VI-LABEL: {{^}}dpp_first_in_bb: 30 ; VI: ; %endif 31 ; VI-OPT: s_mov_b32 32 ; VI-OPT: s_mov_b32 33 ; VI-NOOPT: s_nop 1 34 ; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 35 ; VI: s_nop 1 36 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 37 ; VI: s_nop 1 38 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 39 define void @dpp_first_in_bb(float addrspace(1)* %out, float addrspace(1)* %in, float %cond, float %a, float %b) { 40 %cmp = fcmp oeq float %cond, 0.0 41 br i1 %cmp, label %if, label %else 42 43 if: 44 %out_val = load float, float addrspace(1)* %out 45 %if_val = fadd float %a, %out_val 46 br label %endif 47 48 else: 49 %in_val = load float, float addrspace(1)* %in 50 %else_val = fadd float %b, %in_val 51 br label %endif 52 53 endif: 54 %val = phi float [%if_val, %if], [%else_val, %else] 55 %val_i32 = bitcast float %val to i32 56 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %val_i32, i32 1, i32 1, i32 1, i1 1) #0 57 %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0 58 %tmp2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp1, i32 1, i32 1, i32 1, i1 1) #0 59 %tmp_float = bitcast i32 %tmp2 to float 60 store float %tmp_float, float addrspace(1)* %out 61 ret void 62 } 63 64 declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #0 65 66 attributes #0 = { nounwind readnone convergent } 67
