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      1 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 | FileCheck %s
      2 ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi | FileCheck %s
      3 ; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi | FileCheck %s
      4 
      5 ; CHECK-LABEL: f0:
      6 ; CHECK-NOT: ldrexd
      7 define i64 @f0(i64* %p) nounwind readonly {
      8 entry:
      9   %0 = load atomic i64, i64* %p seq_cst, align 8
     10   ret i64 %0
     11 }
     12 
     13 ; CHECK-LABEL: f1:
     14 ; CHECK-NOT: strexd
     15 define void @f1(i64* %p) nounwind readonly {
     16 entry:
     17   store atomic i64 0, i64* %p seq_cst, align 8
     18   ret void
     19 }
     20 
     21 ; CHECK-LABEL: f2:
     22 ; CHECK-NOT: ldrexd
     23 ; CHECK-NOT: strexd
     24 define i64 @f2(i64* %p) nounwind readonly {
     25 entry:
     26   %0 = atomicrmw add i64* %p, i64 1 seq_cst
     27   ret i64 %0
     28 }
     29 
     30 ; CHECK-LABEL: f3:
     31 ; CHECK: ldr
     32 define i32 @f3(i32* %p) nounwind readonly {
     33 entry:
     34   %0 = load atomic i32, i32* %p seq_cst, align 4
     35   ret i32 %0
     36 }
     37 
     38 ; CHECK-LABEL: f4:
     39 ; CHECK: ldrb
     40 define i8 @f4(i8* %p) nounwind readonly {
     41 entry:
     42   %0 = load atomic i8, i8* %p seq_cst, align 4
     43   ret i8 %0
     44 }
     45 
     46 ; CHECK-LABEL: f5:
     47 ; CHECK: str
     48 define void @f5(i32* %p) nounwind readonly {
     49 entry:
     50   store atomic i32 0, i32* %p seq_cst, align 4
     51   ret void
     52 }
     53 
     54 ; CHECK-LABEL: f6:
     55 ; CHECK: ldrex
     56 ; CHECK: strex
     57 define i32 @f6(i32* %p) nounwind readonly {
     58 entry:
     59   %0 = atomicrmw add i32* %p, i32 1 seq_cst
     60   ret i32 %0
     61 }
     62