1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 2 ; RUN: -check-prefixes=ALL,GP32 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 4 ; RUN: -check-prefixes=ALL,GP32 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 6 ; RUN: -check-prefixes=ALL,GP32 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 8 ; RUN: -check-prefixes=ALL,GP32 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 10 ; RUN: -check-prefixes=ALL,GP32 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 12 ; RUN: -check-prefixes=ALL,GP32 13 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 14 ; RUN: -check-prefixes=ALL,GP64 15 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 16 ; RUN: -check-prefixes=ALL,GP64 17 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 18 ; RUN: -check-prefixes=ALL,GP64 19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 20 ; RUN: -check-prefixes=ALL,GP64 21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 22 ; RUN: -check-prefixes=ALL,GP64 23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 24 ; RUN: -check-prefixes=ALL,GP64 25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 26 ; RUN: -check-prefixes=ALL,GP64 27 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ 28 ; RUN: -check-prefixes=ALL,MM,MM32 29 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ 30 ; RUN: -check-prefixes=ALL,MM,MM32 31 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ 32 ; RUN: -check-prefixes=ALL,MM,MM64 33 34 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { 35 entry: 36 ; ALL-LABEL: and_i1: 37 38 ; GP32: and $2, $4, $5 39 40 ; GP64: and $2, $4, $5 41 42 ; MM: and16 $[[T0:[0-9]+]], $5 43 ; MM: move $2, $[[T0]] 44 45 %r = and i1 %a, %b 46 ret i1 %r 47 } 48 49 define signext i8 @and_i8(i8 signext %a, i8 signext %b) { 50 entry: 51 ; ALL-LABEL: and_i8: 52 53 ; GP32: and $2, $4, $5 54 55 ; GP64: and $2, $4, $5 56 57 ; MM: and16 $[[T0:[0-9]+]], $5 58 ; MM: move $2, $[[T0]] 59 60 %r = and i8 %a, %b 61 ret i8 %r 62 } 63 64 define signext i16 @and_i16(i16 signext %a, i16 signext %b) { 65 entry: 66 ; ALL-LABEL: and_i16: 67 68 ; GP32: and $2, $4, $5 69 70 ; GP64: and $2, $4, $5 71 72 ; MM: and16 $[[T0:[0-9]+]], $5 73 ; MM: move $2, $[[T0]] 74 75 %r = and i16 %a, %b 76 ret i16 %r 77 } 78 79 define signext i32 @and_i32(i32 signext %a, i32 signext %b) { 80 entry: 81 ; ALL-LABEL: and_i32: 82 83 ; GP32: and $2, $4, $5 84 85 ; GP64: and $[[T0:[0-9]+]], $4, $5 86 ; GP64: sll $2, $[[T0]], 0 87 88 ; MM32: and16 $[[T0:[0-9]+]], $5 89 ; MM32: move $2, $[[T0]] 90 91 ; MM64: and $[[T0:[0-9]+]], $4, $5 92 ; MM64: sll $2, $[[T0]], 0 93 94 %r = and i32 %a, %b 95 ret i32 %r 96 } 97 98 define signext i64 @and_i64(i64 signext %a, i64 signext %b) { 99 entry: 100 ; ALL-LABEL: and_i64: 101 102 ; GP32: and $2, $4, $6 103 ; GP32: and $3, $5, $7 104 105 ; GP64: and $2, $4, $5 106 107 ; MM32: and16 $[[T0:[0-9]+]], $6 108 ; MM32: and16 $[[T1:[0-9]+]], $7 109 ; MM32: move $2, $[[T0]] 110 ; MM32: move $3, $[[T1]] 111 112 ; MM64: and $2, $4, $5 113 114 %r = and i64 %a, %b 115 ret i64 %r 116 } 117 118 define signext i128 @and_i128(i128 signext %a, i128 signext %b) { 119 entry: 120 ; ALL-LABEL: and_i128: 121 122 ; GP32: lw $[[T0:[0-9]+]], 24($sp) 123 ; GP32: lw $[[T1:[0-9]+]], 20($sp) 124 ; GP32: lw $[[T2:[0-9]+]], 16($sp) 125 ; GP32: and $2, $4, $[[T2]] 126 ; GP32: and $3, $5, $[[T1]] 127 ; GP32: and $4, $6, $[[T0]] 128 ; GP32: lw $[[T3:[0-9]+]], 28($sp) 129 ; GP32: and $5, $7, $[[T3]] 130 131 ; GP64: and $2, $4, $6 132 ; GP64: and $3, $5, $7 133 134 ; MM32: lw $[[T0:[0-9]+]], 20($sp) 135 ; MM32: lw $[[T1:[0-9]+]], 16($sp) 136 ; MM32: and16 $[[T1]], $4 137 ; MM32: and16 $[[T0]], $5 138 ; MM32: lw $[[T2:[0-9]+]], 24($sp) 139 ; MM32: and16 $[[T2]], $6 140 ; MM32: lw $[[T3:[0-9]+]], 28($sp) 141 ; MM32: and16 $[[T3]], $7 142 143 ; MM64: and $2, $4, $6 144 ; MM64: and $3, $5, $7 145 146 %r = and i128 %a, %b 147 ret i128 %r 148 } 149 150 define signext i1 @and_i1_4(i1 signext %b) { 151 entry: 152 ; ALL-LABEL: and_i1_4: 153 154 ; GP32: addiu $2, $zero, 0 155 156 ; GP64: addiu $2, $zero, 0 157 158 ; MM: lui $2, 0 159 160 %r = and i1 4, %b 161 ret i1 %r 162 } 163 164 define signext i8 @and_i8_4(i8 signext %b) { 165 entry: 166 ; ALL-LABEL: and_i8_4: 167 168 ; GP32: andi $2, $4, 4 169 170 ; GP64: andi $2, $4, 4 171 172 ; MM: andi16 $2, $4, 4 173 174 %r = and i8 4, %b 175 ret i8 %r 176 } 177 178 define signext i16 @and_i16_4(i16 signext %b) { 179 entry: 180 ; ALL-LABEL: and_i16_4: 181 182 ; GP32: andi $2, $4, 4 183 184 ; GP64: andi $2, $4, 4 185 186 ; MM: andi16 $2, $4, 4 187 188 %r = and i16 4, %b 189 ret i16 %r 190 } 191 192 define signext i32 @and_i32_4(i32 signext %b) { 193 entry: 194 ; ALL-LABEL: and_i32_4: 195 196 ; GP32: andi $2, $4, 4 197 198 ; GP64: andi $2, $4, 4 199 200 ; MM: andi16 $2, $4, 4 201 202 %r = and i32 4, %b 203 ret i32 %r 204 } 205 206 define signext i64 @and_i64_4(i64 signext %b) { 207 entry: 208 ; ALL-LABEL: and_i64_4: 209 210 ; GP32: andi $3, $5, 4 211 ; GP32: addiu $2, $zero, 0 212 213 ; GP64: andi $2, $4, 4 214 215 ; MM32: andi16 $3, $5, 4 216 ; MM32: lui $2, 0 217 218 ; MM64: andi $2, $4, 4 219 220 %r = and i64 4, %b 221 ret i64 %r 222 } 223 224 define signext i128 @and_i128_4(i128 signext %b) { 225 entry: 226 ; ALL-LABEL: and_i128_4: 227 228 ; GP32: andi $5, $7, 4 229 ; GP32: addiu $2, $zero, 0 230 ; GP32: addiu $3, $zero, 0 231 ; GP32: addiu $4, $zero, 0 232 233 ; GP64: andi $3, $5, 4 234 ; GP64: daddiu $2, $zero, 0 235 236 ; MM32: andi16 $5, $7, 4 237 ; MM32: lui $2, 0 238 ; MM32: lui $3, 0 239 ; MM32: lui $4, 0 240 241 ; MM64: andi $3, $5, 4 242 ; MM64: daddiu $2, $zero, 0 243 244 %r = and i128 4, %b 245 ret i128 %r 246 } 247 248 define signext i1 @and_i1_31(i1 signext %b) { 249 entry: 250 ; ALL-LABEL: and_i1_31: 251 252 ; ALL: move $2, $4 253 254 %r = and i1 31, %b 255 ret i1 %r 256 } 257 258 define signext i8 @and_i8_31(i8 signext %b) { 259 entry: 260 ; ALL-LABEL: and_i8_31: 261 262 ; GP32: andi $2, $4, 31 263 264 ; GP64: andi $2, $4, 31 265 266 ; MM: andi16 $2, $4, 31 267 268 %r = and i8 31, %b 269 ret i8 %r 270 } 271 272 define signext i16 @and_i16_31(i16 signext %b) { 273 entry: 274 ; ALL-LABEL: and_i16_31: 275 276 ; GP32: andi $2, $4, 31 277 278 ; GP64: andi $2, $4, 31 279 280 ; MM: andi16 $2, $4, 31 281 282 %r = and i16 31, %b 283 ret i16 %r 284 } 285 286 define signext i32 @and_i32_31(i32 signext %b) { 287 entry: 288 ; ALL-LABEL: and_i32_31: 289 290 ; GP32: andi $2, $4, 31 291 292 ; GP64: andi $2, $4, 31 293 294 ; MM: andi16 $2, $4, 31 295 296 %r = and i32 31, %b 297 ret i32 %r 298 } 299 300 define signext i64 @and_i64_31(i64 signext %b) { 301 entry: 302 ; ALL-LABEL: and_i64_31: 303 304 ; GP32: andi $3, $5, 31 305 ; GP32: addiu $2, $zero, 0 306 307 ; GP64: andi $2, $4, 31 308 309 ; MM32: andi16 $3, $5, 31 310 ; MM32: lui $2, 0 311 312 ; MM64: andi $2, $4, 31 313 314 %r = and i64 31, %b 315 ret i64 %r 316 } 317 318 define signext i128 @and_i128_31(i128 signext %b) { 319 entry: 320 ; ALL-LABEL: and_i128_31: 321 322 ; GP32: andi $5, $7, 31 323 ; GP32: addiu $2, $zero, 0 324 ; GP32: addiu $3, $zero, 0 325 ; GP32: addiu $4, $zero, 0 326 327 ; GP64: andi $3, $5, 31 328 ; GP64: daddiu $2, $zero, 0 329 330 ; MM32: andi16 $5, $7, 31 331 ; MM32: lui $2, 0 332 ; MM32: lui $3, 0 333 ; MM32: lui $4, 0 334 335 ; MM64: andi $3, $5, 31 336 ; MM64: daddiu $2, $zero, 0 337 338 %r = and i128 31, %b 339 ret i128 %r 340 } 341 342 define signext i1 @and_i1_255(i1 signext %b) { 343 entry: 344 ; ALL-LABEL: and_i1_255: 345 346 ; ALL: move $2, $4 347 348 %r = and i1 255, %b 349 ret i1 %r 350 } 351 352 define signext i8 @and_i8_255(i8 signext %b) { 353 entry: 354 ; ALL-LABEL: and_i8_255: 355 356 ; ALL: move $2, $4 357 358 %r = and i8 255, %b 359 ret i8 %r 360 } 361 362 define signext i16 @and_i16_255(i16 signext %b) { 363 entry: 364 ; ALL-LABEL: and_i16_255: 365 366 ; GP32: andi $2, $4, 255 367 368 ; GP64: andi $2, $4, 255 369 370 ; MM: andi16 $2, $4, 255 371 372 %r = and i16 255, %b 373 ret i16 %r 374 } 375 376 define signext i32 @and_i32_255(i32 signext %b) { 377 entry: 378 ; ALL-LABEL: and_i32_255: 379 380 ; GP32: andi $2, $4, 255 381 382 ; GP64: andi $2, $4, 255 383 384 ; MM: andi16 $2, $4, 255 385 386 %r = and i32 255, %b 387 ret i32 %r 388 } 389 390 define signext i64 @and_i64_255(i64 signext %b) { 391 entry: 392 ; ALL-LABEL: and_i64_255: 393 394 ; GP32: andi $3, $5, 255 395 ; GP32: addiu $2, $zero, 0 396 397 ; GP64: andi $2, $4, 255 398 399 ; MM32: andi16 $3, $5, 255 400 ; MM32: lui $2, 0 401 402 ; MM64: andi $2, $4, 255 403 404 %r = and i64 255, %b 405 ret i64 %r 406 } 407 408 define signext i128 @and_i128_255(i128 signext %b) { 409 entry: 410 ; ALL-LABEL: and_i128_255: 411 412 ; GP32: andi $5, $7, 255 413 ; GP32: addiu $2, $zero, 0 414 ; GP32: addiu $3, $zero, 0 415 ; GP32: addiu $4, $zero, 0 416 417 ; GP64: andi $3, $5, 255 418 ; GP64: daddiu $2, $zero, 0 419 420 ; MM32: andi16 $5, $7, 255 421 ; MM32: lui $2, 0 422 ; MM32: lui $3, 0 423 ; MM32: lui $4, 0 424 425 ; MM64: andi $3, $5, 255 426 ; MM64: daddiu $2, $zero, 0 427 428 %r = and i128 255, %b 429 ret i128 %r 430 } 431 432 define signext i1 @and_i1_32768(i1 signext %b) { 433 entry: 434 ; ALL-LABEL: and_i1_32768: 435 436 ; GP32: addiu $2, $zero, 0 437 438 ; GP64: addiu $2, $zero, 0 439 440 ; MM: lui $2, 0 441 442 %r = and i1 32768, %b 443 ret i1 %r 444 } 445 446 define signext i8 @and_i8_32768(i8 signext %b) { 447 entry: 448 ; ALL-LABEL: and_i8_32768: 449 450 ; GP32: addiu $2, $zero, 0 451 452 ; GP64: addiu $2, $zero, 0 453 454 ; MM: lui $2, 0 455 456 %r = and i8 32768, %b 457 ret i8 %r 458 } 459 460 define signext i16 @and_i16_32768(i16 signext %b) { 461 entry: 462 ; ALL-LABEL: and_i16_32768: 463 464 ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 465 ; GP32: and $2, $4, $[[T0]] 466 467 ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 468 ; GP64: and $2, $4, $[[T0]] 469 470 ; MM: addiu $2, $zero, -32768 471 ; MM: and16 $2, $4 472 473 %r = and i16 32768, %b 474 ret i16 %r 475 } 476 477 define signext i32 @and_i32_32768(i32 signext %b) { 478 entry: 479 ; ALL-LABEL: and_i32_32768: 480 481 ; GP32: andi $2, $4, 32768 482 483 ; GP64: andi $2, $4, 32768 484 485 ; MM: andi16 $2, $4, 32768 486 487 %r = and i32 32768, %b 488 ret i32 %r 489 } 490 491 define signext i64 @and_i64_32768(i64 signext %b) { 492 entry: 493 ; ALL-LABEL: and_i64_32768: 494 495 ; GP32: andi $3, $5, 32768 496 ; GP32: addiu $2, $zero, 0 497 498 ; GP64: andi $2, $4, 32768 499 500 ; MM32: andi16 $3, $5, 32768 501 ; MM32: lui $2, 0 502 503 ; MM64: andi $2, $4, 32768 504 505 %r = and i64 32768, %b 506 ret i64 %r 507 } 508 509 define signext i128 @and_i128_32768(i128 signext %b) { 510 entry: 511 ; ALL-LABEL: and_i128_32768: 512 513 ; GP32: andi $5, $7, 32768 514 ; GP32: addiu $2, $zero, 0 515 ; GP32: addiu $3, $zero, 0 516 ; GP32: addiu $4, $zero, 0 517 518 ; GP64: andi $3, $5, 32768 519 ; GP64: daddiu $2, $zero, 0 520 521 ; MM32: andi16 $5, $7, 32768 522 ; MM32: lui $2, 0 523 ; MM32: lui $3, 0 524 ; MM32: lui $4, 0 525 526 ; MM64: andi $3, $5, 32768 527 ; MM64: daddiu $2, $zero, 0 528 529 %r = and i128 32768, %b 530 ret i128 %r 531 } 532 533 define signext i1 @and_i1_65(i1 signext %b) { 534 entry: 535 ; ALL-LABEL: and_i1_65: 536 537 ; ALL: move $2, $4 538 539 %r = and i1 65, %b 540 ret i1 %r 541 } 542 543 define signext i8 @and_i8_65(i8 signext %b) { 544 entry: 545 ; ALL-LABEL: and_i8_65: 546 547 ; ALL: andi $2, $4, 65 548 549 %r = and i8 65, %b 550 ret i8 %r 551 } 552 553 define signext i16 @and_i16_65(i16 signext %b) { 554 entry: 555 ; ALL-LABEL: and_i16_65: 556 557 ; ALL: andi $2, $4, 65 558 559 %r = and i16 65, %b 560 ret i16 %r 561 } 562 563 define signext i32 @and_i32_65(i32 signext %b) { 564 entry: 565 ; ALL-LABEL: and_i32_65: 566 567 ; ALL: andi $2, $4, 65 568 569 %r = and i32 65, %b 570 ret i32 %r 571 } 572 573 define signext i64 @and_i64_65(i64 signext %b) { 574 entry: 575 ; ALL-LABEL: and_i64_65: 576 577 ; GP32: andi $3, $5, 65 578 ; GP32: addiu $2, $zero, 0 579 580 ; GP64: andi $2, $4, 65 581 582 ; MM32: andi $3, $5, 65 583 ; MM32: lui $2, 0 584 585 ; MM64: andi $2, $4, 65 586 587 %r = and i64 65, %b 588 ret i64 %r 589 } 590 591 define signext i128 @and_i128_65(i128 signext %b) { 592 entry: 593 ; ALL-LABEL: and_i128_65: 594 595 ; GP32: andi $5, $7, 65 596 ; GP32: addiu $2, $zero, 0 597 ; GP32: addiu $3, $zero, 0 598 ; GP32: addiu $4, $zero, 0 599 600 ; GP64: andi $3, $5, 65 601 ; GP64: daddiu $2, $zero, 0 602 603 ; MM32: andi $5, $7, 65 604 ; MM32: lui $2, 0 605 ; MM32: lui $3, 0 606 ; MM32: lui $4, 0 607 608 ; MM64: andi $3, $5, 65 609 ; MM64: daddiu $2, $zero, 0 610 611 %r = and i128 65, %b 612 ret i128 %r 613 } 614 615 define signext i1 @and_i1_256(i1 signext %b) { 616 entry: 617 ; ALL-LABEL: and_i1_256: 618 619 ; GP32: addiu $2, $zero, 0 620 621 ; GP64: addiu $2, $zero, 0 622 623 ; MM: lui $2, 0 624 625 %r = and i1 256, %b 626 ret i1 %r 627 } 628 629 define signext i8 @and_i8_256(i8 signext %b) { 630 entry: 631 ; ALL-LABEL: and_i8_256: 632 633 ; GP32: addiu $2, $zero, 0 634 635 ; GP64: addiu $2, $zero, 0 636 637 ; MM: lui $2, 0 638 639 %r = and i8 256, %b 640 ret i8 %r 641 } 642 643 define signext i16 @and_i16_256(i16 signext %b) { 644 entry: 645 ; ALL-LABEL: and_i16_256: 646 647 ; ALL: andi $2, $4, 256 648 649 %r = and i16 256, %b 650 ret i16 %r 651 } 652 653 define signext i32 @and_i32_256(i32 signext %b) { 654 entry: 655 ; ALL-LABEL: and_i32_256: 656 657 ; ALL: andi $2, $4, 256 658 659 %r = and i32 256, %b 660 ret i32 %r 661 } 662 663 define signext i64 @and_i64_256(i64 signext %b) { 664 entry: 665 ; ALL-LABEL: and_i64_256: 666 667 ; GP32: andi $3, $5, 256 668 ; GP32: addiu $2, $zero, 0 669 670 ; GP64: andi $2, $4, 256 671 672 ; MM32: andi $3, $5, 256 673 ; MM32: lui $2, 0 674 675 ; MM64: andi $2, $4, 256 676 677 %r = and i64 256, %b 678 ret i64 %r 679 } 680 681 define signext i128 @and_i128_256(i128 signext %b) { 682 entry: 683 ; ALL-LABEL: and_i128_256: 684 685 ; GP32: andi $5, $7, 256 686 ; GP32: addiu $2, $zero, 0 687 ; GP32: addiu $3, $zero, 0 688 ; GP32: addiu $4, $zero, 0 689 690 ; GP64: andi $3, $5, 256 691 ; GP64: daddiu $2, $zero, 0 692 693 ; MM32: andi $5, $7, 256 694 ; MM32: lui $2, 0 695 ; MM32: lui $3, 0 696 ; MM32: lui $4, 0 697 698 ; MM64: andi $3, $5, 256 699 ; MM64: daddiu $2, $zero, 0 700 701 %r = and i128 256, %b 702 ret i128 %r 703 } 704
