1 ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s 2 ; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s \ 3 ; RUN: | FileCheck %s -check-prefix=O32 4 ; RUN: llc -march=mipsel -mcpu=mips32r6 -force-mips-long-branch -O3 \ 5 ; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=O32-R6 6 ; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ 7 ; RUN: < %s | FileCheck %s -check-prefix=N64 8 ; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ 9 ; RUN: < %s | FileCheck %s -check-prefix=N64 10 ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \ 11 ; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=N64-R6 12 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \ 13 ; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS 14 ; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \ 15 ; RUN: | FileCheck %s -check-prefix=NACL 16 17 18 @x = external global i32 19 20 define void @test1(i32 signext %s) { 21 entry: 22 %cmp = icmp eq i32 %s, 0 23 br i1 %cmp, label %end, label %then 24 25 then: 26 store i32 1, i32* @x, align 4 27 br label %end 28 29 end: 30 ret void 31 32 33 ; First check the normal version (without long branch). beqz jumps to return, 34 ; and fallthrough block stores 1 to global variable. 35 36 ; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp) 37 ; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 38 ; CHECK: beqz $4, $[[BB0:BB[0-9_]+]] 39 ; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25 40 ; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 41 ; CHECK: addiu $[[R2:[0-9]+]], $zero, 1 42 ; CHECK: sw $[[R2]], 0($[[R1]]) 43 ; CHECK: $[[BB0]]: 44 ; CHECK: jr $ra 45 ; CHECK: nop 46 47 48 ; Check the MIPS32 version. Check that branch logic is inverted, so that the 49 ; target of the new branch (bnez) is the fallthrough block of the original 50 ; branch. Check that fallthrough block of the new branch contains long branch 51 ; expansion which at the end indirectly jumps to the target of the original 52 ; branch. 53 54 ; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp) 55 ; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 56 ; O32: bnez $4, $[[BB0:BB[0-9_]+]] 57 ; O32: addu $[[GP:[0-9]+]], $[[R0]], $25 58 59 ; Check for long branch expansion: 60 ; O32: addiu $sp, $sp, -8 61 ; O32-NEXT: sw $ra, 0($sp) 62 ; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 63 ; O32-NEXT: bal $[[BB1]] 64 ; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 65 ; O32-NEXT: $[[BB1]]: 66 ; O32-NEXT: addu $1, $ra, $1 67 ; O32-NEXT: lw $ra, 0($sp) 68 ; O32-NEXT: jr $1 69 ; O32-NEXT: addiu $sp, $sp, 8 70 71 ; O32: $[[BB0]]: 72 ; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 73 ; O32: addiu $[[R2:[0-9]+]], $zero, 1 74 ; O32: sw $[[R2]], 0($[[R1]]) 75 ; O32: $[[BB2]]: 76 ; O32: jr $ra 77 ; O32: nop 78 79 ; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the 80 ; same with the O32 prefix, we use -asm-show-inst in order to make sure that 81 ; the opcode of the MachineInst is a JALR. 82 ; O32-R6: JALR 83 84 ; Check the MIPS64 version. 85 86 ; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1))) 87 ; N64: bnez $4, $[[BB0:BB[0-9_]+]] 88 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25 89 90 ; Check for long branch expansion: 91 ; N64: daddiu $sp, $sp, -16 92 ; N64-NEXT: sd $ra, 0($sp) 93 ; N64-NEXT: daddiu $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 94 ; N64-NEXT: dsll $1, $1, 16 95 ; N64-NEXT: bal $[[BB1]] 96 ; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 97 ; N64-NEXT: $[[BB1]]: 98 ; N64-NEXT: daddu $1, $ra, $1 99 ; N64-NEXT: ld $ra, 0($sp) 100 ; N64-NEXT: jr $1 101 ; N64-NEXT: daddiu $sp, $sp, 16 102 103 ; N64: $[[BB0]]: 104 ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) 105 ; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) 106 ; N64: addiu $[[R3:[0-9]+]], $zero, 1 107 ; N64: sw $[[R3]], 0($[[R2]]) 108 ; N64: $[[BB2]]: 109 ; N64: jr $ra 110 ; N64: nop 111 112 ; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the 113 ; same with the N64 prefix, we use -asm-show-inst in order to make sure that 114 ; the opcode of the MachineInst is a JALR. 115 ; N64-R6: JALR64 116 117 118 ; Check the microMIPS version. 119 120 ; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp) 121 ; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 122 ; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]] 123 ; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25 124 125 ; Check for long branch expansion: 126 ; MICROMIPS: addiu $sp, $sp, -8 127 ; MICROMIPS-NEXT: sw $ra, 0($sp) 128 ; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 129 ; MICROMIPS-NEXT: bal $[[BB1]] 130 ; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 131 ; MICROMIPS-NEXT: $[[BB1]]: 132 ; MICROMIPS-NEXT: addu $1, $ra, $1 133 ; MICROMIPS-NEXT: lw $ra, 0($sp) 134 ; MICROMIPS-NEXT: jr $1 135 ; MICROMIPS-NEXT: addiu $sp, $sp, 8 136 137 ; MICROMIPS: $[[BB0]]: 138 ; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 139 ; MICROMIPS: li16 $[[R2:[0-9]+]], 1 140 ; MICROMIPS: sw16 $[[R2]], 0($[[R1]]) 141 ; MICROMIPS: $[[BB2]]: 142 ; MICROMIPS: jrc $ra 143 144 145 ; Check the NaCl version. Check that sp change is not in the branch delay slot 146 ; of "jr $1" instruction. Check that target of indirect branch "jr $1" is 147 ; bundle aligned. 148 149 ; NACL: lui $[[R0:[0-9]+]], %hi(_gp_disp) 150 ; NACL: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 151 ; NACL: bnez $4, $[[BB0:BB[0-9_]+]] 152 ; NACL: addu $[[GP:[0-9]+]], $[[R0]], $25 153 154 ; Check for long branch expansion: 155 ; NACL: addiu $sp, $sp, -8 156 ; NACL-NEXT: sw $ra, 0($sp) 157 ; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 158 ; NACL-NEXT: bal $[[BB1]] 159 ; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 160 ; NACL-NEXT: $[[BB1]]: 161 ; NACL-NEXT: addu $1, $ra, $1 162 ; NACL-NEXT: lw $ra, 0($sp) 163 ; NACL-NEXT: addiu $sp, $sp, 8 164 ; NACL-NEXT: jr $1 165 ; NACL-NEXT: nop 166 167 ; NACL: $[[BB0]]: 168 ; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 169 ; NACL: addiu $[[R2:[0-9]+]], $zero, 1 170 ; NACL: sw $[[R2]], 0($[[R1]]) 171 ; NACL: .p2align 4 172 ; NACL-NEXT: $[[BB2]]: 173 ; NACL: jr $ra 174 ; NACL: nop 175 } 176
