1 ; Test the MSA intrinsics that are encoded with the 3R instruction format. 2 ; There are lots of these so this covers those beginning with 'b' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s 6 7 @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 9 @llvm_mips_bclr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11 define void @llvm_mips_bclr_b_test() nounwind { 12 entry: 13 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bclr_b_ARG1 14 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bclr_b_ARG2 15 %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1) 16 store <16 x i8> %2, <16 x i8>* @llvm_mips_bclr_b_RES 17 ret void 18 } 19 20 declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind 21 22 ; CHECK: llvm_mips_bclr_b_test: 23 ; CHECK: ld.b 24 ; CHECK: ld.b 25 ; CHECK: bclr.b 26 ; CHECK: st.b 27 ; CHECK: .size llvm_mips_bclr_b_test 28 ; 29 @llvm_mips_bclr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 30 @llvm_mips_bclr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 31 @llvm_mips_bclr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 32 33 define void @llvm_mips_bclr_h_test() nounwind { 34 entry: 35 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bclr_h_ARG1 36 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bclr_h_ARG2 37 %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1) 38 store <8 x i16> %2, <8 x i16>* @llvm_mips_bclr_h_RES 39 ret void 40 } 41 42 declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind 43 44 ; CHECK: llvm_mips_bclr_h_test: 45 ; CHECK: ld.h 46 ; CHECK: ld.h 47 ; CHECK: bclr.h 48 ; CHECK: st.h 49 ; CHECK: .size llvm_mips_bclr_h_test 50 ; 51 @llvm_mips_bclr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 52 @llvm_mips_bclr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 53 @llvm_mips_bclr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 54 55 define void @llvm_mips_bclr_w_test() nounwind { 56 entry: 57 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bclr_w_ARG1 58 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bclr_w_ARG2 59 %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1) 60 store <4 x i32> %2, <4 x i32>* @llvm_mips_bclr_w_RES 61 ret void 62 } 63 64 declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind 65 66 ; CHECK: llvm_mips_bclr_w_test: 67 ; CHECK: ld.w 68 ; CHECK: ld.w 69 ; CHECK: bclr.w 70 ; CHECK: st.w 71 ; CHECK: .size llvm_mips_bclr_w_test 72 ; 73 @llvm_mips_bclr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 74 @llvm_mips_bclr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 75 @llvm_mips_bclr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 76 77 define void @llvm_mips_bclr_d_test() nounwind { 78 entry: 79 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bclr_d_ARG1 80 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bclr_d_ARG2 81 %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1) 82 store <2 x i64> %2, <2 x i64>* @llvm_mips_bclr_d_RES 83 ret void 84 } 85 86 declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind 87 88 ; CHECK: llvm_mips_bclr_d_test: 89 ; CHECK: ld.d 90 ; CHECK: ld.d 91 ; CHECK: bclr.d 92 ; CHECK: st.d 93 ; CHECK: .size llvm_mips_bclr_d_test 94 95 @llvm_mips_binsl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 96 @llvm_mips_binsl_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 97 @llvm_mips_binsl_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 98 @llvm_mips_binsl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 99 100 define void @llvm_mips_binsl_b_test() nounwind { 101 entry: 102 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsl_b_ARG1 103 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsl_b_ARG2 104 %2 = load <16 x i8>, <16 x i8>* @llvm_mips_binsl_b_ARG3 105 %3 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) 106 store <16 x i8> %3, <16 x i8>* @llvm_mips_binsl_b_RES 107 ret void 108 } 109 110 declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind 111 112 ; CHECK: llvm_mips_binsl_b_test: 113 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG1)( 114 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG2)( 115 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG3)( 116 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) 117 ; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]]) 118 ; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]]) 119 ; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]] 120 ; CHECK-DAG: st.b [[R4]], 0( 121 ; CHECK: .size llvm_mips_binsl_b_test 122 123 @llvm_mips_binsl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 124 @llvm_mips_binsl_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 125 @llvm_mips_binsl_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 126 @llvm_mips_binsl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 127 128 define void @llvm_mips_binsl_h_test() nounwind { 129 entry: 130 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsl_h_ARG1 131 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsl_h_ARG2 132 %2 = load <8 x i16>, <8 x i16>* @llvm_mips_binsl_h_ARG3 133 %3 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) 134 store <8 x i16> %3, <8 x i16>* @llvm_mips_binsl_h_RES 135 ret void 136 } 137 138 declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind 139 140 ; CHECK: llvm_mips_binsl_h_test: 141 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG1)( 142 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG2)( 143 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG3)( 144 ; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]]) 145 ; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]]) 146 ; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]]) 147 ; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]] 148 ; CHECK-DAG: st.h [[R4]], 0( 149 ; CHECK: .size llvm_mips_binsl_h_test 150 151 @llvm_mips_binsl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 152 @llvm_mips_binsl_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 153 @llvm_mips_binsl_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 154 @llvm_mips_binsl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 155 156 define void @llvm_mips_binsl_w_test() nounwind { 157 entry: 158 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsl_w_ARG1 159 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsl_w_ARG2 160 %2 = load <4 x i32>, <4 x i32>* @llvm_mips_binsl_w_ARG3 161 %3 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) 162 store <4 x i32> %3, <4 x i32>* @llvm_mips_binsl_w_RES 163 ret void 164 } 165 166 declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind 167 168 ; CHECK: llvm_mips_binsl_w_test: 169 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG1)( 170 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG2)( 171 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG3)( 172 ; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]]) 173 ; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]]) 174 ; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]]) 175 ; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]] 176 ; CHECK-DAG: st.w [[R4]], 0( 177 ; CHECK: .size llvm_mips_binsl_w_test 178 179 @llvm_mips_binsl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 180 @llvm_mips_binsl_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16 181 @llvm_mips_binsl_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16 182 @llvm_mips_binsl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 183 184 define void @llvm_mips_binsl_d_test() nounwind { 185 entry: 186 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsl_d_ARG1 187 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsl_d_ARG2 188 %2 = load <2 x i64>, <2 x i64>* @llvm_mips_binsl_d_ARG3 189 %3 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) 190 store <2 x i64> %3, <2 x i64>* @llvm_mips_binsl_d_RES 191 ret void 192 } 193 194 declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind 195 196 ; CHECK: llvm_mips_binsl_d_test: 197 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG1)( 198 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG2)( 199 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG3)( 200 ; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]]) 201 ; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]]) 202 ; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]]) 203 ; CHECK-DAG: binsl.d [[R4]], [[R5]], [[R6]] 204 ; CHECK-DAG: st.d [[R4]], 0( 205 ; CHECK: .size llvm_mips_binsl_d_test 206 207 @llvm_mips_binsr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 208 @llvm_mips_binsr_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 209 @llvm_mips_binsr_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 210 @llvm_mips_binsr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 211 212 define void @llvm_mips_binsr_b_test() nounwind { 213 entry: 214 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsr_b_ARG1 215 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsr_b_ARG2 216 %2 = load <16 x i8>, <16 x i8>* @llvm_mips_binsr_b_ARG3 217 %3 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) 218 store <16 x i8> %3, <16 x i8>* @llvm_mips_binsr_b_RES 219 ret void 220 } 221 222 declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind 223 224 ; CHECK: llvm_mips_binsr_b_test: 225 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG1)( 226 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG2)( 227 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG3)( 228 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) 229 ; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]]) 230 ; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]]) 231 ; CHECK-DAG: binsr.b [[R4]], [[R5]], [[R6]] 232 ; CHECK-DAG: st.b [[R4]], 0( 233 ; CHECK: .size llvm_mips_binsr_b_test 234 235 @llvm_mips_binsr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 236 @llvm_mips_binsr_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 237 @llvm_mips_binsr_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 238 @llvm_mips_binsr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 239 240 define void @llvm_mips_binsr_h_test() nounwind { 241 entry: 242 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsr_h_ARG1 243 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsr_h_ARG2 244 %2 = load <8 x i16>, <8 x i16>* @llvm_mips_binsr_h_ARG3 245 %3 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) 246 store <8 x i16> %3, <8 x i16>* @llvm_mips_binsr_h_RES 247 ret void 248 } 249 250 declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind 251 252 ; CHECK: llvm_mips_binsr_h_test: 253 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG1)( 254 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG2)( 255 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG3)( 256 ; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]]) 257 ; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]]) 258 ; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]]) 259 ; CHECK-DAG: binsr.h [[R4]], [[R5]], [[R6]] 260 ; CHECK-DAG: st.h [[R4]], 0( 261 ; CHECK: .size llvm_mips_binsr_h_test 262 263 @llvm_mips_binsr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 264 @llvm_mips_binsr_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 265 @llvm_mips_binsr_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 266 @llvm_mips_binsr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 267 268 define void @llvm_mips_binsr_w_test() nounwind { 269 entry: 270 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsr_w_ARG1 271 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsr_w_ARG2 272 %2 = load <4 x i32>, <4 x i32>* @llvm_mips_binsr_w_ARG3 273 %3 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) 274 store <4 x i32> %3, <4 x i32>* @llvm_mips_binsr_w_RES 275 ret void 276 } 277 278 declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind 279 280 ; CHECK: llvm_mips_binsr_w_test: 281 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG1)( 282 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG2)( 283 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG3)( 284 ; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]]) 285 ; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]]) 286 ; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]]) 287 ; CHECK-DAG: binsr.w [[R4]], [[R5]], [[R6]] 288 ; CHECK-DAG: st.w [[R4]], 0( 289 ; CHECK: .size llvm_mips_binsr_w_test 290 291 @llvm_mips_binsr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 292 @llvm_mips_binsr_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16 293 @llvm_mips_binsr_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16 294 @llvm_mips_binsr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 295 296 define void @llvm_mips_binsr_d_test() nounwind { 297 entry: 298 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsr_d_ARG1 299 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsr_d_ARG2 300 %2 = load <2 x i64>, <2 x i64>* @llvm_mips_binsr_d_ARG3 301 %3 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) 302 store <2 x i64> %3, <2 x i64>* @llvm_mips_binsr_d_RES 303 ret void 304 } 305 306 declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind 307 308 ; CHECK: llvm_mips_binsr_d_test: 309 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG1)( 310 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG2)( 311 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG3)( 312 ; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]]) 313 ; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]]) 314 ; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]]) 315 ; CHECK-DAG: binsr.d [[R4]], [[R5]], [[R6]] 316 ; CHECK-DAG: st.d [[R4]], 0( 317 ; CHECK: .size llvm_mips_binsr_d_test 318 319 @llvm_mips_bneg_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 320 @llvm_mips_bneg_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 321 @llvm_mips_bneg_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 322 323 define void @llvm_mips_bneg_b_test() nounwind { 324 entry: 325 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bneg_b_ARG1 326 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bneg_b_ARG2 327 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1) 328 store <16 x i8> %2, <16 x i8>* @llvm_mips_bneg_b_RES 329 ret void 330 } 331 332 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind 333 334 ; CHECK: llvm_mips_bneg_b_test: 335 ; CHECK: ld.b 336 ; CHECK: ld.b 337 ; CHECK: bneg.b 338 ; CHECK: st.b 339 ; CHECK: .size llvm_mips_bneg_b_test 340 ; 341 @llvm_mips_bneg_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 342 @llvm_mips_bneg_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 343 @llvm_mips_bneg_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 344 345 define void @llvm_mips_bneg_h_test() nounwind { 346 entry: 347 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bneg_h_ARG1 348 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bneg_h_ARG2 349 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1) 350 store <8 x i16> %2, <8 x i16>* @llvm_mips_bneg_h_RES 351 ret void 352 } 353 354 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind 355 356 ; CHECK: llvm_mips_bneg_h_test: 357 ; CHECK: ld.h 358 ; CHECK: ld.h 359 ; CHECK: bneg.h 360 ; CHECK: st.h 361 ; CHECK: .size llvm_mips_bneg_h_test 362 ; 363 @llvm_mips_bneg_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 364 @llvm_mips_bneg_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 365 @llvm_mips_bneg_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 366 367 define void @llvm_mips_bneg_w_test() nounwind { 368 entry: 369 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bneg_w_ARG1 370 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bneg_w_ARG2 371 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1) 372 store <4 x i32> %2, <4 x i32>* @llvm_mips_bneg_w_RES 373 ret void 374 } 375 376 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind 377 378 ; CHECK: llvm_mips_bneg_w_test: 379 ; CHECK: ld.w 380 ; CHECK: ld.w 381 ; CHECK: bneg.w 382 ; CHECK: st.w 383 ; CHECK: .size llvm_mips_bneg_w_test 384 ; 385 @llvm_mips_bneg_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 386 @llvm_mips_bneg_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 387 @llvm_mips_bneg_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 388 389 define void @llvm_mips_bneg_d_test() nounwind { 390 entry: 391 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bneg_d_ARG1 392 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bneg_d_ARG2 393 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1) 394 store <2 x i64> %2, <2 x i64>* @llvm_mips_bneg_d_RES 395 ret void 396 } 397 398 declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind 399 400 ; CHECK: llvm_mips_bneg_d_test: 401 ; CHECK: ld.d 402 ; CHECK: ld.d 403 ; CHECK: bneg.d 404 ; CHECK: st.d 405 ; CHECK: .size llvm_mips_bneg_d_test 406 ; 407 @llvm_mips_bset_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 408 @llvm_mips_bset_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 409 @llvm_mips_bset_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 410 411 define void @llvm_mips_bset_b_test() nounwind { 412 entry: 413 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bset_b_ARG1 414 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bset_b_ARG2 415 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1) 416 store <16 x i8> %2, <16 x i8>* @llvm_mips_bset_b_RES 417 ret void 418 } 419 420 declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind 421 422 ; CHECK: llvm_mips_bset_b_test: 423 ; CHECK: ld.b 424 ; CHECK: ld.b 425 ; CHECK: bset.b 426 ; CHECK: st.b 427 ; CHECK: .size llvm_mips_bset_b_test 428 ; 429 @llvm_mips_bset_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 430 @llvm_mips_bset_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 431 @llvm_mips_bset_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 432 433 define void @llvm_mips_bset_h_test() nounwind { 434 entry: 435 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bset_h_ARG1 436 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bset_h_ARG2 437 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1) 438 store <8 x i16> %2, <8 x i16>* @llvm_mips_bset_h_RES 439 ret void 440 } 441 442 declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind 443 444 ; CHECK: llvm_mips_bset_h_test: 445 ; CHECK: ld.h 446 ; CHECK: ld.h 447 ; CHECK: bset.h 448 ; CHECK: st.h 449 ; CHECK: .size llvm_mips_bset_h_test 450 ; 451 @llvm_mips_bset_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 452 @llvm_mips_bset_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 453 @llvm_mips_bset_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 454 455 define void @llvm_mips_bset_w_test() nounwind { 456 entry: 457 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bset_w_ARG1 458 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bset_w_ARG2 459 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1) 460 store <4 x i32> %2, <4 x i32>* @llvm_mips_bset_w_RES 461 ret void 462 } 463 464 declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind 465 466 ; CHECK: llvm_mips_bset_w_test: 467 ; CHECK: ld.w 468 ; CHECK: ld.w 469 ; CHECK: bset.w 470 ; CHECK: st.w 471 ; CHECK: .size llvm_mips_bset_w_test 472 ; 473 @llvm_mips_bset_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 474 @llvm_mips_bset_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 475 @llvm_mips_bset_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 476 477 define void @llvm_mips_bset_d_test() nounwind { 478 entry: 479 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bset_d_ARG1 480 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bset_d_ARG2 481 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1) 482 store <2 x i64> %2, <2 x i64>* @llvm_mips_bset_d_RES 483 ret void 484 } 485 486 declare <2 x i64> @llvm.mips.bset.d(<2 x i64>, <2 x i64>) nounwind 487 488 ; CHECK: llvm_mips_bset_d_test: 489 ; CHECK: ld.d 490 ; CHECK: ld.d 491 ; CHECK: bset.d 492 ; CHECK: st.d 493 ; CHECK: .size llvm_mips_bset_d_test 494 ; 495
