1 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic \ 2 ; RUN: -verify-machineinstrs < %s | \ 3 ; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-BE %s 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic \ 5 ; RUN: -verify-machineinstrs < %s | \ 6 ; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-LE %s 7 ; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 \ 8 ; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ 9 ; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-BE %s 10 ; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 \ 11 ; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ 12 ; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-LE %s 13 ; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic \ 14 ; RUN: -verify-machineinstrs < %s | \ 15 ; RUN: FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-BE %s 16 ; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic \ 17 ; RUN: -verify-machineinstrs < %s | \ 18 ; RUN: FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-LE %s 19 20 @v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0> 21 @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 22 @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 23 @v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0> 24 @v2i64 = global <2 x i64> <i64 0, i64 0> 25 @i32 = global i32 0 26 @i64 = global i64 0 27 28 define void @const_v16i8() nounwind { 29 ; ALL-LABEL: const_v16i8: 30 31 store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8 32 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 33 34 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8 35 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 36 37 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8 38 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 39 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 40 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 41 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) 42 43 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8 44 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 45 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 46 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 47 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) 48 49 store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8 50 ; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256 51 ; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1 52 53 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8 54 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258 55 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027 56 ; ALL-BE-DAG: ori [[R2]], [[R2]], 772 57 ; ALL-LE-DAG: ori [[R2]], [[R2]], 513 58 ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] 59 60 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8 61 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 62 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 63 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 64 ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) 65 66 ret void 67 } 68 69 define void @const_v8i16() nounwind { 70 ; ALL-LABEL: const_v8i16: 71 72 store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16 73 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 74 75 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16 76 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 77 78 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16 79 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 80 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 81 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 82 ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) 83 84 store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16 85 ; ALL: ldi.b [[R1:\$w[0-9]+]], 4 86 87 store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16 88 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1 89 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2 90 ; ALL-BE-DAG: ori [[R2]], [[R2]], 2 91 ; ALL-LE-DAG: ori [[R2]], [[R2]], 1 92 ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] 93 94 store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16 95 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 96 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 97 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 98 ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) 99 100 ret void 101 } 102 103 define void @const_v4i32() nounwind { 104 ; ALL-LABEL: const_v4i32: 105 106 store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32 107 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 108 109 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32 110 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1 111 112 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32 113 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 114 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 115 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 116 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 117 118 store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32 119 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 120 121 store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32 122 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 123 124 store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32 125 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 126 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 127 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 128 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 129 130 store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32 131 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 132 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 133 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 134 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 135 136 ret void 137 } 138 139 define void @const_v2i64() nounwind { 140 ; ALL-LABEL: const_v2i64: 141 142 store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64 143 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 144 145 store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64 146 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1 147 148 store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64 149 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 150 151 store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64 152 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1 153 154 store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64 155 ; ALL: ldi.d [[R1:\$w[0-9]+]], 1 156 157 store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64 158 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 159 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 160 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 161 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 162 ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 163 164 store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64 165 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 166 ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 167 ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ 168 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 169 ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 170 171 ret void 172 } 173 174 define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind { 175 ; ALL-LABEL: nonconst_v16i8: 176 177 %1 = insertelement <16 x i8> undef, i8 %a, i32 0 178 %2 = insertelement <16 x i8> %1, i8 %b, i32 1 179 %3 = insertelement <16 x i8> %2, i8 %c, i32 2 180 %4 = insertelement <16 x i8> %3, i8 %d, i32 3 181 %5 = insertelement <16 x i8> %4, i8 %e, i32 4 182 %6 = insertelement <16 x i8> %5, i8 %f, i32 5 183 %7 = insertelement <16 x i8> %6, i8 %g, i32 6 184 %8 = insertelement <16 x i8> %7, i8 %h, i32 7 185 %9 = insertelement <16 x i8> %8, i8 %h, i32 8 186 %10 = insertelement <16 x i8> %9, i8 %h, i32 9 187 %11 = insertelement <16 x i8> %10, i8 %h, i32 10 188 %12 = insertelement <16 x i8> %11, i8 %h, i32 11 189 %13 = insertelement <16 x i8> %12, i8 %h, i32 12 190 %14 = insertelement <16 x i8> %13, i8 %h, i32 13 191 %15 = insertelement <16 x i8> %14, i8 %h, i32 14 192 %16 = insertelement <16 x i8> %15, i8 %h, i32 15 193 ; ALL-DAG: insert.b [[R1:\$w[0-9]+]][0], $4 194 ; ALL-DAG: insert.b [[R1]][1], $5 195 ; ALL-DAG: insert.b [[R1]][2], $6 196 ; ALL-DAG: insert.b [[R1]][3], $7 197 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp) 198 ; MIPS32-DAG: insert.b [[R1]][4], [[R2]] 199 ; MIPS64-DAG: insert.b [[R1]][4], $8 200 ; MIPS32-DAG: lw [[R3:\$[0-9]+]], 20($sp) 201 ; MIPS32-DAG: insert.b [[R1]][5], [[R3]] 202 ; MIPS64-DAG: insert.b [[R1]][5], $9 203 ; MIPS32-DAG: lw [[R4:\$[0-9]+]], 24($sp) 204 ; MIPS32-DAG: insert.b [[R1]][6], [[R4]] 205 ; MIPS64-DAG: insert.b [[R1]][6], $10 206 ; MIPS32-DAG: lw [[R5:\$[0-9]+]], 28($sp) 207 ; MIPS32-DAG: insert.b [[R1]][7], [[R5]] 208 ; MIPS64-DAG: insert.b [[R1]][7], [[R5:\$11]] 209 ; ALL-DAG: insert.b [[R1]][8], [[R5]] 210 ; ALL-DAG: insert.b [[R1]][9], [[R5]] 211 ; ALL-DAG: insert.b [[R1]][10], [[R5]] 212 ; ALL-DAG: insert.b [[R1]][11], [[R5]] 213 ; ALL-DAG: insert.b [[R1]][12], [[R5]] 214 ; ALL-DAG: insert.b [[R1]][13], [[R5]] 215 ; ALL-DAG: insert.b [[R1]][14], [[R5]] 216 ; ALL-DAG: insert.b [[R1]][15], [[R5]] 217 218 store volatile <16 x i8> %16, <16 x i8>*@v16i8 219 220 ret void 221 } 222 223 define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind { 224 ; ALL-LABEL: nonconst_v8i16: 225 226 %1 = insertelement <8 x i16> undef, i16 %a, i32 0 227 %2 = insertelement <8 x i16> %1, i16 %b, i32 1 228 %3 = insertelement <8 x i16> %2, i16 %c, i32 2 229 %4 = insertelement <8 x i16> %3, i16 %d, i32 3 230 %5 = insertelement <8 x i16> %4, i16 %e, i32 4 231 %6 = insertelement <8 x i16> %5, i16 %f, i32 5 232 %7 = insertelement <8 x i16> %6, i16 %g, i32 6 233 %8 = insertelement <8 x i16> %7, i16 %h, i32 7 234 ; ALL-DAG: insert.h [[R1:\$w[0-9]+]][0], $4 235 ; ALL-DAG: insert.h [[R1]][1], $5 236 ; ALL-DAG: insert.h [[R1]][2], $6 237 ; ALL-DAG: insert.h [[R1]][3], $7 238 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp) 239 ; MIPS32-DAG: insert.h [[R1]][4], [[R2]] 240 ; MIPS64-DAG: insert.h [[R1]][4], $8 241 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 20($sp) 242 ; MIPS32-DAG: insert.h [[R1]][5], [[R2]] 243 ; MIPS64-DAG: insert.h [[R1]][5], $9 244 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 24($sp) 245 ; MIPS32-DAG: insert.h [[R1]][6], [[R2]] 246 ; MIPS64-DAG: insert.h [[R1]][6], $10 247 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 28($sp) 248 ; MIPS32-DAG: insert.h [[R1]][7], [[R2]] 249 ; MIPS64-DAG: insert.h [[R1]][7], $11 250 251 store volatile <8 x i16> %8, <8 x i16>*@v8i16 252 253 ret void 254 } 255 256 define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { 257 ; ALL-LABEL: nonconst_v4i32: 258 259 %1 = insertelement <4 x i32> undef, i32 %a, i32 0 260 %2 = insertelement <4 x i32> %1, i32 %b, i32 1 261 %3 = insertelement <4 x i32> %2, i32 %c, i32 2 262 %4 = insertelement <4 x i32> %3, i32 %d, i32 3 263 ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4 264 ; ALL: insert.w [[R1]][1], $5 265 ; ALL: insert.w [[R1]][2], $6 266 ; ALL: insert.w [[R1]][3], $7 267 268 store volatile <4 x i32> %4, <4 x i32>*@v4i32 269 270 ret void 271 } 272 273 define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind { 274 ; ALL-LABEL: nonconst_v2i64: 275 276 %1 = insertelement <2 x i64> undef, i64 %a, i32 0 277 %2 = insertelement <2 x i64> %1, i64 %b, i32 1 278 ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4 279 ; MIPS32: insert.w [[R1]][1], $5 280 ; MIPS32: insert.w [[R1]][2], $6 281 ; MIPS32: insert.w [[R1]][3], $7 282 ; MIPS64: insert.d [[R1:\$w[0-9]+]][0], $4 283 ; MIPS64: insert.d [[R1]][1], $5 284 285 store volatile <2 x i64> %2, <2 x i64>*@v2i64 286 287 ret void 288 } 289 290 define i32 @extract_sext_v16i8() nounwind { 291 ; ALL-LABEL: extract_sext_v16i8: 292 293 %1 = load <16 x i8>, <16 x i8>* @v16i8 294 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 295 296 %2 = add <16 x i8> %1, %1 297 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 298 299 %3 = extractelement <16 x i8> %2, i32 1 300 %4 = sext i8 %3 to i32 301 ; ALL-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1] 302 ; ALL-NOT: sll 303 ; ALL-NOT: sra 304 305 ret i32 %4 306 } 307 308 define i32 @extract_sext_v8i16() nounwind { 309 ; ALL-LABEL: extract_sext_v8i16: 310 311 %1 = load <8 x i16>, <8 x i16>* @v8i16 312 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 313 314 %2 = add <8 x i16> %1, %1 315 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 316 317 %3 = extractelement <8 x i16> %2, i32 1 318 %4 = sext i16 %3 to i32 319 ; ALL-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1] 320 ; ALL-NOT: sll 321 ; ALL-NOT: sra 322 323 ret i32 %4 324 } 325 326 define i32 @extract_sext_v4i32() nounwind { 327 ; ALL-LABEL: extract_sext_v4i32: 328 329 %1 = load <4 x i32>, <4 x i32>* @v4i32 330 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 331 332 %2 = add <4 x i32> %1, %1 333 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 334 335 %3 = extractelement <4 x i32> %2, i32 1 336 ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1] 337 338 ret i32 %3 339 } 340 341 define i64 @extract_sext_v2i64() nounwind { 342 ; ALL-LABEL: extract_sext_v2i64: 343 344 %1 = load <2 x i64>, <2 x i64>* @v2i64 345 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 346 347 %2 = add <2 x i64> %1, %1 348 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 349 350 %3 = extractelement <2 x i64> %2, i32 1 351 ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2] 352 ; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3] 353 ; MIPS64-DAG: copy_s.d [[R3:\$[0-9]+]], [[R1]][1] 354 ; ALL-NOT: sll 355 ; ALL-NOT: sra 356 357 ret i64 %3 358 } 359 360 define i32 @extract_zext_v16i8() nounwind { 361 ; ALL-LABEL: extract_zext_v16i8: 362 363 %1 = load <16 x i8>, <16 x i8>* @v16i8 364 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 365 366 %2 = add <16 x i8> %1, %1 367 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 368 369 %3 = extractelement <16 x i8> %2, i32 1 370 %4 = zext i8 %3 to i32 371 ; ALL-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1] 372 ; ALL-NOT: andi 373 374 ret i32 %4 375 } 376 377 define i32 @extract_zext_v8i16() nounwind { 378 ; ALL-LABEL: extract_zext_v8i16: 379 380 %1 = load <8 x i16>, <8 x i16>* @v8i16 381 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 382 383 %2 = add <8 x i16> %1, %1 384 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 385 386 %3 = extractelement <8 x i16> %2, i32 1 387 %4 = zext i16 %3 to i32 388 ; ALL-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1] 389 ; ALL-NOT: andi 390 391 ret i32 %4 392 } 393 394 define i32 @extract_zext_v4i32() nounwind { 395 ; ALL-LABEL: extract_zext_v4i32: 396 397 %1 = load <4 x i32>, <4 x i32>* @v4i32 398 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 399 400 %2 = add <4 x i32> %1, %1 401 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 402 403 %3 = extractelement <4 x i32> %2, i32 1 404 ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1] 405 406 ret i32 %3 407 } 408 409 define i64 @extract_zext_v2i64() nounwind { 410 ; ALL-LABEL: extract_zext_v2i64: 411 412 %1 = load <2 x i64>, <2 x i64>* @v2i64 413 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 414 415 %2 = add <2 x i64> %1, %1 416 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 417 418 %3 = extractelement <2 x i64> %2, i32 1 419 ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2] 420 ; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3] 421 ; MIPS64-DAG: copy_{{[su]}}.d [[R3:\$[0-9]+]], [[R1]][1] 422 ; ALL-NOT: andi 423 424 ret i64 %3 425 } 426 427 define i32 @extract_sext_v16i8_vidx() nounwind { 428 ; ALL-LABEL: extract_sext_v16i8_vidx: 429 430 %1 = load <16 x i8>, <16 x i8>* @v16i8 431 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( 432 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 433 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 434 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) 435 436 %2 = add <16 x i8> %1, %1 437 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 438 439 %3 = load i32, i32* @i32 440 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 441 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 442 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 443 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 444 445 %4 = extractelement <16 x i8> %2, i32 %3 446 %5 = sext i8 %4 to i32 447 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 448 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 449 ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24 450 451 ret i32 %5 452 } 453 454 define i32 @extract_sext_v8i16_vidx() nounwind { 455 ; ALL-LABEL: extract_sext_v8i16_vidx: 456 457 %1 = load <8 x i16>, <8 x i16>* @v8i16 458 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( 459 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 460 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 461 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) 462 463 %2 = add <8 x i16> %1, %1 464 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 465 466 %3 = load i32, i32* @i32 467 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 468 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 469 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 470 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 471 472 %4 = extractelement <8 x i16> %2, i32 %3 473 %5 = sext i16 %4 to i32 474 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 475 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 476 ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16 477 478 ret i32 %5 479 } 480 481 define i32 @extract_sext_v4i32_vidx() nounwind { 482 ; ALL-LABEL: extract_sext_v4i32_vidx: 483 484 %1 = load <4 x i32>, <4 x i32>* @v4i32 485 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( 486 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 487 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 488 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) 489 490 %2 = add <4 x i32> %1, %1 491 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 492 493 %3 = load i32, i32* @i32 494 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 495 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 496 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 497 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 498 499 %4 = extractelement <4 x i32> %2, i32 %3 500 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 501 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 502 ; ALL-NOT: sra 503 504 ret i32 %4 505 } 506 507 define i64 @extract_sext_v2i64_vidx() nounwind { 508 ; ALL-LABEL: extract_sext_v2i64_vidx: 509 510 %1 = load <2 x i64>, <2 x i64>* @v2i64 511 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( 512 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 513 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 514 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) 515 516 %2 = add <2 x i64> %1, %1 517 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 518 519 %3 = load i32, i32* @i32 520 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 521 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 522 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 523 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 524 525 %4 = extractelement <2 x i64> %2, i32 %3 526 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 527 ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 528 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 529 ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] 530 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 531 ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]] 532 ; ALL-NOT: sra 533 534 ret i64 %4 535 } 536 537 define i32 @extract_zext_v16i8_vidx() nounwind { 538 ; ALL-LABEL: extract_zext_v16i8_vidx: 539 540 %1 = load <16 x i8>, <16 x i8>* @v16i8 541 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)( 542 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 543 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)( 544 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]]) 545 546 %2 = add <16 x i8> %1, %1 547 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 548 549 %3 = load i32, i32* @i32 550 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 551 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 552 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 553 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 554 555 %4 = extractelement <16 x i8> %2, i32 %3 556 %5 = zext i8 %4 to i32 557 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 558 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 559 ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24 560 561 ret i32 %5 562 } 563 564 define i32 @extract_zext_v8i16_vidx() nounwind { 565 ; ALL-LABEL: extract_zext_v8i16_vidx: 566 567 %1 = load <8 x i16>, <8 x i16>* @v8i16 568 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)( 569 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 570 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)( 571 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]]) 572 573 %2 = add <8 x i16> %1, %1 574 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 575 576 %3 = load i32, i32* @i32 577 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 578 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 579 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 580 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 581 582 %4 = extractelement <8 x i16> %2, i32 %3 583 %5 = zext i16 %4 to i32 584 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 585 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 586 ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16 587 588 ret i32 %5 589 } 590 591 define i32 @extract_zext_v4i32_vidx() nounwind { 592 ; ALL-LABEL: extract_zext_v4i32_vidx: 593 594 %1 = load <4 x i32>, <4 x i32>* @v4i32 595 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)( 596 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 597 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)( 598 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) 599 600 %2 = add <4 x i32> %1, %1 601 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 602 603 %3 = load i32, i32* @i32 604 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 605 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 606 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 607 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 608 609 %4 = extractelement <4 x i32> %2, i32 %3 610 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 611 ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 612 ; ALL-NOT: srl 613 614 ret i32 %4 615 } 616 617 define i64 @extract_zext_v2i64_vidx() nounwind { 618 ; ALL-LABEL: extract_zext_v2i64_vidx: 619 620 %1 = load <2 x i64>, <2 x i64>* @v2i64 621 ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)( 622 ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 623 ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)( 624 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) 625 626 %2 = add <2 x i64> %1, %1 627 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 628 629 %3 = load i32, i32* @i32 630 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 631 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 632 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 633 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 634 635 %4 = extractelement <2 x i64> %2, i32 %3 636 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 637 ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]] 638 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 639 ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]] 640 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]] 641 ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]] 642 ; ALL-NOT: srl 643 644 ret i64 %4 645 } 646 647 define void @insert_v16i8(i32 signext %a) nounwind { 648 ; ALL-LABEL: insert_v16i8: 649 650 %1 = load <16 x i8>, <16 x i8>* @v16i8 651 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 652 653 %a2 = trunc i32 %a to i8 654 %a3 = sext i8 %a2 to i32 655 %a4 = trunc i32 %a3 to i8 656 ; ALL-NOT: andi 657 ; ALL-NOT: sra 658 659 %2 = insertelement <16 x i8> %1, i8 %a4, i32 1 660 ; ALL-DAG: insert.b [[R1]][1], $4 661 662 store <16 x i8> %2, <16 x i8>* @v16i8 663 ; ALL-DAG: st.b [[R1]] 664 665 ret void 666 } 667 668 define void @insert_v8i16(i32 signext %a) nounwind { 669 ; ALL-LABEL: insert_v8i16: 670 671 %1 = load <8 x i16>, <8 x i16>* @v8i16 672 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 673 674 %a2 = trunc i32 %a to i16 675 %a3 = sext i16 %a2 to i32 676 %a4 = trunc i32 %a3 to i16 677 ; ALL-NOT: andi 678 ; ALL-NOT: sra 679 680 %2 = insertelement <8 x i16> %1, i16 %a4, i32 1 681 ; ALL-DAG: insert.h [[R1]][1], $4 682 683 store <8 x i16> %2, <8 x i16>* @v8i16 684 ; ALL-DAG: st.h [[R1]] 685 686 ret void 687 } 688 689 define void @insert_v4i32(i32 signext %a) nounwind { 690 ; ALL-LABEL: insert_v4i32: 691 692 %1 = load <4 x i32>, <4 x i32>* @v4i32 693 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 694 695 ; ALL-NOT: andi 696 ; ALL-NOT: sra 697 698 %2 = insertelement <4 x i32> %1, i32 %a, i32 1 699 ; ALL-DAG: insert.w [[R1]][1], $4 700 701 store <4 x i32> %2, <4 x i32>* @v4i32 702 ; ALL-DAG: st.w [[R1]] 703 704 ret void 705 } 706 707 define void @insert_v2i64(i64 signext %a) nounwind { 708 ; ALL-LABEL: insert_v2i64: 709 710 %1 = load <2 x i64>, <2 x i64>* @v2i64 711 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 712 ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]], 713 714 ; ALL-NOT: andi 715 ; ALL-NOT: sra 716 717 %2 = insertelement <2 x i64> %1, i64 %a, i32 1 718 ; MIPS32-DAG: insert.w [[R1]][2], $4 719 ; MIPS32-DAG: insert.w [[R1]][3], $5 720 ; MIPS64-DAG: insert.d [[R1]][1], $4 721 722 store <2 x i64> %2, <2 x i64>* @v2i64 723 ; MIPS32-DAG: st.w [[R1]] 724 ; MIPS64-DAG: st.d [[R1]] 725 726 ret void 727 } 728 729 define void @insert_v16i8_vidx(i32 signext %a) nounwind { 730 ; ALL-LABEL: insert_v16i8_vidx: 731 732 %1 = load <16 x i8>, <16 x i8>* @v16i8 733 ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 734 735 %2 = load i32, i32* @i32 736 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 737 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 738 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 739 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 740 741 %a2 = trunc i32 %a to i8 742 %a3 = sext i8 %a2 to i32 743 %a4 = trunc i32 %a3 to i8 744 ; ALL-NOT: andi 745 ; ALL-NOT: sra 746 747 %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2 748 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]] 749 ; ALL-DAG: insert.b [[R1]][0], $4 750 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] 751 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]] 752 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[IDX]] 753 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 754 755 store <16 x i8> %3, <16 x i8>* @v16i8 756 ; ALL-DAG: st.b [[R1]] 757 758 ret void 759 } 760 761 define void @insert_v8i16_vidx(i32 signext %a) nounwind { 762 ; ALL-LABEL: insert_v8i16_vidx: 763 764 %1 = load <8 x i16>, <8 x i16>* @v8i16 765 ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 766 767 %2 = load i32, i32* @i32 768 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 769 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 770 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 771 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 772 773 %a2 = trunc i32 %a to i16 774 %a3 = sext i16 %a2 to i32 775 %a4 = trunc i32 %a3 to i16 776 ; ALL-NOT: andi 777 ; ALL-NOT: sra 778 779 %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2 780 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1 781 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 782 ; ALL-DAG: insert.h [[R1]][0], $4 783 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 784 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 785 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] 786 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 787 788 store <8 x i16> %3, <8 x i16>* @v8i16 789 ; ALL-DAG: st.h [[R1]] 790 791 ret void 792 } 793 794 define void @insert_v4i32_vidx(i32 signext %a) nounwind { 795 ; ALL-LABEL: insert_v4i32_vidx: 796 797 %1 = load <4 x i32>, <4 x i32>* @v4i32 798 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 799 800 %2 = load i32, i32* @i32 801 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 802 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 803 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 804 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 805 806 ; ALL-NOT: andi 807 ; ALL-NOT: sra 808 809 %3 = insertelement <4 x i32> %1, i32 %a, i32 %2 810 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 811 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 812 ; ALL-DAG: insert.w [[R1]][0], $4 813 ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 814 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 815 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] 816 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 817 818 store <4 x i32> %3, <4 x i32>* @v4i32 819 ; ALL-DAG: st.w [[R1]] 820 821 ret void 822 } 823 824 define void @insert_v2i64_vidx(i64 signext %a) nounwind { 825 ; ALL-LABEL: insert_v2i64_vidx: 826 827 %1 = load <2 x i64>, <2 x i64>* @v2i64 828 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 829 ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]], 830 831 %2 = load i32, i32* @i32 832 ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 833 ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( 834 ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( 835 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 836 837 ; ALL-NOT: andi 838 ; ALL-NOT: sra 839 840 %3 = insertelement <2 x i64> %1, i64 %a, i32 %2 841 ; TODO: This code could be a lot better but it works. The legalizer splits 842 ; 64-bit inserts into two 32-bit inserts because there is no i64 type on 843 ; MIPS32. The obvious optimisation is to perform both insert.w's at once while 844 ; the vector is rotated. 845 ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 846 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 847 ; MIPS32-DAG: insert.w [[R1]][0], $4 848 ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 849 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 850 ; MIPS32-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1 851 ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2 852 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 853 ; MIPS32-DAG: insert.w [[R1]][0], $5 854 ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 855 ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 856 857 ; MIPS64-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3 858 ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 859 ; MIPS64-DAG: insert.d [[R1]][0], $4 860 ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 861 ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] 862 ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 863 864 store <2 x i64> %3, <2 x i64>* @v2i64 865 ; MIPS32-DAG: st.w [[R1]] 866 ; MIPS64-DAG: st.d [[R1]] 867 868 ret void 869 } 870 871 define void @truncstore() nounwind { 872 ; ALL-LABEL: truncstore: 873 874 store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8 875 ; TODO: What code should be emitted? 876 877 ret void 878 } 879
