1 ; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s 2 target triple = "powerpc64-bgq-linux" 3 4 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 5 6 define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone { 7 entry: 8 %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 9 ret <4 x float> %r 10 11 ; CHECK-LABEL: @test1 12 ; CHECK: qvfsel 1, 3, 1, 2 13 ; CHECK: blr 14 } 15 16 define <4 x float> @test2(<4 x float> %a, <4 x float> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone { 17 entry: 18 %v = insertelement <4 x i1> undef, i1 %c1, i32 0 19 %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1 20 %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2 21 %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3 22 %r = select <4 x i1> %v4, <4 x float> %a, <4 x float> %b 23 ret <4 x float> %r 24 25 ; CHECK-LABEL: @test2 26 ; CHECK: stw 27 ; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 28 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 29 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 30 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 31 ; CHECK: qvfsel 1, [[REG4]], 1, 2 32 ; CHECK: blr 33 } 34 35 define <4 x i1> @test3(<4 x i1> %a) nounwind readnone { 36 entry: 37 %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1> 38 ret <4 x i1> %v 39 40 ; CHECK-LABEL: @test3 41 ; CHECK: qvlfsx [[REG:[0-9]+]], 42 ; qvflogical 1, 1, [[REG]], 1 43 ; blr 44 } 45 46 define <4 x i1> @test4(<4 x i1> %a, <4 x i1>* %t) nounwind { 47 entry: 48 %q = load <4 x i1>, <4 x i1>* %t, align 16 49 %v = and <4 x i1> %a, %q 50 ret <4 x i1> %v 51 52 ; CHECK-LABEL: @test4 53 ; CHECK-DAG: lbz 54 ; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], 55 ; CHECK-DAG: stw 56 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], 57 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] 58 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] 59 ; CHECK: qvflogical 1, 1, [[REG4]], 1 60 ; CHECK: blr 61 } 62 63 define void @test5(<4 x i1> %a) nounwind { 64 entry: 65 store <4 x i1> %a, <4 x i1>* @R 66 ret void 67 68 ; CHECK-LABEL: @test5 69 ; CHECK: qvlfdx [[REG1:[0-9]+]], 70 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 71 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 72 ; CHECK: qvstfiwx [[REG3]], 73 ; CHECK: lwz 74 ; CHECK: stb 75 ; CHECK: blr 76 } 77 78 define i1 @test6(<4 x i1> %a) nounwind { 79 entry: 80 %r = extractelement <4 x i1> %a, i32 2 81 ret i1 %r 82 83 ; CHECK-LABEL: @test6 84 ; CHECK: qvlfdx [[REG1:[0-9]+]], 85 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 86 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 87 ; CHECK: qvstfiwx [[REG3]], 88 ; CHECK: lwz 89 ; CHECK: blr 90 } 91 92 define i1 @test7(<4 x i1> %a) nounwind { 93 entry: 94 %r = extractelement <4 x i1> %a, i32 2 95 %s = extractelement <4 x i1> %a, i32 3 96 %q = and i1 %r, %s 97 ret i1 %q 98 99 ; CHECK-LABEL: @test7 100 ; CHECK: qvlfdx [[REG1:[0-9]+]], 101 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 102 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 103 ; CHECK: qvstfiwx [[REG3]], 104 ; CHECK-DAG: lwz [[REG4:[0-9]+]], 105 ; FIXME: We're storing the vector twice, and that's silly. 106 ; CHECK-DAG: qvstfiwx [[REG3]], 107 ; CHECK: lwz [[REG5:[0-9]+]], 108 ; CHECK: and 3, 109 ; CHECK: blr 110 } 111 112 define i1 @test8(<3 x i1> %a) nounwind { 113 entry: 114 %r = extractelement <3 x i1> %a, i32 2 115 ret i1 %r 116 117 ; CHECK-LABEL: @test8 118 ; CHECK: qvlfdx [[REG1:[0-9]+]], 119 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 120 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 121 ; CHECK: qvstfiwx [[REG3]], 122 ; CHECK: lwz 123 ; CHECK: blr 124 } 125 126 define <3 x float> @test9(<3 x float> %a, <3 x float> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone { 127 entry: 128 %v = insertelement <3 x i1> undef, i1 %c1, i32 0 129 %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1 130 %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2 131 %r = select <3 x i1> %v3, <3 x float> %a, <3 x float> %b 132 ret <3 x float> %r 133 134 ; CHECK-LABEL: @test9 135 ; CHECK: stw 136 ; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 137 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 138 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 139 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 140 ; CHECK: qvfsel 1, [[REG4]], 1, 2 141 ; CHECK: blr 142 } 143 144
