1 ; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s 2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.) 3 ; rdar://11331541 4 5 define i32 @t(i32 %a) nounwind { 6 ; CHECK-LABEL: t: 7 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31 8 ; CHECK: eors [[REG2]], [[REG1]] 9 %tmp0 = ashr i32 %a, 31 10 %tmp1 = xor i32 %tmp0, %a 11 ret i32 %tmp1 12 } 13
