1 /* 2 * 3 * Copyright (c) International Business Machines Corp., 2001 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 13 * the GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 20 /* 21 * Remember that you want to seperate your header 22 * files between what is needed in kernel space 23 * only, and what will also be needed by a user 24 * space program that is using this module. For 25 * that reason keep all structures that will need 26 * kernel space pointers in a seperate header file 27 * from where ioctl flags aer kept 28 * 29 * author: Kai Zhao 30 * date: 08/25/2003 31 * 32 */ 33 34 struct ltpmod_user { 35 36 //put any pointers in here that might be needed by other ioctl calls 37 38 }; 39 typedef struct ltpmod_user ltpmod_user_t; 40 static struct agp_bridge_data *tmp_bridge = NULL; 41 //static struct agp_memory *tmp_agp_memory = NULL; 42 43 44 45 46 47 #include <asm/agp.h> // for flush_agp_cache() 48 49 #define PFX "agpgart: " 50 51 extern struct agp_bridge_data *agp_bridge; 52 53 enum aper_size_type { 54 U8_APER_SIZE, 55 U16_APER_SIZE, 56 U32_APER_SIZE, 57 LVL2_APER_SIZE, 58 FIXED_APER_SIZE 59 }; 60 61 struct gatt_mask { 62 unsigned long mask; 63 u32 type; 64 // totally device specific, for integrated chipsets that 65 // might have different types of memory masks. For other 66 // devices this will probably be ignored 67 }; 68 69 struct aper_size_info_8 { 70 int size; 71 int num_entries; 72 int page_order; 73 u8 size_value; 74 }; 75 76 struct aper_size_info_16 { 77 int size; 78 int num_entries; 79 int page_order; 80 u16 size_value; 81 }; 82 83 struct aper_size_info_32 { 84 int size; 85 int num_entries; 86 int page_order; 87 u32 size_value; 88 }; 89 90 struct aper_size_info_lvl2 { 91 int size; 92 int num_entries; 93 u32 size_value; 94 }; 95 96 struct aper_size_info_fixed { 97 int size; 98 int num_entries; 99 int page_order; 100 }; 101 102 struct agp_bridge_driver { 103 struct module *owner; 104 void *aperture_sizes; 105 int num_aperture_sizes; 106 enum aper_size_type size_type; 107 int cant_use_aperture; 108 int needs_scratch_page; 109 struct gatt_mask *masks; 110 int (*fetch_size)(void); 111 int (*configure)(void); 112 void (*agp_enable)(u32); 113 void (*cleanup)(void); 114 void (*tlb_flush)(struct agp_memory *); 115 unsigned long (*mask_memory)(unsigned long, int); 116 void (*cache_flush)(void); 117 int (*create_gatt_table)(void); 118 int (*free_gatt_table)(void); 119 int (*insert_memory)(struct agp_memory *, off_t, int); 120 int (*remove_memory)(struct agp_memory *, off_t, int); 121 struct agp_memory *(*alloc_by_type) (size_t, int); 122 void (*free_by_type)(struct agp_memory *); 123 void *(*agp_alloc_page)(void); 124 void (*agp_destroy_page)(void *); 125 }; 126 127 struct agp_bridge_data { 128 struct agp_version *version; 129 struct agp_bridge_driver *driver; 130 struct vm_operations_struct *vm_ops; 131 void *previous_size; 132 void *current_size; 133 void *dev_private_data; 134 struct pci_dev *dev; 135 u32 *gatt_table; 136 u32 *gatt_table_real; 137 unsigned long scratch_page; 138 unsigned long scratch_page_real; 139 unsigned long gart_bus_addr; 140 unsigned long gatt_bus_addr; 141 u32 mode; 142 enum chipset_type type; 143 unsigned long *key_list; 144 atomic_t current_memory_agp; 145 atomic_t agp_in_use; 146 int max_memory_agp; // in number of pages 147 int aperture_size_idx; 148 int capndx; 149 char major_version; 150 char minor_version; 151 }; 152 153 #define OUTREG64(mmap, addr, val) __raw_writeq((val), (mmap)+(addr)) 154 #define OUTREG32(mmap, addr, val) __raw_writel((val), (mmap)+(addr)) 155 #define OUTREG16(mmap, addr, val) __raw_writew((val), (mmap)+(addr)) 156 #define OUTREG8(mmap, addr, val) __raw_writeb((val), (mmap)+(addr)) 157 158 #define INREG64(mmap, addr) __raw_readq((mmap)+(addr)) 159 #define INREG32(mmap, addr) __raw_readl((mmap)+(addr)) 160 #define INREG16(mmap, addr) __raw_readw((mmap)+(addr)) 161 #define INREG8(mmap, addr) __raw_readb((mmap)+(addr)) 162 163 #define KB(x) ((x) * 1024) 164 #define MB(x) (KB (KB (x))) 165 #define GB(x) (MB (KB (x))) 166 167 #define A_SIZE_8(x) ((struct aper_size_info_8 *) x) 168 #define A_SIZE_16(x) ((struct aper_size_info_16 *) x) 169 #define A_SIZE_32(x) ((struct aper_size_info_32 *) x) 170 #define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x) 171 #define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x) 172 #define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i) 173 #define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i) 174 #define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i) 175 #define MAXKEY (4096 * 32) 176 177 #define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page) 178 179 // intel register 180 #define INTEL_APBASE 0x10 181 #define INTEL_APSIZE 0xb4 182 #define INTEL_ATTBASE 0xb8 183 #define INTEL_AGPCTRL 0xb0 184 #define INTEL_NBXCFG 0x50 185 #define INTEL_ERRSTS 0x91 186 187 // Intel 460GX Registers 188 #define INTEL_I460_APBASE 0x10 189 #define INTEL_I460_BAPBASE 0x98 190 #define INTEL_I460_GXBCTL 0xa0 191 #define INTEL_I460_AGPSIZ 0xa2 192 #define INTEL_I460_ATTBASE 0xfe200000 193 #define INTEL_I460_GATT_VALID (1UL << 24) 194 #define INTEL_I460_GATT_COHERENT (1UL << 25) 195 196 // intel i830 registers 197 #define I830_GMCH_CTRL 0x52 198 #define I830_GMCH_ENABLED 0x4 199 #define I830_GMCH_MEM_MASK 0x1 200 #define I830_GMCH_MEM_64M 0x1 201 #define I830_GMCH_MEM_128M 0 202 #define I830_GMCH_GMS_MASK 0x70 203 #define I830_GMCH_GMS_DISABLED 0x00 204 #define I830_GMCH_GMS_LOCAL 0x10 205 #define I830_GMCH_GMS_STOLEN_512 0x20 206 #define I830_GMCH_GMS_STOLEN_1024 0x30 207 #define I830_GMCH_GMS_STOLEN_8192 0x40 208 #define I830_RDRAM_CHANNEL_TYPE 0x03010 209 #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) 210 #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) 211 212 // This one is for I830MP w. an external graphic card 213 #define INTEL_I830_ERRSTS 0x92 214 215 // Intel 855GM/852GM registers 216 #define I855_GMCH_GMS_STOLEN_0M 0x0 217 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 218 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 219 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 220 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 221 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 222 #define I85X_CAPID 0x44 223 #define I85X_VARIANT_MASK 0x7 224 #define I85X_VARIANT_SHIFT 5 225 #define I855_GME 0x0 226 #define I855_GM 0x4 227 #define I852_GME 0x2 228 #define I852_GM 0x5 229 230 // intel 815 register 231 #define INTEL_815_APCONT 0x51 232 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 233 234 // intel i820 registers 235 #define INTEL_I820_RDCR 0x51 236 #define INTEL_I820_ERRSTS 0xc8 237 238 // intel i840 registers 239 #define INTEL_I840_MCHCFG 0x50 240 #define INTEL_I840_ERRSTS 0xc8 241 242 // intel i845 registers 243 #define INTEL_I845_AGPM 0x51 244 #define INTEL_I845_ERRSTS 0xc8 245 246 // intel i850 registers 247 #define INTEL_I850_MCHCFG 0x50 248 #define INTEL_I850_ERRSTS 0xc8 249 250 // intel i860 registers 251 #define INTEL_I860_MCHCFG 0x50 252 #define INTEL_I860_ERRSTS 0xc8 253 254 // intel i810 registers 255 #define I810_GMADDR 0x10 256 #define I810_MMADDR 0x14 257 #define I810_PTE_BASE 0x10000 258 #define I810_PTE_MAIN_UNCACHED 0x00000000 259 #define I810_PTE_LOCAL 0x00000002 260 #define I810_PTE_VALID 0x00000001 261 #define I810_SMRAM_MISCC 0x70 262 #define I810_GFX_MEM_WIN_SIZE 0x00010000 263 #define I810_GFX_MEM_WIN_32M 0x00010000 264 #define I810_GMS 0x000000c0 265 #define I810_GMS_DISABLE 0x00000000 266 #define I810_PGETBL_CTL 0x2020 267 #define I810_PGETBL_ENABLED 0x00000001 268 #define I810_DRAM_CTL 0x3000 269 #define I810_DRAM_ROW_0 0x00000001 270 #define I810_DRAM_ROW_0_SDRAM 0x00000001 271 272 // Intel 7505 registers 273 #define INTEL_I7505_NAPBASELO 0x10 274 #define INTEL_I7505_APSIZE 0x74 275 #define INTEL_I7505_NCAPID 0x60 276 #define INTEL_I7505_NISTAT 0x6c 277 #define INTEL_I7505_ATTBASE 0x78 278 #define INTEL_I7505_ERRSTS 0x42 279 #define INTEL_I7505_AGPCTRL 0x70 280 #define INTEL_I7505_MCHCFG 0x50 281 282 // VIA register 283 #define VIA_APBASE 0x10 284 #define VIA_GARTCTRL 0x80 285 #define VIA_APSIZE 0x84 286 #define VIA_ATTBASE 0x88 287 288 // VIA KT400 289 #define VIA_AGP3_GARTCTRL 0x90 290 #define VIA_AGP3_APSIZE 0x94 291 #define VIA_AGP3_ATTBASE 0x98 292 #define VIA_AGPSEL 0xfd 293 294 // SiS registers 295 #define SIS_APBASE 0x10 296 #define SIS_ATTBASE 0x90 297 #define SIS_APSIZE 0x94 298 #define SIS_TLBCNTRL 0x97 299 #define SIS_TLBFLUSH 0x98 300 301 // AMD registers 302 #define AMD_APBASE 0x10 303 #define AMD_MMBASE 0x14 304 #define AMD_APSIZE 0xac 305 #define AMD_MODECNTL 0xb0 306 #define AMD_MODECNTL2 0xb2 307 #define AMD_GARTENABLE 0x02 // In mmio region (16-bit register) 308 #define AMD_ATTBASE 0x04 // In mmio region (32-bit register) 309 #define AMD_TLBFLUSH 0x0c // In mmio region (32-bit register) 310 #define AMD_CACHEENTRY 0x10 // In mmio region (32-bit register) 311 312 #define AMD_8151_APSIZE 0xb4 313 #define AMD_8151_GARTBLOCK 0xb8 314 315 #define AMD_X86_64_GARTAPERTURECTL 0x90 316 #define AMD_X86_64_GARTAPERTUREBASE 0x94 317 #define AMD_X86_64_GARTTABLEBASE 0x98 318 #define AMD_X86_64_GARTCACHECTL 0x9c 319 #define AMD_X86_64_GARTEN 1<<0 320 321 #define AMD_8151_VMAPERTURE 0x10 322 #define AMD_8151_AGP_CTL 0xb0 323 #define AMD_8151_APERTURESIZE 0xb4 324 #define AMD_8151_GARTPTR 0xb8 325 #define AMD_8151_GTLBEN 1<<7 326 #define AMD_8151_APEREN 1<<8 327 328 // ALi registers 329 #define ALI_APBASE 0x10 330 #define ALI_AGPCTRL 0xb8 331 #define ALI_ATTBASE 0xbc 332 #define ALI_TLBCTRL 0xc0 333 #define ALI_TAGCTRL 0xc4 334 #define ALI_CACHE_FLUSH_CTRL 0xD0 335 #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000 336 #define ALI_CACHE_FLUSH_EN 0x100 337 338 // Serverworks Registers 339 #define SVWRKS_APSIZE 0x10 340 #define SVWRKS_SIZE_MASK 0xfe000000 341 342 #define SVWRKS_MMBASE 0x14 343 #define SVWRKS_CACHING 0x4b 344 #define SVWRKS_FEATURE 0x68 345 346 // func 1 registers 347 #define SVWRKS_AGP_ENABLE 0x60 348 #define SVWRKS_COMMAND 0x04 349 350 // Memory mapped registers 351 #define SVWRKS_GART_CACHE 0x02 352 #define SVWRKS_GATTBASE 0x04 353 #define SVWRKS_TLBFLUSH 0x10 354 #define SVWRKS_POSTFLUSH 0x14 355 #define SVWRKS_DIRFLUSH 0x0c 356 357 // HP ZX1 SBA registers 358 #define HP_ZX1_CTRL 0x200 359 #define HP_ZX1_IBASE 0x300 360 #define HP_ZX1_IMASK 0x308 361 #define HP_ZX1_PCOM 0x310 362 #define HP_ZX1_TCNFG 0x318 363 #define HP_ZX1_PDIR_BASE 0x320 364 #define HP_ZX1_CACHE_FLUSH 0x428 365 366 struct agp_device_ids { 367 unsigned short device_id; // first, to make table easier to read 368 enum chipset_type chipset; 369 const char *chipset_name; 370 int (*chipset_setup) (struct pci_dev *pdev); // used to override generic 371 }; 372 373 // Driver registration 374 struct agp_bridge_data *agp_alloc_bridge(void); 375 void agp_put_bridge(struct agp_bridge_data *bridge); 376 int agp_add_bridge(struct agp_bridge_data *bridge); 377 void agp_remove_bridge(struct agp_bridge_data *bridge); 378 379 // Frontend routines. 380 int agp_frontend_initialize(void); 381 void agp_frontend_cleanup(void); 382 383 // Generic routines. 384 void agp_generic_enable(u32 mode); 385 int agp_generic_create_gatt_table(void); 386 int agp_generic_free_gatt_table(void); 387 struct agp_memory *agp_create_memory(int scratch_pages); 388 int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type); 389 int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type); 390 struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type); 391 void agp_generic_free_by_type(struct agp_memory *curr); 392 void *agp_generic_alloc_page(void); 393 void agp_generic_destroy_page(void *addr); 394 void agp_free_key(int key); 395 int agp_num_entries(void); 396 u32 agp_collect_device_status(u32 mode, u32 command); 397 void agp_device_command(u32 command, int agp_v3); 398 int agp_3_5_enable(struct agp_bridge_data *bridge); 399 void global_cache_flush(void); 400 void get_agp_version(struct agp_bridge_data *bridge); 401 unsigned long agp_generic_mask_memory(unsigned long addr, int type); 402 403 // Standard agp registers 404 #define AGPSTAT 0x4 405 #define AGPCMD 0x8 406 #define AGPNISTAT 0xc 407 #define AGPNEPG 0x16 408 #define AGPNICMD 0x20 409 410 #define AGP_MAJOR_VERSION_SHIFT (20) 411 #define AGP_MINOR_VERSION_SHIFT (16) 412 413 #define AGPSTAT_RQ_DEPTH (0xff000000) 414 415 #define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10) 416 #define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13) 417 #define AGPSTAT_ARQSZ_SHIFT 13 418 419 #define AGPSTAT_SBA (1<<9) 420 #define AGPSTAT_AGP_ENABLE (1<<8) 421 #define AGPSTAT_FW (1<<4) 422 #define AGPSTAT_MODE_3_0 (1<<3) 423 424 #define AGPSTAT2_1X (1<<0) 425 #define AGPSTAT2_2X (1<<1) 426 #define AGPSTAT2_4X (1<<2) 427 428 #define AGPSTAT3_RSVD (1<<2) 429 #define AGPSTAT3_8X (1<<1) 430 #define AGPSTAT3_4X (1) 431 432 433
