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      1 /*
      2  * Copyright (c) 2012-2015 Etnaviv Project
      3  *
      4  * Permission is hereby granted, free of charge, to any person obtaining a
      5  * copy of this software and associated documentation files (the "Software"),
      6  * to deal in the Software without restriction, including without limitation
      7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
      8  * and/or sell copies of the Software, and to permit persons to whom the
      9  * Software is furnished to do so, subject to the following conditions:
     10  *
     11  * The above copyright notice and this permission notice (including the
     12  * next paragraph) shall be included in all copies or substantial portions
     13  * of the Software.
     14  *
     15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
     18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     21  * DEALINGS IN THE SOFTWARE.
     22  *
     23  * Authors:
     24  *    Wladimir J. van der Laan <laanwj (at) gmail.com>
     25  *    Christian Gmeiner <christian.gmeiner (at) gmail.com>
     26  */
     27 
     28 #include "etnaviv_screen.h"
     29 
     30 #include "hw/common.xml.h"
     31 
     32 #include "etnaviv_compiler.h"
     33 #include "etnaviv_context.h"
     34 #include "etnaviv_debug.h"
     35 #include "etnaviv_fence.h"
     36 #include "etnaviv_format.h"
     37 #include "etnaviv_query.h"
     38 #include "etnaviv_resource.h"
     39 #include "etnaviv_translate.h"
     40 
     41 #include "os/os_time.h"
     42 #include "util/u_math.h"
     43 #include "util/u_memory.h"
     44 #include "util/u_string.h"
     45 
     46 #include "state_tracker/drm_driver.h"
     47 
     48 static const struct debug_named_value debug_options[] = {
     49    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
     50    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
     51    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
     52    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
     53    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
     54    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
     55    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
     56    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
     57    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
     58    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
     59    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
     60    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
     61    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
     62    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
     63    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
     64    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
     65    DEBUG_NAMED_VALUE_END
     66 };
     67 
     68 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
     69 int etna_mesa_debug = 0;
     70 
     71 static void
     72 etna_screen_destroy(struct pipe_screen *pscreen)
     73 {
     74    struct etna_screen *screen = etna_screen(pscreen);
     75 
     76    if (screen->pipe)
     77       etna_pipe_del(screen->pipe);
     78 
     79    if (screen->gpu)
     80       etna_gpu_del(screen->gpu);
     81 
     82    if (screen->ro)
     83       FREE(screen->ro);
     84 
     85    if (screen->dev)
     86       etna_device_del(screen->dev);
     87 
     88    FREE(screen);
     89 }
     90 
     91 static const char *
     92 etna_screen_get_name(struct pipe_screen *pscreen)
     93 {
     94    struct etna_screen *priv = etna_screen(pscreen);
     95    static char buffer[128];
     96 
     97    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
     98                  priv->revision);
     99 
    100    return buffer;
    101 }
    102 
    103 static const char *
    104 etna_screen_get_vendor(struct pipe_screen *pscreen)
    105 {
    106    return "etnaviv";
    107 }
    108 
    109 static const char *
    110 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
    111 {
    112    return "Vivante";
    113 }
    114 
    115 static int
    116 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    117 {
    118    struct etna_screen *screen = etna_screen(pscreen);
    119 
    120    switch (param) {
    121    /* Supported features (boolean caps). */
    122    case PIPE_CAP_TWO_SIDED_STENCIL:
    123    case PIPE_CAP_ANISOTROPIC_FILTER:
    124    case PIPE_CAP_POINT_SPRITE:
    125    case PIPE_CAP_TEXTURE_SHADOW_MAP:
    126    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
    127    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
    128    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
    129    case PIPE_CAP_SM3:
    130    case PIPE_CAP_TEXTURE_BARRIER:
    131    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
    132    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
    133    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
    134    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
    135    case PIPE_CAP_USER_CONSTANT_BUFFERS:
    136    case PIPE_CAP_TGSI_TEXCOORD:
    137    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
    138       return 1;
    139 
    140    /* Memory */
    141    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
    142       return 256;
    143    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
    144       return 4; /* XXX could easily be supported */
    145    case PIPE_CAP_GLSL_FEATURE_LEVEL:
    146       return 120;
    147 
    148    case PIPE_CAP_NPOT_TEXTURES:
    149       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
    150                       NON_POWER_OF_TWO); */
    151 
    152    case PIPE_CAP_PRIMITIVE_RESTART:
    153       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
    154 
    155    case PIPE_CAP_ENDIANNESS:
    156       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
    157                                     ENDIANNESS_CONFIG) */
    158 
    159    /* Unsupported features. */
    160    case PIPE_CAP_SEAMLESS_CUBE_MAP:
    161    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
    162    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
    163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
    164    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
    165    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
    166    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
    167    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
    168    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
    169    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
    170    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
    171    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
    172    case PIPE_CAP_INDEP_BLEND_ENABLE:
    173    case PIPE_CAP_INDEP_BLEND_FUNC:
    174    case PIPE_CAP_DEPTH_CLIP_DISABLE:
    175    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
    176    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
    177    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
    178    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
    179    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
    180    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
    181    case PIPE_CAP_USER_VERTEX_BUFFERS:
    182    case PIPE_CAP_USER_INDEX_BUFFERS:
    183    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
    184    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
    185    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
    186    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
    187    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
    188    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
    189    case PIPE_CAP_TEXTURE_GATHER_SM5:
    190    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
    191    case PIPE_CAP_FAKE_SW_MSAA:
    192    case PIPE_CAP_TEXTURE_QUERY_LOD:
    193    case PIPE_CAP_SAMPLE_SHADING:
    194    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
    195    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
    196    case PIPE_CAP_DRAW_INDIRECT:
    197    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
    198    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
    199    case PIPE_CAP_SAMPLER_VIEW_TARGET:
    200    case PIPE_CAP_CLIP_HALFZ:
    201    case PIPE_CAP_VERTEXID_NOBASE:
    202    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
    203    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
    204    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
    205    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
    206    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
    207    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
    208    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
    209    case PIPE_CAP_DEPTH_BOUNDS_TEST:
    210    case PIPE_CAP_TGSI_TXQS:
    211    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
    212    case PIPE_CAP_SHAREABLE_SHADERS:
    213    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
    214    case PIPE_CAP_CLEAR_TEXTURE:
    215    case PIPE_CAP_DRAW_PARAMETERS:
    216    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
    217    case PIPE_CAP_MULTI_DRAW_INDIRECT:
    218    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
    219    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
    220    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
    221    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
    222    case PIPE_CAP_INVALIDATE_BUFFER:
    223    case PIPE_CAP_GENERATE_MIPMAP:
    224    case PIPE_CAP_STRING_MARKER:
    225    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
    226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
    227    case PIPE_CAP_QUERY_MEMORY_INFO:
    228    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
    229    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
    230    case PIPE_CAP_CULL_DISTANCE:
    231    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
    232    case PIPE_CAP_TGSI_VOTE:
    233    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
    234    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
    235    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
    236    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
    237    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
    238    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
    239    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
    240    case PIPE_CAP_NATIVE_FENCE_FD:
    241    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    242    case PIPE_CAP_TGSI_FS_FBFETCH:
    243       return 0;
    244 
    245    /* Stream output. */
    246    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
    247    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
    248    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
    249    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
    250       return 0;
    251 
    252    /* Geometry shader output, unsupported. */
    253    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
    254    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
    255    case PIPE_CAP_MAX_VERTEX_STREAMS:
    256       return 0;
    257 
    258    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
    259       return 128;
    260 
    261    /* Texturing. */
    262    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
    263    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
    264    {
    265       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
    266       assert(log2_max_tex_size > 0);
    267       return log2_max_tex_size;
    268    }
    269    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
    270       return 5;
    271    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
    272       return 0;
    273    case PIPE_CAP_CUBE_MAP_ARRAY:
    274       return 0;
    275    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
    276    case PIPE_CAP_MIN_TEXEL_OFFSET:
    277       return -8;
    278    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
    279    case PIPE_CAP_MAX_TEXEL_OFFSET:
    280       return 7;
    281    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
    282       return 0;
    283    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
    284       return 65536;
    285 
    286    /* Render targets. */
    287    case PIPE_CAP_MAX_RENDER_TARGETS:
    288       return 1;
    289 
    290    /* Viewports and scissors. */
    291    case PIPE_CAP_MAX_VIEWPORTS:
    292       return 1;
    293 
    294    /* Timer queries. */
    295    case PIPE_CAP_QUERY_TIME_ELAPSED:
    296    case PIPE_CAP_OCCLUSION_QUERY:
    297       return 0;
    298    case PIPE_CAP_QUERY_TIMESTAMP:
    299       return 1;
    300    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
    301       return 0;
    302 
    303    /* Preferences */
    304    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
    305       return 0;
    306 
    307    case PIPE_CAP_PCI_GROUP:
    308    case PIPE_CAP_PCI_BUS:
    309    case PIPE_CAP_PCI_DEVICE:
    310    case PIPE_CAP_PCI_FUNCTION:
    311       return 0;
    312    case PIPE_CAP_VENDOR_ID:
    313    case PIPE_CAP_DEVICE_ID:
    314       return 0xFFFFFFFF;
    315    case PIPE_CAP_ACCELERATED:
    316       return 1;
    317    case PIPE_CAP_VIDEO_MEMORY:
    318       return 0;
    319    case PIPE_CAP_UMA:
    320       return 1;
    321    }
    322 
    323    debug_printf("unknown param %d", param);
    324    return 0;
    325 }
    326 
    327 static float
    328 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
    329 {
    330    switch (param) {
    331    case PIPE_CAPF_MAX_LINE_WIDTH:
    332    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
    333    case PIPE_CAPF_MAX_POINT_WIDTH:
    334    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
    335       return 8192.0f;
    336    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
    337       return 16.0f;
    338    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
    339       return 16.0f;
    340    case PIPE_CAPF_GUARD_BAND_LEFT:
    341    case PIPE_CAPF_GUARD_BAND_TOP:
    342    case PIPE_CAPF_GUARD_BAND_RIGHT:
    343    case PIPE_CAPF_GUARD_BAND_BOTTOM:
    344       return 0.0f;
    345    }
    346 
    347    debug_printf("unknown paramf %d", param);
    348    return 0;
    349 }
    350 
    351 static int
    352 etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
    353                              enum pipe_shader_cap param)
    354 {
    355    struct etna_screen *screen = etna_screen(pscreen);
    356 
    357    switch (shader) {
    358    case PIPE_SHADER_FRAGMENT:
    359    case PIPE_SHADER_VERTEX:
    360       break;
    361    case PIPE_SHADER_COMPUTE:
    362    case PIPE_SHADER_GEOMETRY:
    363    case PIPE_SHADER_TESS_CTRL:
    364    case PIPE_SHADER_TESS_EVAL:
    365       return 0;
    366    default:
    367       DBG("unknown shader type %d", shader);
    368       return 0;
    369    }
    370 
    371    switch (param) {
    372    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
    373    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
    374    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
    375    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
    376       return ETNA_MAX_TOKENS;
    377    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
    378       return ETNA_MAX_DEPTH; /* XXX */
    379    case PIPE_SHADER_CAP_MAX_INPUTS:
    380       /* Maximum number of inputs for the vertex shader is the number
    381        * of vertex elements - each element defines one vertex shader
    382        * input register.  For the fragment shader, this is the number
    383        * of varyings. */
    384       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
    385                                             : screen->specs.vertex_max_elements;
    386    case PIPE_SHADER_CAP_MAX_OUTPUTS:
    387       return 16; /* see VIVS_VS_OUTPUT */
    388    case PIPE_SHADER_CAP_MAX_TEMPS:
    389       return 64; /* Max native temporaries. */
    390    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
    391       return 1;
    392    case PIPE_SHADER_CAP_MAX_PREDS:
    393       return 0; /* nothing uses this */
    394    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
    395       return 1;
    396    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
    397    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
    398    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
    399    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
    400       return 1;
    401    case PIPE_SHADER_CAP_SUBROUTINES:
    402       return 0;
    403    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
    404       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
    405    case PIPE_SHADER_CAP_INTEGERS:
    406       return 0;
    407    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
    408    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
    409       return shader == PIPE_SHADER_FRAGMENT
    410                 ? screen->specs.fragment_sampler_count
    411                 : screen->specs.vertex_sampler_count;
    412    case PIPE_SHADER_CAP_PREFERRED_IR:
    413       return PIPE_SHADER_IR_TGSI;
    414    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
    415       return 4096;
    416    case PIPE_SHADER_CAP_DOUBLES:
    417    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
    418    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
    419    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    420    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
    421       return false;
    422    case PIPE_SHADER_CAP_SUPPORTED_IRS:
    423       return 0;
    424    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
    425       return 32;
    426    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
    427    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
    428    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
    429       return 0;
    430    }
    431 
    432    debug_printf("unknown shader param %d", param);
    433    return 0;
    434 }
    435 
    436 static uint64_t
    437 etna_screen_get_timestamp(struct pipe_screen *pscreen)
    438 {
    439    return os_time_get_nano();
    440 }
    441 
    442 static bool
    443 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
    444 {
    445    if (fmt == TEXTURE_FORMAT_ETC1)
    446       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
    447 
    448    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
    449       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
    450 
    451    return true;
    452 }
    453 
    454 static boolean
    455 etna_screen_is_format_supported(struct pipe_screen *pscreen,
    456                                 enum pipe_format format,
    457                                 enum pipe_texture_target target,
    458                                 unsigned sample_count, unsigned usage)
    459 {
    460    struct etna_screen *screen = etna_screen(pscreen);
    461    unsigned allowed = 0;
    462 
    463    if (target != PIPE_BUFFER &&
    464        target != PIPE_TEXTURE_1D &&
    465        target != PIPE_TEXTURE_2D &&
    466        target != PIPE_TEXTURE_3D &&
    467        target != PIPE_TEXTURE_CUBE &&
    468        target != PIPE_TEXTURE_RECT)
    469       return FALSE;
    470 
    471    if (usage & PIPE_BIND_RENDER_TARGET) {
    472       /* If render target, must be RS-supported format that is not rb swapped.
    473        * Exposing rb swapped (or other swizzled) formats for rendering would
    474        * involve swizzing in the pixel shader.
    475        */
    476       if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) {
    477          /* Validate MSAA; number of samples must be allowed, and render target
    478           * must have MSAA'able format. */
    479          if (sample_count > 1) {
    480             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
    481                 translate_msaa_format(format) != ETNA_NO_MATCH) {
    482                allowed |= PIPE_BIND_RENDER_TARGET;
    483             }
    484          } else {
    485             allowed |= PIPE_BIND_RENDER_TARGET;
    486          }
    487       }
    488    }
    489 
    490    if (usage & PIPE_BIND_DEPTH_STENCIL) {
    491       if (translate_depth_format(format) != ETNA_NO_MATCH)
    492          allowed |= PIPE_BIND_DEPTH_STENCIL;
    493    }
    494 
    495    if (usage & PIPE_BIND_SAMPLER_VIEW) {
    496       uint32_t fmt = translate_texture_format(format);
    497 
    498       if (!gpu_supports_texure_format(screen, fmt))
    499          fmt = ETNA_NO_MATCH;
    500 
    501       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
    502          allowed |= PIPE_BIND_SAMPLER_VIEW;
    503    }
    504 
    505    if (usage & PIPE_BIND_VERTEX_BUFFER) {
    506       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
    507          allowed |= PIPE_BIND_VERTEX_BUFFER;
    508    }
    509 
    510    if (usage & PIPE_BIND_INDEX_BUFFER) {
    511       /* must be supported index format */
    512       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
    513           (format == PIPE_FORMAT_I32_UINT &&
    514            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
    515          allowed |= PIPE_BIND_INDEX_BUFFER;
    516       }
    517    }
    518 
    519    /* Always allowed */
    520    allowed |=
    521       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
    522 
    523    if (usage != allowed) {
    524       DBG("not supported: format=%s, target=%d, sample_count=%d, "
    525           "usage=%x, allowed=%x",
    526           util_format_name(format), target, sample_count, usage, allowed);
    527    }
    528 
    529    return usage == allowed;
    530 }
    531 
    532 static boolean
    533 etna_get_specs(struct etna_screen *screen)
    534 {
    535    uint64_t val;
    536    uint32_t instruction_count;
    537 
    538    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
    539       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
    540       goto fail;
    541    }
    542    instruction_count = val;
    543 
    544    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
    545                           &val)) {
    546       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
    547       goto fail;
    548    }
    549    screen->specs.vertex_output_buffer_size = val;
    550 
    551    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
    552       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
    553       goto fail;
    554    }
    555    screen->specs.vertex_cache_size = val;
    556 
    557    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
    558       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
    559       goto fail;
    560    }
    561    screen->specs.shader_core_count = val;
    562 
    563    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
    564       DBG("could not get ETNA_GPU_STREAM_COUNT");
    565       goto fail;
    566    }
    567    screen->specs.stream_count = val;
    568 
    569    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
    570       DBG("could not get ETNA_GPU_REGISTER_MAX");
    571       goto fail;
    572    }
    573    screen->specs.max_registers = val;
    574 
    575    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
    576       DBG("could not get ETNA_GPU_PIXEL_PIPES");
    577       goto fail;
    578    }
    579    screen->specs.pixel_pipes = val;
    580 
    581    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
    582       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
    583       goto fail;
    584    }
    585    if (val == 0) {
    586       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
    587       val = 168;
    588    }
    589    screen->specs.num_constants = val;
    590 
    591    screen->specs.can_supertile =
    592       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
    593    screen->specs.bits_per_tile =
    594       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
    595    screen->specs.ts_clear_value =
    596       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
    597                                                            : 0x11111111;
    598 
    599    /* vertex and fragment samplers live in one address space */
    600    screen->specs.vertex_sampler_offset = 8;
    601    screen->specs.fragment_sampler_count = 8;
    602    screen->specs.vertex_sampler_count = 4;
    603    screen->specs.vs_need_z_div =
    604       screen->model < 0x1000 && screen->model != 0x880;
    605    screen->specs.has_sin_cos_sqrt =
    606       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
    607    screen->specs.has_sign_floor_ceil =
    608       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
    609    screen->specs.has_shader_range_registers =
    610       screen->model >= 0x1000 || screen->model == 0x880;
    611    screen->specs.npot_tex_any_wrap =
    612       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
    613    screen->specs.has_new_sin_cos =
    614       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
    615 
    616    if (instruction_count > 256) { /* unified instruction memory? */
    617       screen->specs.vs_offset = 0xC000;
    618       screen->specs.ps_offset = 0xD000; /* like vivante driver */
    619       screen->specs.max_instructions = 256;
    620    } else {
    621       screen->specs.vs_offset = 0x4000;
    622       screen->specs.ps_offset = 0x6000;
    623       screen->specs.max_instructions = instruction_count / 2;
    624    }
    625 
    626    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
    627       screen->specs.max_varyings = 12;
    628       screen->specs.vertex_max_elements = 16;
    629    } else {
    630       screen->specs.max_varyings = 8;
    631       /* Etna_viv documentation seems confused over the correct value
    632        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
    633        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
    634       screen->specs.vertex_max_elements = 10;
    635    }
    636 
    637    /* Etna_viv documentation does not indicate where varyings above 8 are
    638     * stored. Moreover, if we are passed more than 8 varyings, we will
    639     * walk off the end of some arrays. Limit the maximum number of varyings. */
    640    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
    641       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
    642 
    643    /* from QueryShaderCaps in kernel driver */
    644    if (screen->model < chipModel_GC4000) {
    645       screen->specs.max_vs_uniforms = 168;
    646       screen->specs.max_ps_uniforms = 64;
    647    } else {
    648       screen->specs.max_vs_uniforms = 256;
    649       screen->specs.max_ps_uniforms = 256;
    650    }
    651 
    652    screen->specs.max_texture_size =
    653       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
    654    screen->specs.max_rendertarget_size =
    655       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
    656 
    657    return true;
    658 
    659 fail:
    660    return false;
    661 }
    662 
    663 boolean
    664 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
    665                           unsigned stride, struct winsys_handle *whandle)
    666 {
    667    whandle->stride = stride;
    668 
    669    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
    670       return etna_bo_get_name(bo, &whandle->handle) == 0;
    671    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
    672       whandle->handle = etna_bo_handle(bo);
    673       return TRUE;
    674    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
    675       whandle->handle = etna_bo_dmabuf(bo);
    676       return TRUE;
    677    } else {
    678       return FALSE;
    679    }
    680 }
    681 
    682 struct etna_bo *
    683 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
    684                            struct winsys_handle *whandle, unsigned *out_stride)
    685 {
    686    struct etna_screen *screen = etna_screen(pscreen);
    687    struct etna_bo *bo;
    688 
    689    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
    690       bo = etna_bo_from_name(screen->dev, whandle->handle);
    691    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
    692       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
    693    } else {
    694       DBG("Attempt to import unsupported handle type %d", whandle->type);
    695       return NULL;
    696    }
    697 
    698    if (!bo) {
    699       DBG("ref name 0x%08x failed", whandle->handle);
    700       return NULL;
    701    }
    702 
    703    *out_stride = whandle->stride;
    704 
    705    return bo;
    706 }
    707 
    708 struct pipe_screen *
    709 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
    710                    struct renderonly *ro)
    711 {
    712    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
    713    struct pipe_screen *pscreen;
    714    uint64_t val;
    715 
    716    if (!screen)
    717       return NULL;
    718 
    719    pscreen = &screen->base;
    720    screen->dev = dev;
    721    screen->gpu = gpu;
    722    screen->ro = renderonly_dup(ro);
    723 
    724    if (!screen->ro) {
    725       DBG("could not create renderonly object");
    726       goto fail;
    727    }
    728 
    729    etna_mesa_debug = debug_get_option_etna_mesa_debug();
    730 
    731    /* FIXME: Disable tile status for stability at the moment */
    732    etna_mesa_debug |= ETNA_DBG_NO_TS;
    733 
    734    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
    735    if (!screen->pipe) {
    736       DBG("could not create 3d pipe");
    737       goto fail;
    738    }
    739 
    740    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
    741       DBG("could not get ETNA_GPU_MODEL");
    742       goto fail;
    743    }
    744    screen->model = val;
    745 
    746    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
    747       DBG("could not get ETNA_GPU_REVISION");
    748       goto fail;
    749    }
    750    screen->revision = val;
    751 
    752    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
    753       DBG("could not get ETNA_GPU_FEATURES_0");
    754       goto fail;
    755    }
    756    screen->features[0] = val;
    757 
    758    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
    759       DBG("could not get ETNA_GPU_FEATURES_1");
    760       goto fail;
    761    }
    762    screen->features[1] = val;
    763 
    764    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
    765       DBG("could not get ETNA_GPU_FEATURES_2");
    766       goto fail;
    767    }
    768    screen->features[2] = val;
    769 
    770    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
    771       DBG("could not get ETNA_GPU_FEATURES_3");
    772       goto fail;
    773    }
    774    screen->features[3] = val;
    775 
    776    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
    777       DBG("could not get ETNA_GPU_FEATURES_4");
    778       goto fail;
    779    }
    780    screen->features[4] = val;
    781 
    782    if (!etna_get_specs(screen))
    783       goto fail;
    784 
    785    pscreen->destroy = etna_screen_destroy;
    786    pscreen->get_param = etna_screen_get_param;
    787    pscreen->get_paramf = etna_screen_get_paramf;
    788    pscreen->get_shader_param = etna_screen_get_shader_param;
    789 
    790    pscreen->get_name = etna_screen_get_name;
    791    pscreen->get_vendor = etna_screen_get_vendor;
    792    pscreen->get_device_vendor = etna_screen_get_device_vendor;
    793 
    794    pscreen->get_timestamp = etna_screen_get_timestamp;
    795    pscreen->context_create = etna_context_create;
    796    pscreen->is_format_supported = etna_screen_is_format_supported;
    797 
    798    etna_fence_screen_init(pscreen);
    799    etna_query_screen_init(pscreen);
    800    etna_resource_screen_init(pscreen);
    801 
    802    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
    803 
    804    return pscreen;
    805 
    806 fail:
    807    etna_screen_destroy(pscreen);
    808    return NULL;
    809 }
    810