1 /* 2 * Copyright 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <stdint.h> 25 26 #define __gen_address_type uint64_t 27 #define __gen_user_data void 28 29 static inline uint64_t 30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) 31 { 32 return addr + delta; 33 } 34 35 #include "genxml/gen_macros.h" 36 #include "genxml/genX_pack.h" 37 38 #include "isl_priv.h" 39 40 #define __PASTE2(x, y) x ## y 41 #define __PASTE(x, y) __PASTE2(x, y) 42 #define isl_genX(x) __PASTE(isl_, genX(x)) 43 44 #if GEN_GEN >= 8 45 static const uint8_t isl_to_gen_halign[] = { 46 [4] = HALIGN4, 47 [8] = HALIGN8, 48 [16] = HALIGN16, 49 }; 50 #elif GEN_GEN >= 7 51 static const uint8_t isl_to_gen_halign[] = { 52 [4] = HALIGN_4, 53 [8] = HALIGN_8, 54 }; 55 #endif 56 57 #if GEN_GEN >= 8 58 static const uint8_t isl_to_gen_valign[] = { 59 [4] = VALIGN4, 60 [8] = VALIGN8, 61 [16] = VALIGN16, 62 }; 63 #elif GEN_GEN >= 6 64 static const uint8_t isl_to_gen_valign[] = { 65 [2] = VALIGN_2, 66 [4] = VALIGN_4, 67 }; 68 #endif 69 70 #if GEN_GEN >= 8 71 static const uint8_t isl_to_gen_tiling[] = { 72 [ISL_TILING_LINEAR] = LINEAR, 73 [ISL_TILING_X] = XMAJOR, 74 [ISL_TILING_Y0] = YMAJOR, 75 [ISL_TILING_Yf] = YMAJOR, 76 [ISL_TILING_Ys] = YMAJOR, 77 [ISL_TILING_W] = WMAJOR, 78 }; 79 #endif 80 81 #if GEN_GEN >= 7 82 static const uint32_t isl_to_gen_multisample_layout[] = { 83 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS, 84 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL, 85 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS, 86 }; 87 #endif 88 89 #if GEN_GEN >= 9 90 static const uint32_t isl_to_gen_aux_mode[] = { 91 [ISL_AUX_USAGE_NONE] = AUX_NONE, 92 [ISL_AUX_USAGE_HIZ] = AUX_HIZ, 93 [ISL_AUX_USAGE_MCS] = AUX_CCS_D, 94 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D, 95 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, 96 }; 97 #elif GEN_GEN >= 8 98 static const uint32_t isl_to_gen_aux_mode[] = { 99 [ISL_AUX_USAGE_NONE] = AUX_NONE, 100 [ISL_AUX_USAGE_HIZ] = AUX_HIZ, 101 [ISL_AUX_USAGE_MCS] = AUX_MCS, 102 [ISL_AUX_USAGE_CCS_D] = AUX_MCS, 103 }; 104 #endif 105 106 static uint8_t 107 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) 108 { 109 switch (dim) { 110 default: 111 unreachable("bad isl_surf_dim"); 112 case ISL_SURF_DIM_1D: 113 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); 114 return SURFTYPE_1D; 115 case ISL_SURF_DIM_2D: 116 if ((usage & ISL_SURF_USAGE_CUBE_BIT) && 117 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) { 118 /* We need SURFTYPE_CUBE to make cube sampling work */ 119 return SURFTYPE_CUBE; 120 } else { 121 /* Everything else (render and storage) treat cubes as plain 122 * 2D array textures 123 */ 124 return SURFTYPE_2D; 125 } 126 case ISL_SURF_DIM_3D: 127 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); 128 return SURFTYPE_3D; 129 } 130 } 131 132 /** 133 * Get the horizontal and vertical alignment in the units expected by the 134 * hardware. Note that this does NOT give you the actual hardware enum values 135 * but an index into the isl_to_gen_[hv]align arrays above. 136 */ 137 static inline struct isl_extent3d 138 get_image_alignment(const struct isl_surf *surf) 139 { 140 if (GEN_GEN >= 9) { 141 if (isl_tiling_is_std_y(surf->tiling) || 142 surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { 143 /* The hardware ignores the alignment values. Anyway, the surface's 144 * true alignment is likely outside the enum range of HALIGN* and 145 * VALIGN*. 146 */ 147 return isl_extent3d(4, 4, 1); 148 } else { 149 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units 150 * of surface elements (not pixels nor samples). For compressed formats, 151 * a "surface element" is defined as a compression block. For example, 152 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2 153 * format (ETC2 has a block height of 4), then the vertical alignment is 154 * 4 compression blocks or, equivalently, 16 pixels. 155 */ 156 return isl_surf_get_image_alignment_el(surf); 157 } 158 } else { 159 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in 160 * units of surface samples. For example, if SurfaceVerticalAlignment 161 * is VALIGN_4 and the surface is singlesampled, then for any surface 162 * format (compressed or not) the vertical alignment is 163 * 4 pixels. 164 */ 165 return isl_surf_get_image_alignment_sa(surf); 166 } 167 } 168 169 #if GEN_GEN >= 8 170 static uint32_t 171 get_qpitch(const struct isl_surf *surf) 172 { 173 switch (surf->dim_layout) { 174 default: 175 unreachable("Bad isl_surf_dim"); 176 case ISL_DIM_LAYOUT_GEN4_2D: 177 if (GEN_GEN >= 9) { 178 if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) { 179 /* This is rather annoying and completely undocumented. It 180 * appears that the hardware has a bug (or undocumented feature) 181 * regarding stencil buffers most likely related to the way 182 * W-tiling is handled as modified Y-tiling. If you bind a 3-D 183 * stencil buffer normally, and use texelFetch on it, the z or 184 * array index will get implicitly multiplied by 2 for no obvious 185 * reason. The fix appears to be to divide qpitch by 2 for 186 * W-tiled surfaces. 187 */ 188 return isl_surf_get_array_pitch_el_rows(surf) / 2; 189 } else { 190 return isl_surf_get_array_pitch_el_rows(surf); 191 } 192 } else { 193 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch 194 * 195 * "This field must be set to an integer multiple of the Surface 196 * Vertical Alignment. For compressed textures (BC*, FXT1, 197 * ETC*, and EAC* Surface Formats), this field is in units of 198 * rows in the uncompressed surface, and must be set to an 199 * integer multiple of the vertical alignment parameter "j" 200 * defined in the Common Surface Formats section." 201 */ 202 return isl_surf_get_array_pitch_sa_rows(surf); 203 } 204 case ISL_DIM_LAYOUT_GEN9_1D: 205 /* QPitch is usually expressed as rows of surface elements (where 206 * a surface element is an compression block or a single surface 207 * sample). Skylake 1D is an outlier. 208 * 209 * From the Skylake BSpec >> Memory Views >> Common Surface 210 * Formats >> Surface Layout and Tiling >> 1D Surfaces: 211 * 212 * Surface QPitch specifies the distance in pixels between array 213 * slices. 214 */ 215 return isl_surf_get_array_pitch_el(surf); 216 case ISL_DIM_LAYOUT_GEN4_3D: 217 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a 218 * different pitch at each LOD. Also, the QPitch field is ignored for 219 * these surfaces. From the Broadwell PRM documentation for QPitch: 220 * 221 * This field specifies the distance in rows between array slices. It 222 * is used only in the following cases: 223 * - Surface Array is enabled OR 224 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled 225 * Surface Storage Format set to MSFMT_MSS OR 226 * - Surface Type is SURFTYPE_CUBE 227 * 228 * None of the three conditions above can possibly apply to a 3D surface 229 * so it is safe to just set QPitch to 0. 230 */ 231 return 0; 232 } 233 } 234 #endif /* GEN_GEN >= 8 */ 235 236 void 237 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, 238 const struct isl_surf_fill_state_info *restrict info) 239 { 240 struct GENX(RENDER_SURFACE_STATE) s = { 0 }; 241 242 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage); 243 244 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) 245 assert(isl_format_supports_rendering(dev->info, info->view->format)); 246 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) 247 assert(isl_format_supports_sampling(dev->info, info->view->format)); 248 249 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat 250 * 251 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*) 252 * format if the Surface Type is SURFTYPE_1D 253 */ 254 if (info->surf->dim == ISL_SURF_DIM_1D) 255 assert(!isl_format_is_compressed(info->view->format)); 256 257 s.SurfaceFormat = info->view->format; 258 259 #if GEN_IS_HASWELL 260 s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat); 261 #endif 262 263 assert(info->surf->logical_level0_px.width > 0 && 264 info->surf->logical_level0_px.height > 0); 265 266 s.Width = info->surf->logical_level0_px.width - 1; 267 s.Height = info->surf->logical_level0_px.height - 1; 268 269 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 270 * (Surface Arrays For all surfaces other than separate stencil buffer): 271 * 272 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value 273 * calculated in the equation above , for every other odd Surface Height 274 * starting from 1 i.e. 1,5,9,13" 275 * 276 * Since this Qpitch errata only impacts the sampler, we have to adjust the 277 * input for the rendering surface to achieve the same qpitch. For the 278 * affected heights, we increment the height by 1 for the rendering 279 * surface. 280 */ 281 if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && 282 info->surf->samples > 1 && 283 (info->surf->logical_level0_px.height % 4) == 1) 284 s.Height++; 285 286 switch (s.SurfaceType) { 287 case SURFTYPE_1D: 288 case SURFTYPE_2D: 289 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement: 290 * 291 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field 292 * must be set to zero if this surface is used with sampling engine 293 * messages." 294 * 295 * This restriction appears to exist only on Ivy Bridge. 296 */ 297 if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) && 298 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) && 299 info->surf->samples > 1) 300 assert(info->view->base_array_layer == 0); 301 302 s.MinimumArrayElement = info->view->base_array_layer; 303 304 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: 305 * 306 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced 307 * by one for each increase from zero of Minimum Array Element. For 308 * example, if Minimum Array Element is set to 1024 on a 2D surface, 309 * the range of this field is reduced to [0,1023]. 310 * 311 * In other words, 'Depth' is the number of array layers. 312 */ 313 s.Depth = info->view->array_len - 1; 314 315 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent: 316 * 317 * For Render Target and Typed Dataport 1D and 2D Surfaces: 318 * This field must be set to the same value as the Depth field. 319 */ 320 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | 321 ISL_SURF_USAGE_STORAGE_BIT)) 322 s.RenderTargetViewExtent = s.Depth; 323 break; 324 case SURFTYPE_CUBE: 325 s.MinimumArrayElement = info->view->base_array_layer; 326 /* Same as SURFTYPE_2D, but divided by 6 */ 327 s.Depth = info->view->array_len / 6 - 1; 328 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | 329 ISL_SURF_USAGE_STORAGE_BIT)) 330 s.RenderTargetViewExtent = s.Depth; 331 break; 332 case SURFTYPE_3D: 333 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: 334 * 335 * If the volume texture is MIP-mapped, this field specifies the 336 * depth of the base MIP level. 337 */ 338 s.Depth = info->surf->logical_level0_px.depth - 1; 339 340 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent: 341 * 342 * For Render Target and Typed Dataport 3D Surfaces: This field 343 * indicates the extent of the accessible 'R' coordinates minus 1 on 344 * the LOD currently being rendered to. 345 * 346 * The docs specify that this only matters for render targets and 347 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the 348 * Depth field has more bits than RenderTargetViewExtent so we can have 349 * textures with more levels than we can render to. In order to prevent 350 * assert-failures in the packing function below, we only set the field 351 * when it's actually going to be used by the hardware. 352 * 353 * Similaraly, the MinimumArrayElement field is ignored by all hardware 354 * prior to Sky Lake when texturing and we want it set to 0 anyway. 355 * Since it's already initialized to 0, we can just leave it alone for 356 * texture surfaces. 357 */ 358 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | 359 ISL_SURF_USAGE_STORAGE_BIT)) { 360 s.MinimumArrayElement = info->view->base_array_layer; 361 s.RenderTargetViewExtent = info->view->array_len - 1; 362 } 363 break; 364 default: 365 unreachable("bad SurfaceType"); 366 } 367 368 #if GEN_GEN >= 7 369 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D; 370 #endif 371 372 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { 373 /* For render target surfaces, the hardware interprets field 374 * MIPCount/LOD as LOD. The Broadwell PRM says: 375 * 376 * MIPCountLOD defines the LOD that will be rendered into. 377 * SurfaceMinLOD is ignored. 378 */ 379 s.MIPCountLOD = info->view->base_level; 380 s.SurfaceMinLOD = 0; 381 } else { 382 /* For non render target surfaces, the hardware interprets field 383 * MIPCount/LOD as MIPCount. The range of levels accessible by the 384 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD]. 385 */ 386 s.SurfaceMinLOD = info->view->base_level; 387 s.MIPCountLOD = MAX(info->view->levels, 1) - 1; 388 } 389 390 #if GEN_GEN >= 9 391 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail 392 * Start LOD" to 15 to prevent the hardware from trying to use them. 393 */ 394 s.TiledResourceMode = NONE; 395 s.MipTailStartLOD = 15; 396 #endif 397 398 #if GEN_GEN >= 6 399 const struct isl_extent3d image_align = get_image_alignment(info->surf); 400 s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height]; 401 #if GEN_GEN >= 7 402 s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width]; 403 #endif 404 #endif 405 406 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { 407 /* For gen9 1-D textures, surface pitch is ignored */ 408 s.SurfacePitch = 0; 409 } else { 410 s.SurfacePitch = info->surf->row_pitch - 1; 411 } 412 413 #if GEN_GEN >= 8 414 s.SurfaceQPitch = get_qpitch(info->surf) >> 2; 415 #elif GEN_GEN == 7 416 s.SurfaceArraySpacing = info->surf->array_pitch_span == 417 ISL_ARRAY_PITCH_SPAN_COMPACT; 418 #endif 419 420 #if GEN_GEN >= 8 421 s.TileMode = isl_to_gen_tiling[info->surf->tiling]; 422 #else 423 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, 424 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : 425 TILEWALK_XMAJOR, 426 #endif 427 428 #if GEN_GEN >= 8 429 s.RenderCacheReadWriteMode = WriteOnlyCache; 430 #else 431 s.RenderCacheReadWriteMode = 0; 432 #endif 433 434 if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) { 435 #if GEN_GEN >= 8 436 s.CubeFaceEnablePositiveZ = 1; 437 s.CubeFaceEnableNegativeZ = 1; 438 s.CubeFaceEnablePositiveY = 1; 439 s.CubeFaceEnableNegativeY = 1; 440 s.CubeFaceEnablePositiveX = 1; 441 s.CubeFaceEnableNegativeX = 1; 442 #else 443 s.CubeFaceEnables = 0x3f; 444 #endif 445 } 446 447 #if GEN_GEN >= 6 448 s.NumberofMultisamples = ffs(info->surf->samples) - 1; 449 #if GEN_GEN >= 7 450 s.MultisampledSurfaceStorageFormat = 451 isl_to_gen_multisample_layout[info->surf->msaa_layout]; 452 #endif 453 #endif 454 455 #if (GEN_GEN >= 8 || GEN_IS_HASWELL) 456 s.ShaderChannelSelectRed = info->view->swizzle.r; 457 s.ShaderChannelSelectGreen = info->view->swizzle.g; 458 s.ShaderChannelSelectBlue = info->view->swizzle.b; 459 s.ShaderChannelSelectAlpha = info->view->swizzle.a; 460 #endif 461 462 s.SurfaceBaseAddress = info->address; 463 464 #if GEN_GEN >= 6 465 s.MOCS = info->mocs; 466 #endif 467 468 #if GEN_GEN > 4 || GEN_IS_G4X 469 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) { 470 /* There are fairly strict rules about when the offsets can be used. 471 * These are mostly taken from the Sky Lake PRM documentation for 472 * RENDER_SURFACE_STATE. 473 */ 474 assert(info->surf->tiling != ISL_TILING_LINEAR); 475 assert(info->surf->dim == ISL_SURF_DIM_2D); 476 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb)); 477 assert(info->surf->levels == 1); 478 assert(info->surf->logical_level0_px.array_len == 1); 479 assert(info->aux_usage == ISL_AUX_USAGE_NONE); 480 481 if (GEN_GEN >= 8) { 482 /* Broadwell added more rules. */ 483 assert(info->surf->samples == 1); 484 if (isl_format_get_layout(info->view->format)->bpb == 8) 485 assert(info->x_offset_sa % 16 == 0); 486 if (isl_format_get_layout(info->view->format)->bpb == 16) 487 assert(info->x_offset_sa % 8 == 0); 488 } 489 490 #if GEN_GEN >= 7 491 s.SurfaceArray = false; 492 #endif 493 } 494 495 const unsigned x_div = 4; 496 const unsigned y_div = GEN_GEN >= 8 ? 4 : 2; 497 assert(info->x_offset_sa % x_div == 0); 498 assert(info->y_offset_sa % y_div == 0); 499 s.XOffset = info->x_offset_sa / x_div; 500 s.YOffset = info->y_offset_sa / y_div; 501 #else 502 assert(info->x_offset_sa == 0); 503 assert(info->y_offset_sa == 0); 504 #endif 505 506 #if GEN_GEN >= 7 507 if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) { 508 struct isl_tile_info tile_info; 509 isl_surf_get_tile_info(dev, info->aux_surf, &tile_info); 510 uint32_t pitch_in_tiles = 511 info->aux_surf->row_pitch / tile_info.phys_extent_B.width; 512 513 #if GEN_GEN >= 8 514 assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E); 515 s.AuxiliarySurfacePitch = pitch_in_tiles - 1; 516 /* Auxiliary surfaces in ISL have compressed formats but the hardware 517 * doesn't expect our definition of the compression, it expects qpitch 518 * in units of samples on the main surface. 519 */ 520 s.AuxiliarySurfaceQPitch = 521 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2; 522 s.AuxiliarySurfaceBaseAddress = info->aux_address; 523 524 if (info->aux_usage == ISL_AUX_USAGE_HIZ) { 525 /* The number of samples must be 1 */ 526 assert(info->surf->samples == 1); 527 528 /* The dimension must not be 3D */ 529 assert(info->surf->dim != ISL_SURF_DIM_3D); 530 531 /* The format must be one of the following: */ 532 switch (info->view->format) { 533 case ISL_FORMAT_R32_FLOAT: 534 case ISL_FORMAT_R24_UNORM_X8_TYPELESS: 535 case ISL_FORMAT_R16_UNORM: 536 break; 537 default: 538 assert(!"Incompatible HiZ Sampling format"); 539 break; 540 } 541 } 542 543 s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage]; 544 #else 545 assert(info->aux_usage == ISL_AUX_USAGE_MCS || 546 info->aux_usage == ISL_AUX_USAGE_CCS_D); 547 s.MCSBaseAddress = info->aux_address, 548 s.MCSSurfacePitch = pitch_in_tiles - 1; 549 s.MCSEnable = true; 550 #endif 551 } 552 #endif 553 554 #if GEN_GEN >= 8 555 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 556 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): 557 * 558 * This bit must be set for the following surface types: BC2_UNORM 559 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM 560 */ 561 if (GEN_GEN >= 9 || dev->info->is_cherryview) { 562 switch (info->view->format) { 563 case ISL_FORMAT_BC2_UNORM: 564 case ISL_FORMAT_BC3_UNORM: 565 case ISL_FORMAT_BC5_UNORM: 566 case ISL_FORMAT_BC5_SNORM: 567 case ISL_FORMAT_BC7_UNORM: 568 s.SamplerL2BypassModeDisable = true; 569 break; 570 default: 571 /* From the SKL PRM, Programming Note under Sampler Output Channel 572 * Mapping: 573 * 574 * If a surface has an associated HiZ Auxilliary surface, the 575 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE 576 * must be set. 577 */ 578 if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ) 579 s.SamplerL2BypassModeDisable = true; 580 break; 581 } 582 } 583 #endif 584 585 if (info->aux_usage != ISL_AUX_USAGE_NONE) { 586 #if GEN_GEN >= 9 587 s.RedClearColor = info->clear_color.u32[0]; 588 s.GreenClearColor = info->clear_color.u32[1]; 589 s.BlueClearColor = info->clear_color.u32[2]; 590 s.AlphaClearColor = info->clear_color.u32[3]; 591 #elif GEN_GEN >= 7 592 /* Prior to Sky Lake, we only have one bit for the clear color which 593 * gives us 0 or 1 in whatever the surface's format happens to be. 594 */ 595 if (isl_format_has_int_channel(info->view->format)) { 596 for (unsigned i = 0; i < 4; i++) { 597 assert(info->clear_color.u32[i] == 0 || 598 info->clear_color.u32[i] == 1); 599 } 600 s.RedClearColor = info->clear_color.u32[0] != 0; 601 s.GreenClearColor = info->clear_color.u32[1] != 0; 602 s.BlueClearColor = info->clear_color.u32[2] != 0; 603 s.AlphaClearColor = info->clear_color.u32[3] != 0; 604 } else { 605 for (unsigned i = 0; i < 4; i++) { 606 assert(info->clear_color.f32[i] == 0.0f || 607 info->clear_color.f32[i] == 1.0f); 608 } 609 s.RedClearColor = info->clear_color.f32[0] != 0.0f; 610 s.GreenClearColor = info->clear_color.f32[1] != 0.0f; 611 s.BlueClearColor = info->clear_color.f32[2] != 0.0f; 612 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f; 613 } 614 #endif 615 } 616 617 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); 618 } 619 620 void 621 isl_genX(buffer_fill_state_s)(void *state, 622 const struct isl_buffer_fill_state_info *restrict info) 623 { 624 uint32_t num_elements = info->size / info->stride; 625 626 if (GEN_GEN >= 7) { 627 /* From the IVB PRM, SURFACE_STATE::Height, 628 * 629 * For typed buffer and structured buffer surfaces, the number 630 * of entries in the buffer ranges from 1 to 2^27. For raw buffer 631 * surfaces, the number of entries in the buffer is the number of bytes 632 * which can range from 1 to 2^30. 633 */ 634 if (info->format == ISL_FORMAT_RAW) { 635 assert(num_elements <= (1ull << 30)); 636 assert((num_elements & 3) == 0); 637 } else { 638 assert(num_elements <= (1ull << 27)); 639 } 640 } else { 641 assert(num_elements <= (1ull << 27)); 642 } 643 644 struct GENX(RENDER_SURFACE_STATE) s = { 0, }; 645 646 s.SurfaceType = SURFTYPE_BUFFER; 647 s.SurfaceFormat = info->format; 648 649 #if GEN_GEN >= 6 650 s.SurfaceVerticalAlignment = isl_to_gen_valign[4]; 651 #if GEN_GEN >= 7 652 s.SurfaceHorizontalAlignment = isl_to_gen_halign[4]; 653 s.SurfaceArray = false; 654 #endif 655 #endif 656 657 #if GEN_GEN >= 7 658 s.Height = ((num_elements - 1) >> 7) & 0x3fff; 659 s.Width = (num_elements - 1) & 0x7f; 660 s.Depth = ((num_elements - 1) >> 21) & 0x3ff; 661 #else 662 s.Height = ((num_elements - 1) >> 7) & 0x1fff; 663 s.Width = (num_elements - 1) & 0x7f; 664 s.Depth = ((num_elements - 1) >> 20) & 0x7f; 665 #endif 666 667 s.SurfacePitch = info->stride - 1; 668 669 #if GEN_GEN >= 6 670 s.NumberofMultisamples = MULTISAMPLECOUNT_1; 671 #endif 672 673 #if (GEN_GEN >= 8) 674 s.TileMode = LINEAR; 675 #else 676 s.TiledSurface = false; 677 #endif 678 679 #if (GEN_GEN >= 8) 680 s.RenderCacheReadWriteMode = WriteOnlyCache; 681 #else 682 s.RenderCacheReadWriteMode = 0; 683 #endif 684 685 s.SurfaceBaseAddress = info->address; 686 #if GEN_GEN >= 6 687 s.MOCS = info->mocs; 688 #endif 689 690 #if (GEN_GEN >= 8 || GEN_IS_HASWELL) 691 s.ShaderChannelSelectRed = SCS_RED; 692 s.ShaderChannelSelectGreen = SCS_GREEN; 693 s.ShaderChannelSelectBlue = SCS_BLUE; 694 s.ShaderChannelSelectAlpha = SCS_ALPHA; 695 #endif 696 697 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); 698 } 699
