1 //===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the JIT interfaces for the ARM target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "jit" 15 #include "ARMJITInfo.h" 16 #include "ARMInstrInfo.h" 17 #include "ARMConstantPoolValue.h" 18 #include "ARMRelocations.h" 19 #include "ARMSubtarget.h" 20 #include "llvm/Function.h" 21 #include "llvm/CodeGen/JITCodeEmitter.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include "llvm/Support/Memory.h" 26 #include <cstdlib> 27 using namespace llvm; 28 29 void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { 30 report_fatal_error("ARMJITInfo::replaceMachineCodeForFunction"); 31 } 32 33 /// JITCompilerFunction - This contains the address of the JIT function used to 34 /// compile a function lazily. 35 static TargetJITInfo::JITCompilerFn JITCompilerFunction; 36 37 // Get the ASMPREFIX for the current host. This is often '_'. 38 #ifndef __USER_LABEL_PREFIX__ 39 #define __USER_LABEL_PREFIX__ 40 #endif 41 #define GETASMPREFIX2(X) #X 42 #define GETASMPREFIX(X) GETASMPREFIX2(X) 43 #define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__) 44 45 // CompilationCallback stub - We can't use a C function with inline assembly in 46 // it, because the prolog/epilog inserted by GCC won't work for us. (We need 47 // to preserve more context and manipulate the stack directly). Instead, 48 // write our own wrapper, which does things our way, so we have complete 49 // control over register saving and restoring. 50 extern "C" { 51 #if defined(__arm__) 52 void ARMCompilationCallback(); 53 asm( 54 ".text\n" 55 ".align 2\n" 56 ".globl " ASMPREFIX "ARMCompilationCallback\n" 57 ASMPREFIX "ARMCompilationCallback:\n" 58 // Save caller saved registers since they may contain stuff 59 // for the real target function right now. We have to act as if this 60 // whole compilation callback doesn't exist as far as the caller is 61 // concerned, so we can't just preserve the callee saved regs. 62 "stmdb sp!, {r0, r1, r2, r3, lr}\n" 63 #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) 64 "fstmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n" 65 #endif 66 // The LR contains the address of the stub function on entry. 67 // pass it as the argument to the C part of the callback 68 "mov r0, lr\n" 69 "sub sp, sp, #4\n" 70 // Call the C portion of the callback 71 "bl " ASMPREFIX "ARMCompilationCallbackC\n" 72 "add sp, sp, #4\n" 73 // Restoring the LR to the return address of the function that invoked 74 // the stub and de-allocating the stack space for it requires us to 75 // swap the two saved LR values on the stack, as they're backwards 76 // for what we need since the pop instruction has a pre-determined 77 // order for the registers. 78 // +--------+ 79 // 0 | LR | Original return address 80 // +--------+ 81 // 1 | LR | Stub address (start of stub) 82 // 2-5 | R3..R0 | Saved registers (we need to preserve all regs) 83 // 6-20 | D0..D7 | Saved VFP registers 84 // +--------+ 85 // 86 #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) 87 // Restore VFP caller-saved registers. 88 "fldmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n" 89 #endif 90 // 91 // We need to exchange the values in slots 0 and 1 so we can 92 // return to the address in slot 1 with the address in slot 0 93 // restored to the LR. 94 "ldr r0, [sp,#20]\n" 95 "ldr r1, [sp,#16]\n" 96 "str r1, [sp,#20]\n" 97 "str r0, [sp,#16]\n" 98 // Return to the (newly modified) stub to invoke the real function. 99 // The above twiddling of the saved return addresses allows us to 100 // deallocate everything, including the LR the stub saved, with two 101 // updating load instructions. 102 "ldmia sp!, {r0, r1, r2, r3, lr}\n" 103 "ldr pc, [sp], #4\n" 104 ); 105 #else // Not an ARM host 106 void ARMCompilationCallback() { 107 llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!"); 108 } 109 #endif 110 } 111 112 /// ARMCompilationCallbackC - This is the target-specific function invoked 113 /// by the function stub when we did not know the real target of a call. 114 /// This function must locate the start of the stub or call site and pass 115 /// it into the JIT compiler function. 116 extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { 117 // Get the address of the compiled code for this function. 118 intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)StubAddr); 119 120 // Rewrite the call target... so that we don't end up here every time we 121 // execute the call. We're replacing the first two instructions of the 122 // stub with: 123 // ldr pc, [pc,#-4] 124 // <addr> 125 if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { 126 llvm_unreachable("ERROR: Unable to mark stub writable"); 127 } 128 *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] 129 *(intptr_t *)(StubAddr+4) = NewVal; 130 if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { 131 llvm_unreachable("ERROR: Unable to mark stub executable"); 132 } 133 } 134 135 TargetJITInfo::LazyResolverFn 136 ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) { 137 JITCompilerFunction = F; 138 return ARMCompilationCallback; 139 } 140 141 void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr, 142 JITCodeEmitter &JCE) { 143 uint8_t Buffer[4]; 144 uint8_t *Cur = Buffer; 145 MachineCodeEmitter::emitWordLEInto(Cur, (intptr_t)Ptr); 146 void *PtrAddr = JCE.allocIndirectGV( 147 GV, Buffer, sizeof(Buffer), /*Alignment=*/4); 148 addIndirectSymAddr(Ptr, (intptr_t)PtrAddr); 149 return PtrAddr; 150 } 151 152 TargetJITInfo::StubLayout ARMJITInfo::getStubLayout() { 153 // The stub contains up to 3 4-byte instructions, aligned at 4 bytes, and a 154 // 4-byte address. See emitFunctionStub for details. 155 StubLayout Result = {16, 4}; 156 return Result; 157 } 158 159 void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn, 160 JITCodeEmitter &JCE) { 161 void *Addr; 162 // If this is just a call to an external function, emit a branch instead of a 163 // call. The code is the same except for one bit of the last instruction. 164 if (Fn != (void*)(intptr_t)ARMCompilationCallback) { 165 // Branch to the corresponding function addr. 166 if (IsPIC) { 167 // The stub is 16-byte size and 4-aligned. 168 intptr_t LazyPtr = getIndirectSymAddr(Fn); 169 if (!LazyPtr) { 170 // In PIC mode, the function stub is loading a lazy-ptr. 171 LazyPtr= (intptr_t)emitGlobalValueIndirectSym((GlobalValue*)F, Fn, JCE); 172 DEBUG(if (F) 173 errs() << "JIT: Indirect symbol emitted at [" << LazyPtr 174 << "] for GV '" << F->getName() << "'\n"; 175 else 176 errs() << "JIT: Stub emitted at [" << LazyPtr 177 << "] for external function at '" << Fn << "'\n"); 178 } 179 JCE.emitAlignment(4); 180 Addr = (void*)JCE.getCurrentPCValue(); 181 if (!sys::Memory::setRangeWritable(Addr, 16)) { 182 llvm_unreachable("ERROR: Unable to mark stub writable"); 183 } 184 JCE.emitWordLE(0xe59fc004); // ldr ip, [pc, #+4] 185 JCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip 186 JCE.emitWordLE(0xe59cf000); // ldr pc, [ip] 187 JCE.emitWordLE(LazyPtr - (intptr_t(Addr)+4+8)); // func - (L_func$scv+8) 188 sys::Memory::InvalidateInstructionCache(Addr, 16); 189 if (!sys::Memory::setRangeExecutable(Addr, 16)) { 190 llvm_unreachable("ERROR: Unable to mark stub executable"); 191 } 192 } else { 193 // The stub is 8-byte size and 4-aligned. 194 JCE.emitAlignment(4); 195 Addr = (void*)JCE.getCurrentPCValue(); 196 if (!sys::Memory::setRangeWritable(Addr, 8)) { 197 llvm_unreachable("ERROR: Unable to mark stub writable"); 198 } 199 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4] 200 JCE.emitWordLE((intptr_t)Fn); // addr of function 201 sys::Memory::InvalidateInstructionCache(Addr, 8); 202 if (!sys::Memory::setRangeExecutable(Addr, 8)) { 203 llvm_unreachable("ERROR: Unable to mark stub executable"); 204 } 205 } 206 } else { 207 // The compilation callback will overwrite the first two words of this 208 // stub with indirect branch instructions targeting the compiled code. 209 // This stub sets the return address to restart the stub, so that 210 // the new branch will be invoked when we come back. 211 // 212 // Branch and link to the compilation callback. 213 // The stub is 16-byte size and 4-byte aligned. 214 JCE.emitAlignment(4); 215 Addr = (void*)JCE.getCurrentPCValue(); 216 if (!sys::Memory::setRangeWritable(Addr, 16)) { 217 llvm_unreachable("ERROR: Unable to mark stub writable"); 218 } 219 // Save LR so the callback can determine which stub called it. 220 // The compilation callback is responsible for popping this prior 221 // to returning. 222 JCE.emitWordLE(0xe92d4000); // push {lr} 223 // Set the return address to go back to the start of this stub. 224 JCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12 225 // Invoke the compilation callback. 226 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4] 227 // The address of the compilation callback. 228 JCE.emitWordLE((intptr_t)ARMCompilationCallback); 229 sys::Memory::InvalidateInstructionCache(Addr, 16); 230 if (!sys::Memory::setRangeExecutable(Addr, 16)) { 231 llvm_unreachable("ERROR: Unable to mark stub executable"); 232 } 233 } 234 235 return Addr; 236 } 237 238 intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const { 239 ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType(); 240 switch (RT) { 241 default: 242 return (intptr_t)(MR->getResultPointer()); 243 case ARM::reloc_arm_pic_jt: 244 // Destination address - jump table base. 245 return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal(); 246 case ARM::reloc_arm_jt_base: 247 // Jump table base address. 248 return getJumpTableBaseAddr(MR->getJumpTableIndex()); 249 case ARM::reloc_arm_cp_entry: 250 case ARM::reloc_arm_vfp_cp_entry: 251 // Constant pool entry address. 252 return getConstantPoolEntryAddr(MR->getConstantPoolIndex()); 253 case ARM::reloc_arm_machine_cp_entry: { 254 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal(); 255 assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) && 256 "Can't handle this machine constant pool entry yet!"); 257 intptr_t Addr = (intptr_t)(MR->getResultPointer()); 258 Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment(); 259 return Addr; 260 } 261 } 262 } 263 264 /// relocate - Before the JIT can run a block of code that has been emitted, 265 /// it must rewrite the code to contain the actual addresses of any 266 /// referenced global symbols. 267 void ARMJITInfo::relocate(void *Function, MachineRelocation *MR, 268 unsigned NumRelocs, unsigned char* GOTBase) { 269 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { 270 void *RelocPos = (char*)Function + MR->getMachineCodeOffset(); 271 intptr_t ResultPtr = resolveRelocDestAddr(MR); 272 switch ((ARM::RelocationType)MR->getRelocationType()) { 273 case ARM::reloc_arm_cp_entry: 274 case ARM::reloc_arm_vfp_cp_entry: 275 case ARM::reloc_arm_relative: { 276 // It is necessary to calculate the correct PC relative value. We 277 // subtract the base addr from the target addr to form a byte offset. 278 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; 279 // If the result is positive, set bit U(23) to 1. 280 if (ResultPtr >= 0) 281 *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift; 282 else { 283 // Otherwise, obtain the absolute value and set bit U(23) to 0. 284 *((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift); 285 ResultPtr = - ResultPtr; 286 } 287 // Set the immed value calculated. 288 // VFP immediate offset is multiplied by 4. 289 if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry) 290 ResultPtr = ResultPtr >> 2; 291 *((intptr_t*)RelocPos) |= ResultPtr; 292 // Set register Rn to PC. 293 *((intptr_t*)RelocPos) |= 294 getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 295 break; 296 } 297 case ARM::reloc_arm_pic_jt: 298 case ARM::reloc_arm_machine_cp_entry: 299 case ARM::reloc_arm_absolute: { 300 // These addresses have already been resolved. 301 *((intptr_t*)RelocPos) |= (intptr_t)ResultPtr; 302 break; 303 } 304 case ARM::reloc_arm_branch: { 305 // It is necessary to calculate the correct value of signed_immed_24 306 // field. We subtract the base addr from the target addr to form a 307 // byte offset, which must be inside the range -33554432 and +33554428. 308 // Then, we set the signed_immed_24 field of the instruction to bits 309 // [25:2] of the byte offset. More details ARM-ARM p. A4-11. 310 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; 311 ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2; 312 assert(ResultPtr >= -33554432 && ResultPtr <= 33554428); 313 *((intptr_t*)RelocPos) |= ResultPtr; 314 break; 315 } 316 case ARM::reloc_arm_jt_base: { 317 // JT base - (instruction addr + 8) 318 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; 319 *((intptr_t*)RelocPos) |= ResultPtr; 320 break; 321 } 322 case ARM::reloc_arm_movw: { 323 ResultPtr = ResultPtr & 0xFFFF; 324 *((intptr_t*)RelocPos) |= ResultPtr & 0xFFF; 325 *((intptr_t*)RelocPos) |= ((ResultPtr >> 12) & 0xF) << 16; 326 break; 327 } 328 case ARM::reloc_arm_movt: { 329 ResultPtr = (ResultPtr >> 16) & 0xFFFF; 330 *((intptr_t*)RelocPos) |= ResultPtr & 0xFFF; 331 *((intptr_t*)RelocPos) |= ((ResultPtr >> 12) & 0xF) << 16; 332 break; 333 } 334 } 335 } 336 } 337
