1 //===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 class SPUReg<string n> : Register<n> { 14 let Namespace = "SPU"; 15 } 16 17 // The SPU's register are all 128-bits wide, which makes specifying the 18 // registers relatively easy, if relatively mundane: 19 20 class SPUVecReg<bits<7> num, string n> : SPUReg<n> { 21 field bits<7> Num = num; 22 } 23 24 def R0 : SPUVecReg<0, "$lr">, DwarfRegNum<[0]>; 25 def R1 : SPUVecReg<1, "$sp">, DwarfRegNum<[1]>; 26 def R2 : SPUVecReg<2, "$2">, DwarfRegNum<[2]>; 27 def R3 : SPUVecReg<3, "$3">, DwarfRegNum<[3]>; 28 def R4 : SPUVecReg<4, "$4">, DwarfRegNum<[4]>; 29 def R5 : SPUVecReg<5, "$5">, DwarfRegNum<[5]>; 30 def R6 : SPUVecReg<6, "$6">, DwarfRegNum<[6]>; 31 def R7 : SPUVecReg<7, "$7">, DwarfRegNum<[7]>; 32 def R8 : SPUVecReg<8, "$8">, DwarfRegNum<[8]>; 33 def R9 : SPUVecReg<9, "$9">, DwarfRegNum<[9]>; 34 def R10 : SPUVecReg<10, "$10">, DwarfRegNum<[10]>; 35 def R11 : SPUVecReg<11, "$11">, DwarfRegNum<[11]>; 36 def R12 : SPUVecReg<12, "$12">, DwarfRegNum<[12]>; 37 def R13 : SPUVecReg<13, "$13">, DwarfRegNum<[13]>; 38 def R14 : SPUVecReg<14, "$14">, DwarfRegNum<[14]>; 39 def R15 : SPUVecReg<15, "$15">, DwarfRegNum<[15]>; 40 def R16 : SPUVecReg<16, "$16">, DwarfRegNum<[16]>; 41 def R17 : SPUVecReg<17, "$17">, DwarfRegNum<[17]>; 42 def R18 : SPUVecReg<18, "$18">, DwarfRegNum<[18]>; 43 def R19 : SPUVecReg<19, "$19">, DwarfRegNum<[19]>; 44 def R20 : SPUVecReg<20, "$20">, DwarfRegNum<[20]>; 45 def R21 : SPUVecReg<21, "$21">, DwarfRegNum<[21]>; 46 def R22 : SPUVecReg<22, "$22">, DwarfRegNum<[22]>; 47 def R23 : SPUVecReg<23, "$23">, DwarfRegNum<[23]>; 48 def R24 : SPUVecReg<24, "$24">, DwarfRegNum<[24]>; 49 def R25 : SPUVecReg<25, "$25">, DwarfRegNum<[25]>; 50 def R26 : SPUVecReg<26, "$26">, DwarfRegNum<[26]>; 51 def R27 : SPUVecReg<27, "$27">, DwarfRegNum<[27]>; 52 def R28 : SPUVecReg<28, "$28">, DwarfRegNum<[28]>; 53 def R29 : SPUVecReg<29, "$29">, DwarfRegNum<[29]>; 54 def R30 : SPUVecReg<30, "$30">, DwarfRegNum<[30]>; 55 def R31 : SPUVecReg<31, "$31">, DwarfRegNum<[31]>; 56 def R32 : SPUVecReg<32, "$32">, DwarfRegNum<[32]>; 57 def R33 : SPUVecReg<33, "$33">, DwarfRegNum<[33]>; 58 def R34 : SPUVecReg<34, "$34">, DwarfRegNum<[34]>; 59 def R35 : SPUVecReg<35, "$35">, DwarfRegNum<[35]>; 60 def R36 : SPUVecReg<36, "$36">, DwarfRegNum<[36]>; 61 def R37 : SPUVecReg<37, "$37">, DwarfRegNum<[37]>; 62 def R38 : SPUVecReg<38, "$38">, DwarfRegNum<[38]>; 63 def R39 : SPUVecReg<39, "$39">, DwarfRegNum<[39]>; 64 def R40 : SPUVecReg<40, "$40">, DwarfRegNum<[40]>; 65 def R41 : SPUVecReg<41, "$41">, DwarfRegNum<[41]>; 66 def R42 : SPUVecReg<42, "$42">, DwarfRegNum<[42]>; 67 def R43 : SPUVecReg<43, "$43">, DwarfRegNum<[43]>; 68 def R44 : SPUVecReg<44, "$44">, DwarfRegNum<[44]>; 69 def R45 : SPUVecReg<45, "$45">, DwarfRegNum<[45]>; 70 def R46 : SPUVecReg<46, "$46">, DwarfRegNum<[46]>; 71 def R47 : SPUVecReg<47, "$47">, DwarfRegNum<[47]>; 72 def R48 : SPUVecReg<48, "$48">, DwarfRegNum<[48]>; 73 def R49 : SPUVecReg<49, "$49">, DwarfRegNum<[49]>; 74 def R50 : SPUVecReg<50, "$50">, DwarfRegNum<[50]>; 75 def R51 : SPUVecReg<51, "$51">, DwarfRegNum<[51]>; 76 def R52 : SPUVecReg<52, "$52">, DwarfRegNum<[52]>; 77 def R53 : SPUVecReg<53, "$53">, DwarfRegNum<[53]>; 78 def R54 : SPUVecReg<54, "$54">, DwarfRegNum<[54]>; 79 def R55 : SPUVecReg<55, "$55">, DwarfRegNum<[55]>; 80 def R56 : SPUVecReg<56, "$56">, DwarfRegNum<[56]>; 81 def R57 : SPUVecReg<57, "$57">, DwarfRegNum<[57]>; 82 def R58 : SPUVecReg<58, "$58">, DwarfRegNum<[58]>; 83 def R59 : SPUVecReg<59, "$59">, DwarfRegNum<[59]>; 84 def R60 : SPUVecReg<60, "$60">, DwarfRegNum<[60]>; 85 def R61 : SPUVecReg<61, "$61">, DwarfRegNum<[61]>; 86 def R62 : SPUVecReg<62, "$62">, DwarfRegNum<[62]>; 87 def R63 : SPUVecReg<63, "$63">, DwarfRegNum<[63]>; 88 def R64 : SPUVecReg<64, "$64">, DwarfRegNum<[64]>; 89 def R65 : SPUVecReg<65, "$65">, DwarfRegNum<[65]>; 90 def R66 : SPUVecReg<66, "$66">, DwarfRegNum<[66]>; 91 def R67 : SPUVecReg<67, "$67">, DwarfRegNum<[67]>; 92 def R68 : SPUVecReg<68, "$68">, DwarfRegNum<[68]>; 93 def R69 : SPUVecReg<69, "$69">, DwarfRegNum<[69]>; 94 def R70 : SPUVecReg<70, "$70">, DwarfRegNum<[70]>; 95 def R71 : SPUVecReg<71, "$71">, DwarfRegNum<[71]>; 96 def R72 : SPUVecReg<72, "$72">, DwarfRegNum<[72]>; 97 def R73 : SPUVecReg<73, "$73">, DwarfRegNum<[73]>; 98 def R74 : SPUVecReg<74, "$74">, DwarfRegNum<[74]>; 99 def R75 : SPUVecReg<75, "$75">, DwarfRegNum<[75]>; 100 def R76 : SPUVecReg<76, "$76">, DwarfRegNum<[76]>; 101 def R77 : SPUVecReg<77, "$77">, DwarfRegNum<[77]>; 102 def R78 : SPUVecReg<78, "$78">, DwarfRegNum<[78]>; 103 def R79 : SPUVecReg<79, "$79">, DwarfRegNum<[79]>; 104 def R80 : SPUVecReg<80, "$80">, DwarfRegNum<[80]>; 105 def R81 : SPUVecReg<81, "$81">, DwarfRegNum<[81]>; 106 def R82 : SPUVecReg<82, "$82">, DwarfRegNum<[82]>; 107 def R83 : SPUVecReg<83, "$83">, DwarfRegNum<[83]>; 108 def R84 : SPUVecReg<84, "$84">, DwarfRegNum<[84]>; 109 def R85 : SPUVecReg<85, "$85">, DwarfRegNum<[85]>; 110 def R86 : SPUVecReg<86, "$86">, DwarfRegNum<[86]>; 111 def R87 : SPUVecReg<87, "$87">, DwarfRegNum<[87]>; 112 def R88 : SPUVecReg<88, "$88">, DwarfRegNum<[88]>; 113 def R89 : SPUVecReg<89, "$89">, DwarfRegNum<[89]>; 114 def R90 : SPUVecReg<90, "$90">, DwarfRegNum<[90]>; 115 def R91 : SPUVecReg<91, "$91">, DwarfRegNum<[91]>; 116 def R92 : SPUVecReg<92, "$92">, DwarfRegNum<[92]>; 117 def R93 : SPUVecReg<93, "$93">, DwarfRegNum<[93]>; 118 def R94 : SPUVecReg<94, "$94">, DwarfRegNum<[94]>; 119 def R95 : SPUVecReg<95, "$95">, DwarfRegNum<[95]>; 120 def R96 : SPUVecReg<96, "$96">, DwarfRegNum<[96]>; 121 def R97 : SPUVecReg<97, "$97">, DwarfRegNum<[97]>; 122 def R98 : SPUVecReg<98, "$98">, DwarfRegNum<[98]>; 123 def R99 : SPUVecReg<99, "$99">, DwarfRegNum<[99]>; 124 def R100 : SPUVecReg<100, "$100">, DwarfRegNum<[100]>; 125 def R101 : SPUVecReg<101, "$101">, DwarfRegNum<[101]>; 126 def R102 : SPUVecReg<102, "$102">, DwarfRegNum<[102]>; 127 def R103 : SPUVecReg<103, "$103">, DwarfRegNum<[103]>; 128 def R104 : SPUVecReg<104, "$104">, DwarfRegNum<[104]>; 129 def R105 : SPUVecReg<105, "$105">, DwarfRegNum<[105]>; 130 def R106 : SPUVecReg<106, "$106">, DwarfRegNum<[106]>; 131 def R107 : SPUVecReg<107, "$107">, DwarfRegNum<[107]>; 132 def R108 : SPUVecReg<108, "$108">, DwarfRegNum<[108]>; 133 def R109 : SPUVecReg<109, "$109">, DwarfRegNum<[109]>; 134 def R110 : SPUVecReg<110, "$110">, DwarfRegNum<[110]>; 135 def R111 : SPUVecReg<111, "$111">, DwarfRegNum<[111]>; 136 def R112 : SPUVecReg<112, "$112">, DwarfRegNum<[112]>; 137 def R113 : SPUVecReg<113, "$113">, DwarfRegNum<[113]>; 138 def R114 : SPUVecReg<114, "$114">, DwarfRegNum<[114]>; 139 def R115 : SPUVecReg<115, "$115">, DwarfRegNum<[115]>; 140 def R116 : SPUVecReg<116, "$116">, DwarfRegNum<[116]>; 141 def R117 : SPUVecReg<117, "$117">, DwarfRegNum<[117]>; 142 def R118 : SPUVecReg<118, "$118">, DwarfRegNum<[118]>; 143 def R119 : SPUVecReg<119, "$119">, DwarfRegNum<[119]>; 144 def R120 : SPUVecReg<120, "$120">, DwarfRegNum<[120]>; 145 def R121 : SPUVecReg<121, "$121">, DwarfRegNum<[121]>; 146 def R122 : SPUVecReg<122, "$122">, DwarfRegNum<[122]>; 147 def R123 : SPUVecReg<123, "$123">, DwarfRegNum<[123]>; 148 def R124 : SPUVecReg<124, "$124">, DwarfRegNum<[124]>; 149 def R125 : SPUVecReg<125, "$125">, DwarfRegNum<[125]>; 150 def R126 : SPUVecReg<126, "$126">, DwarfRegNum<[126]>; 151 def R127 : SPUVecReg<127, "$127">, DwarfRegNum<[127]>; 152 153 /* Need floating point status register here: */ 154 /* def FPCSR : ... */ 155 156 // The SPU's registers as 128-bit wide entities, and can function as general 157 // purpose registers, where the operands are in the "preferred slot": 158 // The non-volatile registers are allocated in reverse order, like PPC does it. 159 def GPRC : RegisterClass<"SPU", [i128], 128, 160 (add (sequence "R%u", 0, 79), 161 (sequence "R%u", 127, 80))>; 162 163 // The SPU's registers as 64-bit wide (double word integer) "preferred slot": 164 def R64C : RegisterClass<"SPU", [i64], 128, (add GPRC)>; 165 166 // The SPU's registers as 64-bit wide (double word) FP "preferred slot": 167 def R64FP : RegisterClass<"SPU", [f64], 128, (add GPRC)>; 168 169 // The SPU's registers as 32-bit wide (word) "preferred slot": 170 def R32C : RegisterClass<"SPU", [i32], 128, (add GPRC)>; 171 172 // The SPU's registers as single precision floating point "preferred slot": 173 def R32FP : RegisterClass<"SPU", [f32], 128, (add GPRC)>; 174 175 // The SPU's registers as 16-bit wide (halfword) "preferred slot": 176 def R16C : RegisterClass<"SPU", [i16], 128, (add GPRC)>; 177 178 // The SPU's registers as 8-bit wide (byte) "preferred slot": 179 def R8C : RegisterClass<"SPU", [i8], 128, (add GPRC)>; 180 181 // The SPU's registers as vector registers: 182 def VECREG : RegisterClass<"SPU", [v16i8,v8i16,v4i32,v4f32,v2i64,v2f64], 128, 183 (add GPRC)>; 184
