1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains logic for simplifying instructions based on information 11 // about how they are used. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #include "InstCombine.h" 17 #include "llvm/Target/TargetData.h" 18 #include "llvm/IntrinsicInst.h" 19 20 using namespace llvm; 21 22 23 /// ShrinkDemandedConstant - Check to see if the specified operand of the 24 /// specified instruction is a constant integer. If so, check to see if there 25 /// are any bits set in the constant that are not demanded. If so, shrink the 26 /// constant and return true. 27 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, 28 APInt Demanded) { 29 assert(I && "No instruction?"); 30 assert(OpNo < I->getNumOperands() && "Operand index too large"); 31 32 // If the operand is not a constant integer, nothing to do. 33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo)); 34 if (!OpC) return false; 35 36 // If there are no bits set that aren't demanded, nothing to do. 37 Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth()); 38 if ((~Demanded & OpC->getValue()) == 0) 39 return false; 40 41 // This instruction is producing bits that are not demanded. Shrink the RHS. 42 Demanded &= OpC->getValue(); 43 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded)); 44 return true; 45 } 46 47 48 49 /// SimplifyDemandedInstructionBits - Inst is an integer instruction that 50 /// SimplifyDemandedBits knows about. See if the instruction has any 51 /// properties that allow us to simplify its operands. 52 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) { 53 unsigned BitWidth = Inst.getType()->getScalarSizeInBits(); 54 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); 55 APInt DemandedMask(APInt::getAllOnesValue(BitWidth)); 56 57 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, 58 KnownZero, KnownOne, 0); 59 if (V == 0) return false; 60 if (V == &Inst) return true; 61 ReplaceInstUsesWith(Inst, V); 62 return true; 63 } 64 65 /// SimplifyDemandedBits - This form of SimplifyDemandedBits simplifies the 66 /// specified instruction operand if possible, updating it in place. It returns 67 /// true if it made any change and false otherwise. 68 bool InstCombiner::SimplifyDemandedBits(Use &U, APInt DemandedMask, 69 APInt &KnownZero, APInt &KnownOne, 70 unsigned Depth) { 71 Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, 72 KnownZero, KnownOne, Depth); 73 if (NewVal == 0) return false; 74 U = NewVal; 75 return true; 76 } 77 78 79 /// SimplifyDemandedUseBits - This function attempts to replace V with a simpler 80 /// value based on the demanded bits. When this function is called, it is known 81 /// that only the bits set in DemandedMask of the result of V are ever used 82 /// downstream. Consequently, depending on the mask and V, it may be possible 83 /// to replace V with a constant or one of its operands. In such cases, this 84 /// function does the replacement and returns true. In all other cases, it 85 /// returns false after analyzing the expression and setting KnownOne and known 86 /// to be one in the expression. KnownZero contains all the bits that are known 87 /// to be zero in the expression. These are provided to potentially allow the 88 /// caller (which might recursively be SimplifyDemandedBits itself) to simplify 89 /// the expression. KnownOne and KnownZero always follow the invariant that 90 /// KnownOne & KnownZero == 0. That is, a bit can't be both 1 and 0. Note that 91 /// the bits in KnownOne and KnownZero may only be accurate for those bits set 92 /// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero 93 /// and KnownOne must all be the same. 94 /// 95 /// This returns null if it did not change anything and it permits no 96 /// simplification. This returns V itself if it did some simplification of V's 97 /// operands based on the information about what bits are demanded. This returns 98 /// some other non-null value if it found out that V is equal to another value 99 /// in the context where the specified bits are demanded, but not for all users. 100 Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, 101 APInt &KnownZero, APInt &KnownOne, 102 unsigned Depth) { 103 assert(V != 0 && "Null pointer of Value???"); 104 assert(Depth <= 6 && "Limit Search Depth"); 105 uint32_t BitWidth = DemandedMask.getBitWidth(); 106 Type *VTy = V->getType(); 107 assert((TD || !VTy->isPointerTy()) && 108 "SimplifyDemandedBits needs to know bit widths!"); 109 assert((!TD || TD->getTypeSizeInBits(VTy->getScalarType()) == BitWidth) && 110 (!VTy->isIntOrIntVectorTy() || 111 VTy->getScalarSizeInBits() == BitWidth) && 112 KnownZero.getBitWidth() == BitWidth && 113 KnownOne.getBitWidth() == BitWidth && 114 "Value *V, DemandedMask, KnownZero and KnownOne " 115 "must have same BitWidth"); 116 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 117 // We know all of the bits for a constant! 118 KnownOne = CI->getValue() & DemandedMask; 119 KnownZero = ~KnownOne & DemandedMask; 120 return 0; 121 } 122 if (isa<ConstantPointerNull>(V)) { 123 // We know all of the bits for a constant! 124 KnownOne.clearAllBits(); 125 KnownZero = DemandedMask; 126 return 0; 127 } 128 129 KnownZero.clearAllBits(); 130 KnownOne.clearAllBits(); 131 if (DemandedMask == 0) { // Not demanding any bits from V. 132 if (isa<UndefValue>(V)) 133 return 0; 134 return UndefValue::get(VTy); 135 } 136 137 if (Depth == 6) // Limit search depth. 138 return 0; 139 140 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); 141 APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0); 142 143 Instruction *I = dyn_cast<Instruction>(V); 144 if (!I) { 145 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); 146 return 0; // Only analyze instructions. 147 } 148 149 // If there are multiple uses of this value and we aren't at the root, then 150 // we can't do any simplifications of the operands, because DemandedMask 151 // only reflects the bits demanded by *one* of the users. 152 if (Depth != 0 && !I->hasOneUse()) { 153 // Despite the fact that we can't simplify this instruction in all User's 154 // context, we can at least compute the knownzero/knownone bits, and we can 155 // do simplifications that apply to *just* the one user if we know that 156 // this instruction has a simpler value in that context. 157 if (I->getOpcode() == Instruction::And) { 158 // If either the LHS or the RHS are Zero, the result is zero. 159 ComputeMaskedBits(I->getOperand(1), DemandedMask, 160 RHSKnownZero, RHSKnownOne, Depth+1); 161 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero, 162 LHSKnownZero, LHSKnownOne, Depth+1); 163 164 // If all of the demanded bits are known 1 on one side, return the other. 165 // These bits cannot contribute to the result of the 'and' in this 166 // context. 167 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == 168 (DemandedMask & ~LHSKnownZero)) 169 return I->getOperand(0); 170 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) == 171 (DemandedMask & ~RHSKnownZero)) 172 return I->getOperand(1); 173 174 // If all of the demanded bits in the inputs are known zeros, return zero. 175 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) 176 return Constant::getNullValue(VTy); 177 178 } else if (I->getOpcode() == Instruction::Or) { 179 // We can simplify (X|Y) -> X or Y in the user's context if we know that 180 // only bits from X or Y are demanded. 181 182 // If either the LHS or the RHS are One, the result is One. 183 ComputeMaskedBits(I->getOperand(1), DemandedMask, 184 RHSKnownZero, RHSKnownOne, Depth+1); 185 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne, 186 LHSKnownZero, LHSKnownOne, Depth+1); 187 188 // If all of the demanded bits are known zero on one side, return the 189 // other. These bits cannot contribute to the result of the 'or' in this 190 // context. 191 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) == 192 (DemandedMask & ~LHSKnownOne)) 193 return I->getOperand(0); 194 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == 195 (DemandedMask & ~RHSKnownOne)) 196 return I->getOperand(1); 197 198 // If all of the potentially set bits on one side are known to be set on 199 // the other side, just use the 'other' side. 200 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) == 201 (DemandedMask & (~RHSKnownZero))) 202 return I->getOperand(0); 203 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == 204 (DemandedMask & (~LHSKnownZero))) 205 return I->getOperand(1); 206 } 207 208 // Compute the KnownZero/KnownOne bits to simplify things downstream. 209 ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth); 210 return 0; 211 } 212 213 // If this is the root being simplified, allow it to have multiple uses, 214 // just set the DemandedMask to all bits so that we can try to simplify the 215 // operands. This allows visitTruncInst (for example) to simplify the 216 // operand of a trunc without duplicating all the logic below. 217 if (Depth == 0 && !V->hasOneUse()) 218 DemandedMask = APInt::getAllOnesValue(BitWidth); 219 220 switch (I->getOpcode()) { 221 default: 222 ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth); 223 break; 224 case Instruction::And: 225 // If either the LHS or the RHS are Zero, the result is zero. 226 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 227 RHSKnownZero, RHSKnownOne, Depth+1) || 228 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownZero, 229 LHSKnownZero, LHSKnownOne, Depth+1)) 230 return I; 231 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 232 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 233 234 // If all of the demanded bits are known 1 on one side, return the other. 235 // These bits cannot contribute to the result of the 'and'. 236 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == 237 (DemandedMask & ~LHSKnownZero)) 238 return I->getOperand(0); 239 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) == 240 (DemandedMask & ~RHSKnownZero)) 241 return I->getOperand(1); 242 243 // If all of the demanded bits in the inputs are known zeros, return zero. 244 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) 245 return Constant::getNullValue(VTy); 246 247 // If the RHS is a constant, see if we can simplify it. 248 if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero)) 249 return I; 250 251 // Output known-1 bits are only known if set in both the LHS & RHS. 252 KnownOne = RHSKnownOne & LHSKnownOne; 253 // Output known-0 are known to be clear if zero in either the LHS | RHS. 254 KnownZero = RHSKnownZero | LHSKnownZero; 255 break; 256 case Instruction::Or: 257 // If either the LHS or the RHS are One, the result is One. 258 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 259 RHSKnownZero, RHSKnownOne, Depth+1) || 260 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownOne, 261 LHSKnownZero, LHSKnownOne, Depth+1)) 262 return I; 263 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 264 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 265 266 // If all of the demanded bits are known zero on one side, return the other. 267 // These bits cannot contribute to the result of the 'or'. 268 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) == 269 (DemandedMask & ~LHSKnownOne)) 270 return I->getOperand(0); 271 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == 272 (DemandedMask & ~RHSKnownOne)) 273 return I->getOperand(1); 274 275 // If all of the potentially set bits on one side are known to be set on 276 // the other side, just use the 'other' side. 277 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) == 278 (DemandedMask & (~RHSKnownZero))) 279 return I->getOperand(0); 280 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == 281 (DemandedMask & (~LHSKnownZero))) 282 return I->getOperand(1); 283 284 // If the RHS is a constant, see if we can simplify it. 285 if (ShrinkDemandedConstant(I, 1, DemandedMask)) 286 return I; 287 288 // Output known-0 bits are only known if clear in both the LHS & RHS. 289 KnownZero = RHSKnownZero & LHSKnownZero; 290 // Output known-1 are known to be set if set in either the LHS | RHS. 291 KnownOne = RHSKnownOne | LHSKnownOne; 292 break; 293 case Instruction::Xor: { 294 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 295 RHSKnownZero, RHSKnownOne, Depth+1) || 296 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 297 LHSKnownZero, LHSKnownOne, Depth+1)) 298 return I; 299 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 300 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 301 302 // If all of the demanded bits are known zero on one side, return the other. 303 // These bits cannot contribute to the result of the 'xor'. 304 if ((DemandedMask & RHSKnownZero) == DemandedMask) 305 return I->getOperand(0); 306 if ((DemandedMask & LHSKnownZero) == DemandedMask) 307 return I->getOperand(1); 308 309 // If all of the demanded bits are known to be zero on one side or the 310 // other, turn this into an *inclusive* or. 311 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 312 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) { 313 Instruction *Or = 314 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), 315 I->getName()); 316 return InsertNewInstWith(Or, *I); 317 } 318 319 // If all of the demanded bits on one side are known, and all of the set 320 // bits on that side are also known to be set on the other side, turn this 321 // into an AND, as we know the bits will be cleared. 322 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 323 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) { 324 // all known 325 if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) { 326 Constant *AndC = Constant::getIntegerValue(VTy, 327 ~RHSKnownOne & DemandedMask); 328 Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC); 329 return InsertNewInstWith(And, *I); 330 } 331 } 332 333 // If the RHS is a constant, see if we can simplify it. 334 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 335 if (ShrinkDemandedConstant(I, 1, DemandedMask)) 336 return I; 337 338 // If our LHS is an 'and' and if it has one use, and if any of the bits we 339 // are flipping are known to be set, then the xor is just resetting those 340 // bits to zero. We can just knock out bits from the 'and' and the 'xor', 341 // simplifying both of them. 342 if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0))) 343 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() && 344 isa<ConstantInt>(I->getOperand(1)) && 345 isa<ConstantInt>(LHSInst->getOperand(1)) && 346 (LHSKnownOne & RHSKnownOne & DemandedMask) != 0) { 347 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1)); 348 ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1)); 349 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask); 350 351 Constant *AndC = 352 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue()); 353 Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC); 354 InsertNewInstWith(NewAnd, *I); 355 356 Constant *XorC = 357 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue()); 358 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC); 359 return InsertNewInstWith(NewXor, *I); 360 } 361 362 // Output known-0 bits are known if clear or set in both the LHS & RHS. 363 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne); 364 // Output known-1 are known to be set if set in only one of the LHS, RHS. 365 KnownOne = (RHSKnownZero & LHSKnownOne) | (RHSKnownOne & LHSKnownZero); 366 break; 367 } 368 case Instruction::Select: 369 if (SimplifyDemandedBits(I->getOperandUse(2), DemandedMask, 370 RHSKnownZero, RHSKnownOne, Depth+1) || 371 SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 372 LHSKnownZero, LHSKnownOne, Depth+1)) 373 return I; 374 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 375 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 376 377 // If the operands are constants, see if we can simplify them. 378 if (ShrinkDemandedConstant(I, 1, DemandedMask) || 379 ShrinkDemandedConstant(I, 2, DemandedMask)) 380 return I; 381 382 // Only known if known in both the LHS and RHS. 383 KnownOne = RHSKnownOne & LHSKnownOne; 384 KnownZero = RHSKnownZero & LHSKnownZero; 385 break; 386 case Instruction::Trunc: { 387 unsigned truncBf = I->getOperand(0)->getType()->getScalarSizeInBits(); 388 DemandedMask = DemandedMask.zext(truncBf); 389 KnownZero = KnownZero.zext(truncBf); 390 KnownOne = KnownOne.zext(truncBf); 391 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 392 KnownZero, KnownOne, Depth+1)) 393 return I; 394 DemandedMask = DemandedMask.trunc(BitWidth); 395 KnownZero = KnownZero.trunc(BitWidth); 396 KnownOne = KnownOne.trunc(BitWidth); 397 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 398 break; 399 } 400 case Instruction::BitCast: 401 if (!I->getOperand(0)->getType()->isIntOrIntVectorTy()) 402 return 0; // vector->int or fp->int? 403 404 if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) { 405 if (VectorType *SrcVTy = 406 dyn_cast<VectorType>(I->getOperand(0)->getType())) { 407 if (DstVTy->getNumElements() != SrcVTy->getNumElements()) 408 // Don't touch a bitcast between vectors of different element counts. 409 return 0; 410 } else 411 // Don't touch a scalar-to-vector bitcast. 412 return 0; 413 } else if (I->getOperand(0)->getType()->isVectorTy()) 414 // Don't touch a vector-to-scalar bitcast. 415 return 0; 416 417 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 418 KnownZero, KnownOne, Depth+1)) 419 return I; 420 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 421 break; 422 case Instruction::ZExt: { 423 // Compute the bits in the result that are not present in the input. 424 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits(); 425 426 DemandedMask = DemandedMask.trunc(SrcBitWidth); 427 KnownZero = KnownZero.trunc(SrcBitWidth); 428 KnownOne = KnownOne.trunc(SrcBitWidth); 429 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 430 KnownZero, KnownOne, Depth+1)) 431 return I; 432 DemandedMask = DemandedMask.zext(BitWidth); 433 KnownZero = KnownZero.zext(BitWidth); 434 KnownOne = KnownOne.zext(BitWidth); 435 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 436 // The top bits are known to be zero. 437 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth); 438 break; 439 } 440 case Instruction::SExt: { 441 // Compute the bits in the result that are not present in the input. 442 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits(); 443 444 APInt InputDemandedBits = DemandedMask & 445 APInt::getLowBitsSet(BitWidth, SrcBitWidth); 446 447 APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth)); 448 // If any of the sign extended bits are demanded, we know that the sign 449 // bit is demanded. 450 if ((NewBits & DemandedMask) != 0) 451 InputDemandedBits.setBit(SrcBitWidth-1); 452 453 InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth); 454 KnownZero = KnownZero.trunc(SrcBitWidth); 455 KnownOne = KnownOne.trunc(SrcBitWidth); 456 if (SimplifyDemandedBits(I->getOperandUse(0), InputDemandedBits, 457 KnownZero, KnownOne, Depth+1)) 458 return I; 459 InputDemandedBits = InputDemandedBits.zext(BitWidth); 460 KnownZero = KnownZero.zext(BitWidth); 461 KnownOne = KnownOne.zext(BitWidth); 462 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 463 464 // If the sign bit of the input is known set or clear, then we know the 465 // top bits of the result. 466 467 // If the input sign bit is known zero, or if the NewBits are not demanded 468 // convert this into a zero extension. 469 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) { 470 // Convert to ZExt cast 471 CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName()); 472 return InsertNewInstWith(NewCast, *I); 473 } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set 474 KnownOne |= NewBits; 475 } 476 break; 477 } 478 case Instruction::Add: { 479 // Figure out what the input bits are. If the top bits of the and result 480 // are not demanded, then the add doesn't demand them from its input 481 // either. 482 unsigned NLZ = DemandedMask.countLeadingZeros(); 483 484 // If there is a constant on the RHS, there are a variety of xformations 485 // we can do. 486 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) { 487 // If null, this should be simplified elsewhere. Some of the xforms here 488 // won't work if the RHS is zero. 489 if (RHS->isZero()) 490 break; 491 492 // If the top bit of the output is demanded, demand everything from the 493 // input. Otherwise, we demand all the input bits except NLZ top bits. 494 APInt InDemandedBits(APInt::getLowBitsSet(BitWidth, BitWidth - NLZ)); 495 496 // Find information about known zero/one bits in the input. 497 if (SimplifyDemandedBits(I->getOperandUse(0), InDemandedBits, 498 LHSKnownZero, LHSKnownOne, Depth+1)) 499 return I; 500 501 // If the RHS of the add has bits set that can't affect the input, reduce 502 // the constant. 503 if (ShrinkDemandedConstant(I, 1, InDemandedBits)) 504 return I; 505 506 // Avoid excess work. 507 if (LHSKnownZero == 0 && LHSKnownOne == 0) 508 break; 509 510 // Turn it into OR if input bits are zero. 511 if ((LHSKnownZero & RHS->getValue()) == RHS->getValue()) { 512 Instruction *Or = 513 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), 514 I->getName()); 515 return InsertNewInstWith(Or, *I); 516 } 517 518 // We can say something about the output known-zero and known-one bits, 519 // depending on potential carries from the input constant and the 520 // unknowns. For example if the LHS is known to have at most the 0x0F0F0 521 // bits set and the RHS constant is 0x01001, then we know we have a known 522 // one mask of 0x00001 and a known zero mask of 0xE0F0E. 523 524 // To compute this, we first compute the potential carry bits. These are 525 // the bits which may be modified. I'm not aware of a better way to do 526 // this scan. 527 const APInt &RHSVal = RHS->getValue(); 528 APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^ RHSVal)); 529 530 // Now that we know which bits have carries, compute the known-1/0 sets. 531 532 // Bits are known one if they are known zero in one operand and one in the 533 // other, and there is no input carry. 534 KnownOne = ((LHSKnownZero & RHSVal) | 535 (LHSKnownOne & ~RHSVal)) & ~CarryBits; 536 537 // Bits are known zero if they are known zero in both operands and there 538 // is no input carry. 539 KnownZero = LHSKnownZero & ~RHSVal & ~CarryBits; 540 } else { 541 // If the high-bits of this ADD are not demanded, then it does not demand 542 // the high bits of its LHS or RHS. 543 if (DemandedMask[BitWidth-1] == 0) { 544 // Right fill the mask of bits for this ADD to demand the most 545 // significant bit and all those below it. 546 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); 547 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, 548 LHSKnownZero, LHSKnownOne, Depth+1) || 549 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, 550 LHSKnownZero, LHSKnownOne, Depth+1)) 551 return I; 552 } 553 } 554 break; 555 } 556 case Instruction::Sub: 557 // If the high-bits of this SUB are not demanded, then it does not demand 558 // the high bits of its LHS or RHS. 559 if (DemandedMask[BitWidth-1] == 0) { 560 // Right fill the mask of bits for this SUB to demand the most 561 // significant bit and all those below it. 562 uint32_t NLZ = DemandedMask.countLeadingZeros(); 563 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); 564 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, 565 LHSKnownZero, LHSKnownOne, Depth+1) || 566 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, 567 LHSKnownZero, LHSKnownOne, Depth+1)) 568 return I; 569 } 570 // Otherwise just hand the sub off to ComputeMaskedBits to fill in 571 // the known zeros and ones. 572 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); 573 break; 574 case Instruction::Shl: 575 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { 576 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 577 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); 578 579 // If the shift is NUW/NSW, then it does demand the high bits. 580 ShlOperator *IOp = cast<ShlOperator>(I); 581 if (IOp->hasNoSignedWrap()) 582 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); 583 else if (IOp->hasNoUnsignedWrap()) 584 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt); 585 586 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, 587 KnownZero, KnownOne, Depth+1)) 588 return I; 589 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 590 KnownZero <<= ShiftAmt; 591 KnownOne <<= ShiftAmt; 592 // low bits known zero. 593 if (ShiftAmt) 594 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); 595 } 596 break; 597 case Instruction::LShr: 598 // For a logical shift right 599 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { 600 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 601 602 // Unsigned shift right. 603 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); 604 605 // If the shift is exact, then it does demand the low bits (and knows that 606 // they are zero). 607 if (cast<LShrOperator>(I)->isExact()) 608 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt); 609 610 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, 611 KnownZero, KnownOne, Depth+1)) 612 return I; 613 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 614 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); 615 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); 616 if (ShiftAmt) { 617 // Compute the new bits that are at the top now. 618 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt)); 619 KnownZero |= HighBits; // high bits known zero. 620 } 621 } 622 break; 623 case Instruction::AShr: 624 // If this is an arithmetic shift right and only the low-bit is set, we can 625 // always convert this into a logical shr, even if the shift amount is 626 // variable. The low bit of the shift cannot be an input sign bit unless 627 // the shift amount is >= the size of the datatype, which is undefined. 628 if (DemandedMask == 1) { 629 // Perform the logical shift right. 630 Instruction *NewVal = BinaryOperator::CreateLShr( 631 I->getOperand(0), I->getOperand(1), I->getName()); 632 return InsertNewInstWith(NewVal, *I); 633 } 634 635 // If the sign bit is the only bit demanded by this ashr, then there is no 636 // need to do it, the shift doesn't change the high bit. 637 if (DemandedMask.isSignBit()) 638 return I->getOperand(0); 639 640 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { 641 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 642 643 // Signed shift right. 644 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); 645 // If any of the "high bits" are demanded, we should set the sign bit as 646 // demanded. 647 if (DemandedMask.countLeadingZeros() <= ShiftAmt) 648 DemandedMaskIn.setBit(BitWidth-1); 649 650 // If the shift is exact, then it does demand the low bits (and knows that 651 // they are zero). 652 if (cast<AShrOperator>(I)->isExact()) 653 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt); 654 655 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, 656 KnownZero, KnownOne, Depth+1)) 657 return I; 658 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 659 // Compute the new bits that are at the top now. 660 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt)); 661 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); 662 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); 663 664 // Handle the sign bits. 665 APInt SignBit(APInt::getSignBit(BitWidth)); 666 // Adjust to where it is now in the mask. 667 SignBit = APIntOps::lshr(SignBit, ShiftAmt); 668 669 // If the input sign bit is known to be zero, or if none of the top bits 670 // are demanded, turn this into an unsigned shift right. 671 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] || 672 (HighBits & ~DemandedMask) == HighBits) { 673 // Perform the logical shift right. 674 Instruction *NewVal = BinaryOperator::CreateLShr( 675 I->getOperand(0), SA, I->getName()); 676 return InsertNewInstWith(NewVal, *I); 677 } else if ((KnownOne & SignBit) != 0) { // New bits are known one. 678 KnownOne |= HighBits; 679 } 680 } 681 break; 682 case Instruction::SRem: 683 if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) { 684 // X % -1 demands all the bits because we don't want to introduce 685 // INT_MIN % -1 (== undef) by accident. 686 if (Rem->isAllOnesValue()) 687 break; 688 APInt RA = Rem->getValue().abs(); 689 if (RA.isPowerOf2()) { 690 if (DemandedMask.ult(RA)) // srem won't affect demanded bits 691 return I->getOperand(0); 692 693 APInt LowBits = RA - 1; 694 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 695 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2, 696 LHSKnownZero, LHSKnownOne, Depth+1)) 697 return I; 698 699 // The low bits of LHS are unchanged by the srem. 700 KnownZero = LHSKnownZero & LowBits; 701 KnownOne = LHSKnownOne & LowBits; 702 703 // If LHS is non-negative or has all low bits zero, then the upper bits 704 // are all zero. 705 if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits)) 706 KnownZero |= ~LowBits; 707 708 // If LHS is negative and not all low bits are zero, then the upper bits 709 // are all one. 710 if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0)) 711 KnownOne |= ~LowBits; 712 713 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 714 } 715 } 716 717 // The sign bit is the LHS's sign bit, except when the result of the 718 // remainder is zero. 719 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) { 720 APInt Mask2 = APInt::getSignBit(BitWidth); 721 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); 722 ComputeMaskedBits(I->getOperand(0), Mask2, LHSKnownZero, LHSKnownOne, 723 Depth+1); 724 // If it's known zero, our sign bit is also zero. 725 if (LHSKnownZero.isNegative()) 726 KnownZero |= LHSKnownZero; 727 } 728 break; 729 case Instruction::URem: { 730 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0); 731 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 732 if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes, 733 KnownZero2, KnownOne2, Depth+1) || 734 SimplifyDemandedBits(I->getOperandUse(1), AllOnes, 735 KnownZero2, KnownOne2, Depth+1)) 736 return I; 737 738 unsigned Leaders = KnownZero2.countLeadingOnes(); 739 Leaders = std::max(Leaders, 740 KnownZero2.countLeadingOnes()); 741 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask; 742 break; 743 } 744 case Instruction::Call: 745 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) { 746 switch (II->getIntrinsicID()) { 747 default: break; 748 case Intrinsic::bswap: { 749 // If the only bits demanded come from one byte of the bswap result, 750 // just shift the input byte into position to eliminate the bswap. 751 unsigned NLZ = DemandedMask.countLeadingZeros(); 752 unsigned NTZ = DemandedMask.countTrailingZeros(); 753 754 // Round NTZ down to the next byte. If we have 11 trailing zeros, then 755 // we need all the bits down to bit 8. Likewise, round NLZ. If we 756 // have 14 leading zeros, round to 8. 757 NLZ &= ~7; 758 NTZ &= ~7; 759 // If we need exactly one byte, we can do this transformation. 760 if (BitWidth-NLZ-NTZ == 8) { 761 unsigned ResultBit = NTZ; 762 unsigned InputBit = BitWidth-NTZ-8; 763 764 // Replace this with either a left or right shift to get the byte into 765 // the right place. 766 Instruction *NewVal; 767 if (InputBit > ResultBit) 768 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0), 769 ConstantInt::get(I->getType(), InputBit-ResultBit)); 770 else 771 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0), 772 ConstantInt::get(I->getType(), ResultBit-InputBit)); 773 NewVal->takeName(I); 774 return InsertNewInstWith(NewVal, *I); 775 } 776 777 // TODO: Could compute known zero/one bits based on the input. 778 break; 779 } 780 case Intrinsic::x86_sse42_crc32_64_8: 781 case Intrinsic::x86_sse42_crc32_64_64: 782 KnownZero = APInt::getHighBitsSet(64, 32); 783 return 0; 784 } 785 } 786 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); 787 break; 788 } 789 790 // If the client is only demanding bits that we know, return the known 791 // constant. 792 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 793 return Constant::getIntegerValue(VTy, KnownOne); 794 return 0; 795 } 796 797 798 /// SimplifyDemandedVectorElts - The specified value produces a vector with 799 /// any number of elements. DemandedElts contains the set of elements that are 800 /// actually used by the caller. This method analyzes which elements of the 801 /// operand are undef and returns that information in UndefElts. 802 /// 803 /// If the information about demanded elements can be used to simplify the 804 /// operation, the operation is simplified, then the resultant value is 805 /// returned. This returns null if no change was made. 806 Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, 807 APInt &UndefElts, 808 unsigned Depth) { 809 unsigned VWidth = cast<VectorType>(V->getType())->getNumElements(); 810 APInt EltMask(APInt::getAllOnesValue(VWidth)); 811 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"); 812 813 if (isa<UndefValue>(V)) { 814 // If the entire vector is undefined, just return this info. 815 UndefElts = EltMask; 816 return 0; 817 } 818 819 if (DemandedElts == 0) { // If nothing is demanded, provide undef. 820 UndefElts = EltMask; 821 return UndefValue::get(V->getType()); 822 } 823 824 UndefElts = 0; 825 if (ConstantVector *CV = dyn_cast<ConstantVector>(V)) { 826 Type *EltTy = cast<VectorType>(V->getType())->getElementType(); 827 Constant *Undef = UndefValue::get(EltTy); 828 829 std::vector<Constant*> Elts; 830 for (unsigned i = 0; i != VWidth; ++i) 831 if (!DemandedElts[i]) { // If not demanded, set to undef. 832 Elts.push_back(Undef); 833 UndefElts.setBit(i); 834 } else if (isa<UndefValue>(CV->getOperand(i))) { // Already undef. 835 Elts.push_back(Undef); 836 UndefElts.setBit(i); 837 } else { // Otherwise, defined. 838 Elts.push_back(CV->getOperand(i)); 839 } 840 841 // If we changed the constant, return it. 842 Constant *NewCP = ConstantVector::get(Elts); 843 return NewCP != CV ? NewCP : 0; 844 } 845 846 if (isa<ConstantAggregateZero>(V)) { 847 // Simplify the CAZ to a ConstantVector where the non-demanded elements are 848 // set to undef. 849 850 // Check if this is identity. If so, return 0 since we are not simplifying 851 // anything. 852 if (DemandedElts.isAllOnesValue()) 853 return 0; 854 855 Type *EltTy = cast<VectorType>(V->getType())->getElementType(); 856 Constant *Zero = Constant::getNullValue(EltTy); 857 Constant *Undef = UndefValue::get(EltTy); 858 std::vector<Constant*> Elts; 859 for (unsigned i = 0; i != VWidth; ++i) { 860 Constant *Elt = DemandedElts[i] ? Zero : Undef; 861 Elts.push_back(Elt); 862 } 863 UndefElts = DemandedElts ^ EltMask; 864 return ConstantVector::get(Elts); 865 } 866 867 // Limit search depth. 868 if (Depth == 10) 869 return 0; 870 871 // If multiple users are using the root value, proceed with 872 // simplification conservatively assuming that all elements 873 // are needed. 874 if (!V->hasOneUse()) { 875 // Quit if we find multiple users of a non-root value though. 876 // They'll be handled when it's their turn to be visited by 877 // the main instcombine process. 878 if (Depth != 0) 879 // TODO: Just compute the UndefElts information recursively. 880 return 0; 881 882 // Conservatively assume that all elements are needed. 883 DemandedElts = EltMask; 884 } 885 886 Instruction *I = dyn_cast<Instruction>(V); 887 if (!I) return 0; // Only analyze instructions. 888 889 bool MadeChange = false; 890 APInt UndefElts2(VWidth, 0); 891 Value *TmpV; 892 switch (I->getOpcode()) { 893 default: break; 894 895 case Instruction::InsertElement: { 896 // If this is a variable index, we don't know which element it overwrites. 897 // demand exactly the same input as we produce. 898 ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2)); 899 if (Idx == 0) { 900 // Note that we can't propagate undef elt info, because we don't know 901 // which elt is getting updated. 902 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, 903 UndefElts2, Depth+1); 904 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 905 break; 906 } 907 908 // If this is inserting an element that isn't demanded, remove this 909 // insertelement. 910 unsigned IdxNo = Idx->getZExtValue(); 911 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) { 912 Worklist.Add(I); 913 return I->getOperand(0); 914 } 915 916 // Otherwise, the element inserted overwrites whatever was there, so the 917 // input demanded set is simpler than the output set. 918 APInt DemandedElts2 = DemandedElts; 919 DemandedElts2.clearBit(IdxNo); 920 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2, 921 UndefElts, Depth+1); 922 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 923 924 // The inserted element is defined. 925 UndefElts.clearBit(IdxNo); 926 break; 927 } 928 case Instruction::ShuffleVector: { 929 ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I); 930 uint64_t LHSVWidth = 931 cast<VectorType>(Shuffle->getOperand(0)->getType())->getNumElements(); 932 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0); 933 for (unsigned i = 0; i < VWidth; i++) { 934 if (DemandedElts[i]) { 935 unsigned MaskVal = Shuffle->getMaskValue(i); 936 if (MaskVal != -1u) { 937 assert(MaskVal < LHSVWidth * 2 && 938 "shufflevector mask index out of range!"); 939 if (MaskVal < LHSVWidth) 940 LeftDemanded.setBit(MaskVal); 941 else 942 RightDemanded.setBit(MaskVal - LHSVWidth); 943 } 944 } 945 } 946 947 APInt UndefElts4(LHSVWidth, 0); 948 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded, 949 UndefElts4, Depth+1); 950 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 951 952 APInt UndefElts3(LHSVWidth, 0); 953 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded, 954 UndefElts3, Depth+1); 955 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; } 956 957 bool NewUndefElts = false; 958 for (unsigned i = 0; i < VWidth; i++) { 959 unsigned MaskVal = Shuffle->getMaskValue(i); 960 if (MaskVal == -1u) { 961 UndefElts.setBit(i); 962 } else if (!DemandedElts[i]) { 963 NewUndefElts = true; 964 UndefElts.setBit(i); 965 } else if (MaskVal < LHSVWidth) { 966 if (UndefElts4[MaskVal]) { 967 NewUndefElts = true; 968 UndefElts.setBit(i); 969 } 970 } else { 971 if (UndefElts3[MaskVal - LHSVWidth]) { 972 NewUndefElts = true; 973 UndefElts.setBit(i); 974 } 975 } 976 } 977 978 if (NewUndefElts) { 979 // Add additional discovered undefs. 980 std::vector<Constant*> Elts; 981 for (unsigned i = 0; i < VWidth; ++i) { 982 if (UndefElts[i]) 983 Elts.push_back(UndefValue::get(Type::getInt32Ty(I->getContext()))); 984 else 985 Elts.push_back(ConstantInt::get(Type::getInt32Ty(I->getContext()), 986 Shuffle->getMaskValue(i))); 987 } 988 I->setOperand(2, ConstantVector::get(Elts)); 989 MadeChange = true; 990 } 991 break; 992 } 993 case Instruction::BitCast: { 994 // Vector->vector casts only. 995 VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType()); 996 if (!VTy) break; 997 unsigned InVWidth = VTy->getNumElements(); 998 APInt InputDemandedElts(InVWidth, 0); 999 unsigned Ratio; 1000 1001 if (VWidth == InVWidth) { 1002 // If we are converting from <4 x i32> -> <4 x f32>, we demand the same 1003 // elements as are demanded of us. 1004 Ratio = 1; 1005 InputDemandedElts = DemandedElts; 1006 } else if (VWidth > InVWidth) { 1007 // Untested so far. 1008 break; 1009 1010 // If there are more elements in the result than there are in the source, 1011 // then an input element is live if any of the corresponding output 1012 // elements are live. 1013 Ratio = VWidth/InVWidth; 1014 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) { 1015 if (DemandedElts[OutIdx]) 1016 InputDemandedElts.setBit(OutIdx/Ratio); 1017 } 1018 } else { 1019 // Untested so far. 1020 break; 1021 1022 // If there are more elements in the source than there are in the result, 1023 // then an input element is live if the corresponding output element is 1024 // live. 1025 Ratio = InVWidth/VWidth; 1026 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) 1027 if (DemandedElts[InIdx/Ratio]) 1028 InputDemandedElts.setBit(InIdx); 1029 } 1030 1031 // div/rem demand all inputs, because they don't want divide by zero. 1032 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), InputDemandedElts, 1033 UndefElts2, Depth+1); 1034 if (TmpV) { 1035 I->setOperand(0, TmpV); 1036 MadeChange = true; 1037 } 1038 1039 UndefElts = UndefElts2; 1040 if (VWidth > InVWidth) { 1041 llvm_unreachable("Unimp"); 1042 // If there are more elements in the result than there are in the source, 1043 // then an output element is undef if the corresponding input element is 1044 // undef. 1045 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) 1046 if (UndefElts2[OutIdx/Ratio]) 1047 UndefElts.setBit(OutIdx); 1048 } else if (VWidth < InVWidth) { 1049 llvm_unreachable("Unimp"); 1050 // If there are more elements in the source than there are in the result, 1051 // then a result element is undef if all of the corresponding input 1052 // elements are undef. 1053 UndefElts = ~0ULL >> (64-VWidth); // Start out all undef. 1054 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) 1055 if (!UndefElts2[InIdx]) // Not undef? 1056 UndefElts.clearBit(InIdx/Ratio); // Clear undef bit. 1057 } 1058 break; 1059 } 1060 case Instruction::And: 1061 case Instruction::Or: 1062 case Instruction::Xor: 1063 case Instruction::Add: 1064 case Instruction::Sub: 1065 case Instruction::Mul: 1066 // div/rem demand all inputs, because they don't want divide by zero. 1067 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, 1068 UndefElts, Depth+1); 1069 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 1070 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts, 1071 UndefElts2, Depth+1); 1072 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; } 1073 1074 // Output elements are undefined if both are undefined. Consider things 1075 // like undef&0. The result is known zero, not undef. 1076 UndefElts &= UndefElts2; 1077 break; 1078 1079 case Instruction::Call: { 1080 IntrinsicInst *II = dyn_cast<IntrinsicInst>(I); 1081 if (!II) break; 1082 switch (II->getIntrinsicID()) { 1083 default: break; 1084 1085 // Binary vector operations that work column-wise. A dest element is a 1086 // function of the corresponding input elements from the two inputs. 1087 case Intrinsic::x86_sse_sub_ss: 1088 case Intrinsic::x86_sse_mul_ss: 1089 case Intrinsic::x86_sse_min_ss: 1090 case Intrinsic::x86_sse_max_ss: 1091 case Intrinsic::x86_sse2_sub_sd: 1092 case Intrinsic::x86_sse2_mul_sd: 1093 case Intrinsic::x86_sse2_min_sd: 1094 case Intrinsic::x86_sse2_max_sd: 1095 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts, 1096 UndefElts, Depth+1); 1097 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; } 1098 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts, 1099 UndefElts2, Depth+1); 1100 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; } 1101 1102 // If only the low elt is demanded and this is a scalarizable intrinsic, 1103 // scalarize it now. 1104 if (DemandedElts == 1) { 1105 switch (II->getIntrinsicID()) { 1106 default: break; 1107 case Intrinsic::x86_sse_sub_ss: 1108 case Intrinsic::x86_sse_mul_ss: 1109 case Intrinsic::x86_sse2_sub_sd: 1110 case Intrinsic::x86_sse2_mul_sd: 1111 // TODO: Lower MIN/MAX/ABS/etc 1112 Value *LHS = II->getArgOperand(0); 1113 Value *RHS = II->getArgOperand(1); 1114 // Extract the element as scalars. 1115 LHS = InsertNewInstWith(ExtractElementInst::Create(LHS, 1116 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); 1117 RHS = InsertNewInstWith(ExtractElementInst::Create(RHS, 1118 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); 1119 1120 switch (II->getIntrinsicID()) { 1121 default: llvm_unreachable("Case stmts out of sync!"); 1122 case Intrinsic::x86_sse_sub_ss: 1123 case Intrinsic::x86_sse2_sub_sd: 1124 TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS, 1125 II->getName()), *II); 1126 break; 1127 case Intrinsic::x86_sse_mul_ss: 1128 case Intrinsic::x86_sse2_mul_sd: 1129 TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS, 1130 II->getName()), *II); 1131 break; 1132 } 1133 1134 Instruction *New = 1135 InsertElementInst::Create( 1136 UndefValue::get(II->getType()), TmpV, 1137 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false), 1138 II->getName()); 1139 InsertNewInstWith(New, *II); 1140 return New; 1141 } 1142 } 1143 1144 // Output elements are undefined if both are undefined. Consider things 1145 // like undef&0. The result is known zero, not undef. 1146 UndefElts &= UndefElts2; 1147 break; 1148 } 1149 break; 1150 } 1151 } 1152 return MadeChange ? I : 0; 1153 } 1154