1 ; Test that we handle cmp (register) and cmp (immediate). 2 3 ; REQUIRES: allow_dump 4 5 ; Compile using standalone assembler. 6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \ 7 ; RUN: | FileCheck %s --check-prefix=ASM 8 9 ; Show bytes in assembled standalone code. 10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 11 ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS 12 13 ; Compile using integrated assembler. 14 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \ 15 ; RUN: | FileCheck %s --check-prefix=IASM 16 17 ; Show bytes in assembled integrated code. 18 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 19 ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS 20 21 define internal i32 @cmpEqI8(i32 %a, i32 %b) { 22 ; ASM-LABEL:cmpEqI8: 23 ; DIS-LABEL:00000000 <cmpEqI8>: 24 ; IASM-LABEL:cmpEqI8: 25 26 27 entry: 28 ; ASM-NEXT:.LcmpEqI8$entry: 29 ; IASM-NEXT:.LcmpEqI8$entry: 30 31 %b.arg_trunc = trunc i32 %b to i8 32 %a.arg_trunc = trunc i32 %a to i8 33 34 ; ASM-NEXT: sub sp, sp, #24 35 ; DIS-NEXT: 0: e24dd018 36 ; IASM-NEXT: .byte 0x18 37 ; IASM-NEXT: .byte 0xd0 38 ; IASM-NEXT: .byte 0x4d 39 ; IASM-NEXT: .byte 0xe2 40 41 ; ASM-NEXT: str r0, [sp, #20] 42 ; ASM-NEXT: # [sp, #20] = def.pseudo 43 ; DIS-NEXT: 4: e58d0014 44 ; IASM-NEXT: .byte 0x14 45 ; IASM-NEXT: .byte 0x0 46 ; IASM-NEXT: .byte 0x8d 47 ; IASM-NEXT: .byte 0xe5 48 49 ; ASM-NEXT: str r1, [sp, #16] 50 ; ASM-NEXT: # [sp, #16] = def.pseudo 51 ; DIS-NEXT: 8: e58d1010 52 ; IASM-NEXT: .byte 0x10 53 ; IASM-NEXT: .byte 0x10 54 ; IASM-NEXT: .byte 0x8d 55 ; IASM-NEXT: .byte 0xe5 56 57 ; ASM-NEXT: ldr r0, [sp, #16] 58 ; DIS-NEXT: c: e59d0010 59 ; IASM-NEXT: .byte 0x10 60 ; IASM-NEXT: .byte 0x0 61 ; IASM-NEXT: .byte 0x9d 62 ; IASM-NEXT: .byte 0xe5 63 64 ; ASM-NEXT: strb r0, [sp, #12] 65 ; ASM-NEXT: # [sp, #12] = def.pseudo 66 ; DIS-NEXT: 10: e5cd000c 67 ; IASM-NEXT: .byte 0xc 68 ; IASM-NEXT: .byte 0x0 69 ; IASM-NEXT: .byte 0xcd 70 ; IASM-NEXT: .byte 0xe5 71 72 ; ASM-NEXT: ldr r0, [sp, #20] 73 ; DIS-NEXT: 14: e59d0014 74 ; IASM-NEXT: .byte 0x14 75 ; IASM-NEXT: .byte 0x0 76 ; IASM-NEXT: .byte 0x9d 77 ; IASM-NEXT: .byte 0xe5 78 79 ; ASM-NEXT: strb r0, [sp, #8] 80 ; ASM-NEXT: # [sp, #8] = def.pseudo 81 ; DIS-NEXT: 18: e5cd0008 82 ; IASM-NEXT: .byte 0x8 83 ; IASM-NEXT: .byte 0x0 84 ; IASM-NEXT: .byte 0xcd 85 ; IASM-NEXT: .byte 0xe5 86 87 ; ASM-NEXT: mov r0, #0 88 ; DIS-NEXT: 1c: e3a00000 89 ; IASM-NEXT: .byte 0x0 90 ; IASM-NEXT: .byte 0x0 91 ; IASM-NEXT: .byte 0xa0 92 ; IASM-NEXT: .byte 0xe3 93 94 ; ASM-NEXT: ldrb r1, [sp, #8] 95 ; DIS-NEXT: 20: e5dd1008 96 ; IASM-NEXT: .byte 0x8 97 ; IASM-NEXT: .byte 0x10 98 ; IASM-NEXT: .byte 0xdd 99 ; IASM-NEXT: .byte 0xe5 100 101 ; ASM-NEXT: lsl r1, r1, #24 102 ; DIS-NEXT: 24: e1a01c01 103 ; IASM-NEXT: .byte 0x1 104 ; IASM-NEXT: .byte 0x1c 105 ; IASM-NEXT: .byte 0xa0 106 ; IASM-NEXT: .byte 0xe1 107 108 ; ASM-NEXT: ldrb r2, [sp, #12] 109 ; DIS-NEXT: 28: e5dd200c 110 ; IASM-NEXT: .byte 0xc 111 ; IASM-NEXT: .byte 0x20 112 ; IASM-NEXT: .byte 0xdd 113 ; IASM-NEXT: .byte 0xe5 114 115 ; ******** CMP instruction test ************** 116 117 %cmp = icmp eq i8 %a.arg_trunc, %b.arg_trunc 118 119 ; ASM-NEXT: cmp r1, r2, lsl #24 120 ; DIS-NEXT: 2c: e1510c02 121 ; IASM-NEXT: .byte 0x2 122 ; IASM-NEXT: .byte 0xc 123 ; IASM-NEXT: .byte 0x51 124 ; IASM-NEXT: .byte 0xe1 125 126 %cmp.ret_ext = zext i1 %cmp to i32 127 ret i32 %cmp.ret_ext 128 } 129 130 define internal i32 @cmpEqI32(i32 %a, i32 %b) { 131 ; ASM-LABEL:cmpEqI32: 132 ; DIS-LABEL:00000050 <cmpEqI32>: 133 ; IASM-LABEL:cmpEqI32: 134 135 entry: 136 ; ASM-NEXT:.LcmpEqI32$entry: 137 ; IASM-NEXT:.LcmpEqI32$entry: 138 139 ; ASM-NEXT: sub sp, sp, #16 140 ; DIS-NEXT: 50: e24dd010 141 ; IASM-NEXT: .byte 0x10 142 ; IASM-NEXT: .byte 0xd0 143 ; IASM-NEXT: .byte 0x4d 144 ; IASM-NEXT: .byte 0xe2 145 146 ; ASM-NEXT: str r0, [sp, #12] 147 ; ASM-NEXT: # [sp, #12] = def.pseudo 148 ; DIS-NEXT: 54: e58d000c 149 ; IASM-NEXT: .byte 0xc 150 ; IASM-NEXT: .byte 0x0 151 ; IASM-NEXT: .byte 0x8d 152 ; IASM-NEXT: .byte 0xe5 153 154 ; ASM-NEXT: str r1, [sp, #8] 155 ; ASM-NEXT: # [sp, #8] = def.pseudo 156 ; DIS-NEXT: 58: e58d1008 157 ; IASM-NEXT: .byte 0x8 158 ; IASM-NEXT: .byte 0x10 159 ; IASM-NEXT: .byte 0x8d 160 ; IASM-NEXT: .byte 0xe5 161 162 ; ASM-NEXT: mov r0, #0 163 ; DIS-NEXT: 5c: e3a00000 164 ; IASM-NEXT: .byte 0x0 165 ; IASM-NEXT: .byte 0x0 166 ; IASM-NEXT: .byte 0xa0 167 ; IASM-NEXT: .byte 0xe3 168 169 ; ASM-NEXT: ldr r1, [sp, #12] 170 ; DIS-NEXT: 60: e59d100c 171 ; IASM-NEXT: .byte 0xc 172 ; IASM-NEXT: .byte 0x10 173 ; IASM-NEXT: .byte 0x9d 174 ; IASM-NEXT: .byte 0xe5 175 176 ; ASM-NEXT: ldr r2, [sp, #8] 177 ; DIS-NEXT: 64: e59d2008 178 ; IASM-NEXT: .byte 0x8 179 ; IASM-NEXT: .byte 0x20 180 ; IASM-NEXT: .byte 0x9d 181 ; IASM-NEXT: .byte 0xe5 182 183 ; ******** CMP instruction test ************** 184 185 %cmp = icmp eq i32 %a, %b 186 187 ; ASM-NEXT: cmp r1, r2 188 ; DIS-NEXT: 68: e1510002 189 ; IASM-NEXT: .byte 0x2 190 ; IASM-NEXT: .byte 0x0 191 ; IASM-NEXT: .byte 0x51 192 ; IASM-NEXT: .byte 0xe1 193 194 %cmp.ret_ext = zext i1 %cmp to i32 195 ret i32 %cmp.ret_ext 196 } 197