1 ; Sample program that generates "str reg, [fp, #CCCC]", to show that we 2 ; recognize that "fp" should be used instead of "sp". 3 4 ; REQUIRES: allow_dump 5 6 ; Compile using standalone assembler. 7 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \ 8 ; RUN: | FileCheck %s --check-prefix=ASM 9 10 ; Show bytes in assembled standalone code. 11 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 12 ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS 13 14 ; Compile using integrated assembler. 15 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \ 16 ; RUN: | FileCheck %s --check-prefix=IASM 17 18 ; Show bytes in assembled integrated code. 19 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 20 ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS 21 22 define internal void @test_vla_in_loop(i32 %n) { 23 ; ASM-LABEL: test_vla_in_loop: 24 ; DIS-LABEL: 00000000 <test_vla_in_loop>: 25 ; IASM-LABEL: test_vla_in_loop: 26 27 entry: 28 29 ; ASM-NEXT: .Ltest_vla_in_loop$entry: 30 ; IASM-NEXT: .Ltest_vla_in_loop$entry: 31 32 ; ASM-NEXT: push {fp} 33 ; DIS-NEXT: 0: e52db004 34 ; IASM-NEXT: .byte 0x4 35 ; IASM-NEXT: .byte 0xb0 36 ; IASM-NEXT: .byte 0x2d 37 ; IASM-NEXT: .byte 0xe5 38 39 ; ASM-NEXT: mov fp, sp 40 ; DIS-NEXT: 4: e1a0b00d 41 ; IASM-NEXT: .byte 0xd 42 ; IASM-NEXT: .byte 0xb0 43 ; IASM-NEXT: .byte 0xa0 44 ; IASM-NEXT: .byte 0xe1 45 46 ; ASM-NEXT: sub sp, sp, #12 47 ; DIS-NEXT: 8: e24dd00c 48 ; IASM-NEXT: .byte 0xc 49 ; IASM-NEXT: .byte 0xd0 50 ; IASM-NEXT: .byte 0x4d 51 ; IASM-NEXT: .byte 0xe2 52 53 ; **** Example of fixed instruction. 54 ; ASM-NEXT: str r0, [fp, #-4] 55 ; DIS-NEXT: c: e50b0004 56 ; IASM-NEXT: .byte 0x4 57 ; IASM-NEXT: .byte 0x0 58 ; IASM-NEXT: .byte 0xb 59 ; IASM-NEXT: .byte 0xe5 60 ; ASM-NEXT: # [fp, #-4] = def.pseudo 61 br label %next 62 63 ; ASM-NEXT: b .Ltest_vla_in_loop$next 64 ; DIS-NEXT: 10: eaffffff 65 66 ; IASM-NEXT: .byte 0xff 67 ; IASM-NEXT: .byte 0xff 68 ; IASM-NEXT: .byte 0xff 69 ; IASM-NEXT: .byte 0xea 70 71 ; Put the variable-length alloca in a non-entry block, to reduce the 72 ; chance the optimizer putting it before the regular frame creation. 73 74 next: 75 %v = alloca i8, i32 %n, align 4 76 ret void 77 } 78
