1 ; Show that we translate intrinsics for fabs on float, double and float vectors. 2 3 ; REQUIRES: allow_dump 4 5 ; Compile using standalone assembler. 6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \ 7 ; RUN: -reg-use s20,d22 \ 8 ; RUN: | FileCheck %s --check-prefix=ASM 9 10 ; Show bytes in assembled standalone code. 11 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 12 ; RUN: --args -Om1 \ 13 ; RUN: -reg-use s20,d22 \ 14 ; RUN: | FileCheck %s --check-prefix=DIS 15 16 ; Compile using integrated assembler. 17 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \ 18 ; RUN: -reg-use s20,d22 \ 19 ; RUN: | FileCheck %s --check-prefix=IASM 20 21 ; Show bytes in assembled integrated code. 22 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 23 ; RUN: --args -Om1 \ 24 ; RUN: -reg-use s20,d22 \ 25 ; RUN: | FileCheck %s --check-prefix=DIS 26 27 declare float @llvm.fabs.f32(float) 28 declare double @llvm.fabs.f64(double) 29 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) 30 31 define internal float @test_fabs_float(float %x) { 32 ; ASM-LABEL: test_fabs_float: 33 ; DIS-LABEL: 00000000 <test_fabs_float>: 34 ; IASM-LABEL: test_fabs_float: 35 36 entry: 37 %r = call float @llvm.fabs.f32(float %x) 38 39 ; ASM: vabs.f32 s20, s20 40 ; DIS: 10: eeb0aaca 41 ; IASM-NOT: vabs.f32 42 43 ret float %r 44 } 45 46 define internal double @test_fabs_double(double %x) { 47 ; ASM-LABEL: test_fabs_double: 48 ; DIS-LABEL: 00000030 <test_fabs_double>: 49 ; IASM-LABEL: test_fabs_double: 50 51 entry: 52 %r = call double @llvm.fabs.f64(double %x) 53 54 ; ASM: vabs.f64 d22, d22 55 ; DIS: 3c: eef06be6 56 ; IASM-NOT: vabs.64 57 58 ret double %r 59 } 60 61 define internal <4 x float> @test_fabs_4float(<4 x float> %x) { 62 ; ASM-LABEL: test_fabs_4float: 63 ; DIS-LABEL: 00000050 <test_fabs_4float>: 64 ; IASM-LABEL: test_fabs_4float: 65 66 entry: 67 %r = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) 68 69 ; ASM: vabs.f32 q0, q0 70 ; DIS: 60: f3b90740 71 ; IASM-NOT: vabs.f32 72 73 ret <4 x float> %r 74 } 75
