1 /* 2 * gPXE driver for Intel eepro1000 ethernet cards 3 * 4 * Written by Marty Connor 5 * 6 * Copyright Entity Cyber, Inc. 2007 7 * 8 * This software may be used and distributed according to the terms of 9 * the GNU General Public License (GPL), incorporated herein by 10 * reference. Drivers based on or derived from this code fall under 11 * the GPL and must retain the authorship, copyright and license 12 * notice. 13 * 14 */ 15 16 /******************************************************************************* 17 18 Intel PRO/1000 Linux driver 19 Copyright(c) 1999 - 2006 Intel Corporation. 20 21 This program is free software; you can redistribute it and/or modify it 22 under the terms and conditions of the GNU General Public License, 23 version 2, as published by the Free Software Foundation. 24 25 This program is distributed in the hope it will be useful, but WITHOUT 26 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 27 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 28 more details. 29 30 You should have received a copy of the GNU General Public License along with 31 this program; if not, write to the Free Software Foundation, Inc., 32 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 33 34 The full GNU General Public License is included in this distribution in 35 the file called "COPYING". 36 37 Contact Information: 38 Linux NICS <linux.nics (at) intel.com> 39 e1000-devel Mailing List <e1000-devel (at) lists.sourceforge.net> 40 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 41 42 *******************************************************************************/ 43 44 FILE_LICENCE ( GPL2_ONLY ); 45 46 #include "e1000.h" 47 48 /** 49 * e1000_get_hw_control - get control of the h/w from f/w 50 * 51 * @v adapter e1000 private structure 52 * 53 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 54 * For ASF and Pass Through versions of f/w this means that 55 * the driver is loaded. For AMT version (only with 82573) 56 * of the f/w this means that the network i/f is open. 57 * 58 **/ 59 static void 60 e1000_get_hw_control ( struct e1000_adapter *adapter ) 61 { 62 uint32_t ctrl_ext; 63 uint32_t swsm; 64 65 DBG ( "e1000_get_hw_control\n" ); 66 67 /* Let firmware know the driver has taken over */ 68 switch (adapter->hw.mac_type) { 69 case e1000_82573: 70 swsm = E1000_READ_REG(&adapter->hw, SWSM); 71 E1000_WRITE_REG(&adapter->hw, SWSM, 72 swsm | E1000_SWSM_DRV_LOAD); 73 break; 74 case e1000_82571: 75 case e1000_82572: 76 case e1000_82576: 77 case e1000_80003es2lan: 78 case e1000_ich8lan: 79 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT); 80 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, 81 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 82 break; 83 default: 84 break; 85 } 86 } 87 88 /** 89 * e1000_irq_enable - Enable default interrupt generation settings 90 * 91 * @v adapter e1000 private structure 92 **/ 93 static void 94 e1000_irq_enable ( struct e1000_adapter *adapter ) 95 { 96 E1000_WRITE_REG ( &adapter->hw, IMS, IMS_ENABLE_MASK ); 97 E1000_WRITE_FLUSH ( &adapter->hw ); 98 } 99 100 /** 101 * e1000_irq_disable - Mask off interrupt generation on the NIC 102 * 103 * @v adapter e1000 private structure 104 **/ 105 static void 106 e1000_irq_disable ( struct e1000_adapter *adapter ) 107 { 108 E1000_WRITE_REG ( &adapter->hw, IMC, ~0 ); 109 E1000_WRITE_FLUSH ( &adapter->hw ); 110 } 111 112 /** 113 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 114 * 115 * @v adapter e1000 private structure 116 * 117 * e1000_sw_init initializes the Adapter private data structure. 118 * Fields are initialized based on PCI device information and 119 * OS network device settings (MTU size). 120 **/ 121 static int 122 e1000_sw_init ( struct e1000_adapter *adapter ) 123 { 124 struct e1000_hw *hw = &adapter->hw; 125 struct pci_device *pdev = adapter->pdev; 126 127 /* PCI config space info */ 128 129 hw->vendor_id = pdev->vendor; 130 hw->device_id = pdev->device; 131 132 pci_read_config_word ( pdev, PCI_COMMAND, &hw->pci_cmd_word ); 133 134 /* Disable Flow Control */ 135 hw->fc = E1000_FC_NONE; 136 137 adapter->eeprom_wol = 0; 138 adapter->wol = adapter->eeprom_wol; 139 adapter->en_mng_pt = 0; 140 adapter->rx_int_delay = 0; 141 adapter->rx_abs_int_delay = 0; 142 143 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; 144 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128; 145 hw->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE + 146 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 147 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE; 148 149 /* identify the MAC */ 150 151 if ( e1000_set_mac_type ( hw ) ) { 152 DBG ( "Unknown MAC Type\n" ); 153 return -EIO; 154 } 155 156 switch ( hw->mac_type ) { 157 default: 158 break; 159 case e1000_82541: 160 case e1000_82547: 161 case e1000_82541_rev_2: 162 case e1000_82547_rev_2: 163 hw->phy_init_script = 1; 164 break; 165 } 166 167 e1000_set_media_type ( hw ); 168 169 hw->autoneg = TRUE; 170 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 171 hw->wait_autoneg_complete = TRUE; 172 173 hw->tbi_compatibility_en = TRUE; 174 hw->adaptive_ifs = TRUE; 175 176 /* Copper options */ 177 178 if ( hw->media_type == e1000_media_type_copper ) { 179 hw->mdix = AUTO_ALL_MODES; 180 hw->disable_polarity_correction = FALSE; 181 hw->master_slave = E1000_MASTER_SLAVE; 182 } 183 184 e1000_irq_disable ( adapter ); 185 186 return 0; 187 } 188 189 /** 190 * e1000_setup_tx_resources - allocate Tx resources (Descriptors) 191 * 192 * @v adapter e1000 private structure 193 * 194 * @ret rc Returns 0 on success, negative on failure 195 **/ 196 static int 197 e1000_setup_tx_resources ( struct e1000_adapter *adapter ) 198 { 199 DBG ( "e1000_setup_tx_resources\n" ); 200 201 /* Allocate transmit descriptor ring memory. 202 It must not cross a 64K boundary because of hardware errata #23 203 so we use malloc_dma() requesting a 128 byte block that is 204 128 byte aligned. This should guarantee that the memory 205 allocated will not cross a 64K boundary, because 128 is an 206 even multiple of 65536 ( 65536 / 128 == 512 ), so all possible 207 allocations of 128 bytes on a 128 byte boundary will not 208 cross 64K bytes. 209 */ 210 211 adapter->tx_base = 212 malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size ); 213 214 if ( ! adapter->tx_base ) { 215 return -ENOMEM; 216 } 217 218 memset ( adapter->tx_base, 0, adapter->tx_ring_size ); 219 220 DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) ); 221 222 return 0; 223 } 224 225 static void 226 e1000_free_tx_resources ( struct e1000_adapter *adapter ) 227 { 228 DBG ( "e1000_free_tx_resources\n" ); 229 230 free_dma ( adapter->tx_base, adapter->tx_ring_size ); 231 } 232 233 /** 234 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 235 * @adapter: board private structure 236 * 237 * Configure the Tx unit of the MAC after a reset. 238 **/ 239 static void 240 e1000_configure_tx ( struct e1000_adapter *adapter ) 241 { 242 struct e1000_hw *hw = &adapter->hw; 243 uint32_t tctl; 244 uint32_t txdctl; 245 246 DBG ( "e1000_configure_tx\n" ); 247 248 E1000_WRITE_REG ( hw, TDBAH, 0 ); 249 E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) ); 250 E1000_WRITE_REG ( hw, TDLEN, adapter->tx_ring_size ); 251 252 DBG ( "TDBAL: %#08x\n", E1000_READ_REG ( hw, TDBAL ) ); 253 DBG ( "TDLEN: %d\n", E1000_READ_REG ( hw, TDLEN ) ); 254 255 /* Setup the HW Tx Head and Tail descriptor pointers */ 256 E1000_WRITE_REG ( hw, TDH, 0 ); 257 E1000_WRITE_REG ( hw, TDT, 0 ); 258 259 adapter->tx_head = 0; 260 adapter->tx_tail = 0; 261 adapter->tx_fill_ctr = 0; 262 263 if (hw->mac_type == e1000_82576) { 264 txdctl = E1000_READ_REG ( hw, TXDCTL ); 265 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 266 E1000_WRITE_REG ( hw, TXDCTL, txdctl ); 267 } 268 269 /* Setup Transmit Descriptor Settings for eop descriptor */ 270 tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 271 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 272 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT); 273 274 e1000_config_collision_dist ( hw ); 275 276 E1000_WRITE_REG ( hw, TCTL, tctl ); 277 E1000_WRITE_FLUSH ( hw ); 278 } 279 280 static void 281 e1000_free_rx_resources ( struct e1000_adapter *adapter ) 282 { 283 int i; 284 285 DBG ( "e1000_free_rx_resources\n" ); 286 287 free_dma ( adapter->rx_base, adapter->rx_ring_size ); 288 289 for ( i = 0; i < NUM_RX_DESC; i++ ) { 290 free_iob ( adapter->rx_iobuf[i] ); 291 } 292 } 293 294 /** 295 * e1000_refill_rx_ring - allocate Rx io_buffers 296 * 297 * @v adapter e1000 private structure 298 * 299 * @ret rc Returns 0 on success, negative on failure 300 **/ 301 int e1000_refill_rx_ring ( struct e1000_adapter *adapter ) 302 { 303 int i, rx_curr; 304 int rc = 0; 305 struct e1000_rx_desc *rx_curr_desc; 306 struct e1000_hw *hw = &adapter->hw; 307 struct io_buffer *iob; 308 309 DBG ("e1000_refill_rx_ring\n"); 310 311 for ( i = 0; i < NUM_RX_DESC; i++ ) { 312 rx_curr = ( ( adapter->rx_curr + i ) % NUM_RX_DESC ); 313 rx_curr_desc = adapter->rx_base + rx_curr; 314 315 if ( rx_curr_desc->status & E1000_RXD_STAT_DD ) 316 continue; 317 318 if ( adapter->rx_iobuf[rx_curr] != NULL ) 319 continue; 320 321 DBG2 ( "Refilling rx desc %d\n", rx_curr ); 322 323 iob = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE ); 324 adapter->rx_iobuf[rx_curr] = iob; 325 326 if ( ! iob ) { 327 DBG ( "alloc_iob failed\n" ); 328 rc = -ENOMEM; 329 break; 330 } else { 331 rx_curr_desc->buffer_addr = virt_to_bus ( iob->data ); 332 333 E1000_WRITE_REG ( hw, RDT, rx_curr ); 334 } 335 } 336 return rc; 337 } 338 339 /** 340 * e1000_setup_rx_resources - allocate Rx resources (Descriptors) 341 * 342 * @v adapter e1000 private structure 343 * 344 * @ret rc Returns 0 on success, negative on failure 345 **/ 346 static int 347 e1000_setup_rx_resources ( struct e1000_adapter *adapter ) 348 { 349 int i, rc = 0; 350 351 DBG ( "e1000_setup_rx_resources\n" ); 352 353 /* Allocate receive descriptor ring memory. 354 It must not cross a 64K boundary because of hardware errata 355 */ 356 357 adapter->rx_base = 358 malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size ); 359 360 if ( ! adapter->rx_base ) { 361 return -ENOMEM; 362 } 363 memset ( adapter->rx_base, 0, adapter->rx_ring_size ); 364 365 for ( i = 0; i < NUM_RX_DESC; i++ ) { 366 /* let e1000_refill_rx_ring() io_buffer allocations */ 367 adapter->rx_iobuf[i] = NULL; 368 } 369 370 /* allocate io_buffers */ 371 rc = e1000_refill_rx_ring ( adapter ); 372 if ( rc < 0 ) 373 e1000_free_rx_resources ( adapter ); 374 375 return rc; 376 } 377 378 /** 379 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 380 * @adapter: board private structure 381 * 382 * Configure the Rx unit of the MAC after a reset. 383 **/ 384 static void 385 e1000_configure_rx ( struct e1000_adapter *adapter ) 386 { 387 struct e1000_hw *hw = &adapter->hw; 388 uint32_t rctl, rxdctl, mrqc, rxcsum; 389 390 DBG ( "e1000_configure_rx\n" ); 391 392 /* disable receives while setting up the descriptors */ 393 rctl = E1000_READ_REG ( hw, RCTL ); 394 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN ); 395 E1000_WRITE_FLUSH ( hw ); 396 mdelay(10); 397 398 adapter->rx_curr = 0; 399 400 /* Setup the HW Rx Head and Tail Descriptor Pointers and 401 * the Base and Length of the Rx Descriptor Ring */ 402 403 E1000_WRITE_REG ( hw, RDBAL, virt_to_bus ( adapter->rx_base ) ); 404 E1000_WRITE_REG ( hw, RDBAH, 0 ); 405 E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size ); 406 407 E1000_WRITE_REG ( hw, RDH, 0 ); 408 if (hw->mac_type == e1000_82576) 409 E1000_WRITE_REG ( hw, RDT, 0 ); 410 else 411 E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 ); 412 413 /* This doesn't seem to be necessary for correct operation, 414 * but it seems as well to be implicit 415 */ 416 if (hw->mac_type == e1000_82576) { 417 rxdctl = E1000_READ_REG ( hw, RXDCTL ); 418 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 419 rxdctl &= 0xFFF00000; 420 rxdctl |= IGB_RX_PTHRESH; 421 rxdctl |= IGB_RX_HTHRESH << 8; 422 rxdctl |= IGB_RX_WTHRESH << 16; 423 E1000_WRITE_REG ( hw, RXDCTL, rxdctl ); 424 E1000_WRITE_FLUSH ( hw ); 425 426 rxcsum = E1000_READ_REG(hw, RXCSUM); 427 rxcsum &= ~( E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE ); 428 E1000_WRITE_REG ( hw, RXCSUM, 0 ); 429 430 /* The initial value for MRQC disables multiple receive 431 * queues, however this setting is not recommended. 432 * - Intel 82576 Gigabit Ethernet Controller Datasheet r2.41 433 * Section 8.10.9 Multiple Queues Command Register - MRQC 434 */ 435 mrqc = E1000_MRQC_ENABLE_VMDQ; 436 E1000_WRITE_REG ( hw, MRQC, mrqc ); 437 } 438 439 /* Enable Receives */ 440 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | 441 E1000_RCTL_MPE; 442 E1000_WRITE_REG ( hw, RCTL, rctl ); 443 E1000_WRITE_FLUSH ( hw ); 444 445 /* On the 82576, RDT([0]) must not be "bumped" before 446 * the enable bit of RXDCTL([0]) is set. 447 * - Intel 82576 Gigabit Ethernet Controller Datasheet r2.41 448 * Section 4.5.9 receive Initialization 449 * 450 * By observation I have found to occur when the enable bit of 451 * RCTL is set. The datasheet recommends polling for this bit, 452 * however as I see no evidence of this in the Linux igb driver 453 * I have omitted that step. 454 * - Simon Horman, May 2009 455 */ 456 if (hw->mac_type == e1000_82576) 457 E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 ); 458 459 DBG ( "RDBAL: %#08x\n", E1000_READ_REG ( hw, RDBAL ) ); 460 DBG ( "RDLEN: %d\n", E1000_READ_REG ( hw, RDLEN ) ); 461 DBG ( "RCTL: %#08x\n", E1000_READ_REG ( hw, RCTL ) ); 462 } 463 464 /** 465 * e1000_reset - Put e1000 NIC in known initial state 466 * 467 * @v adapter e1000 private structure 468 **/ 469 static void 470 e1000_reset ( struct e1000_adapter *adapter ) 471 { 472 uint32_t pba = 0; 473 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF; 474 475 DBG ( "e1000_reset\n" ); 476 477 switch (adapter->hw.mac_type) { 478 case e1000_82542_rev2_0: 479 case e1000_82542_rev2_1: 480 case e1000_82543: 481 case e1000_82544: 482 case e1000_82540: 483 case e1000_82541: 484 case e1000_82541_rev_2: 485 pba = E1000_PBA_48K; 486 break; 487 case e1000_82545: 488 case e1000_82545_rev_3: 489 case e1000_82546: 490 case e1000_82546_rev_3: 491 pba = E1000_PBA_48K; 492 break; 493 case e1000_82547: 494 case e1000_82547_rev_2: 495 pba = E1000_PBA_30K; 496 break; 497 case e1000_82571: 498 case e1000_82572: 499 case e1000_80003es2lan: 500 pba = E1000_PBA_38K; 501 break; 502 case e1000_82573: 503 pba = E1000_PBA_20K; 504 break; 505 case e1000_82576: 506 pba = E1000_PBA_64K; 507 break; 508 case e1000_ich8lan: 509 pba = E1000_PBA_8K; 510 case e1000_undefined: 511 case e1000_num_macs: 512 break; 513 } 514 515 E1000_WRITE_REG ( &adapter->hw, PBA, pba ); 516 517 /* flow control settings */ 518 /* Set the FC high water mark to 90% of the FIFO size. 519 * Required to clear last 3 LSB */ 520 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8; 521 522 /* We can't use 90% on small FIFOs because the remainder 523 * would be less than 1 full frame. In this case, we size 524 * it to allow at least a full frame above the high water 525 * mark. */ 526 if (pba < E1000_PBA_16K) 527 fc_high_water_mark = (pba * 1024) - 1600; 528 529 /* This actually applies to < e1000_82575, one revision less than 530 * e1000_82576, but e1000_82575 isn't currently defined in the code */ 531 if (adapter->hw.mac_type < e1000_82576) { 532 /* 8-byte granularity */ 533 adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF8; 534 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 8; 535 } else { 536 /* 16-byte granularity */ 537 adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF0; 538 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 16; 539 } 540 541 if (adapter->hw.mac_type == e1000_80003es2lan || 542 adapter->hw.mac_type == e1000_82576) 543 adapter->hw.fc_pause_time = 0xFFFF; 544 else 545 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME; 546 adapter->hw.fc_send_xon = 1; 547 adapter->hw.fc = adapter->hw.original_fc; 548 /* Allow time for pending master requests to run */ 549 550 e1000_reset_hw ( &adapter->hw ); 551 552 if ( adapter->hw.mac_type >= e1000_82544 ) 553 E1000_WRITE_REG ( &adapter->hw, WUC, 0 ); 554 555 if ( e1000_init_hw ( &adapter->hw ) ) 556 DBG ( "Hardware Error\n" ); 557 558 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */ 559 if (adapter->hw.mac_type >= e1000_82544 && 560 adapter->hw.mac_type <= e1000_82547_rev_2 && 561 adapter->hw.autoneg == 1 && 562 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) { 563 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL); 564 /* clear phy power management bit if we are in gig only mode, 565 * which if enabled will attempt negotiation to 100Mb, which 566 * can cause a loss of link at power off or driver unload */ 567 ctrl &= ~E1000_CTRL_SWDPIN3; 568 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 569 } 570 571 e1000_phy_get_info ( &adapter->hw, &adapter->phy_info ); 572 573 if (!adapter->smart_power_down && 574 (adapter->hw.mac_type == e1000_82571 || 575 adapter->hw.mac_type == e1000_82572)) { 576 uint16_t phy_data = 0; 577 /* speed up time to link by disabling smart power down, ignore 578 * the return value of this function because there is nothing 579 * different we would do if it failed */ 580 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, 581 &phy_data); 582 phy_data &= ~IGP02E1000_PM_SPD; 583 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, 584 phy_data); 585 } 586 } 587 588 /** Functions that implement the gPXE driver API **/ 589 590 /** 591 * e1000_close - Disables a network interface 592 * 593 * @v netdev network interface device structure 594 * 595 **/ 596 static void 597 e1000_close ( struct net_device *netdev ) 598 { 599 struct e1000_adapter *adapter = netdev_priv ( netdev ); 600 struct e1000_hw *hw = &adapter->hw; 601 uint32_t rctl; 602 uint32_t icr; 603 604 DBG ( "e1000_close\n" ); 605 606 /* Acknowledge interrupts */ 607 icr = E1000_READ_REG ( hw, ICR ); 608 609 e1000_irq_disable ( adapter ); 610 611 /* disable receives */ 612 rctl = E1000_READ_REG ( hw, RCTL ); 613 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN ); 614 E1000_WRITE_FLUSH ( hw ); 615 616 e1000_reset_hw ( hw ); 617 618 e1000_free_tx_resources ( adapter ); 619 e1000_free_rx_resources ( adapter ); 620 } 621 622 /** 623 * e1000_transmit - Transmit a packet 624 * 625 * @v netdev Network device 626 * @v iobuf I/O buffer 627 * 628 * @ret rc Returns 0 on success, negative on failure 629 */ 630 static int 631 e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) 632 { 633 struct e1000_adapter *adapter = netdev_priv( netdev ); 634 struct e1000_hw *hw = &adapter->hw; 635 uint32_t tx_curr = adapter->tx_tail; 636 struct e1000_tx_desc *tx_curr_desc; 637 638 DBG ("e1000_transmit\n"); 639 640 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) { 641 DBG ("TX overflow\n"); 642 return -ENOBUFS; 643 } 644 645 /* Save pointer to iobuf we have been given to transmit, 646 netdev_tx_complete() will need it later 647 */ 648 adapter->tx_iobuf[tx_curr] = iobuf; 649 650 tx_curr_desc = ( void * ) ( adapter->tx_base ) + 651 ( tx_curr * sizeof ( *adapter->tx_base ) ); 652 653 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); 654 DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 ); 655 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) ); 656 657 /* Add the packet to TX ring 658 */ 659 tx_curr_desc->buffer_addr = 660 virt_to_bus ( iobuf->data ); 661 tx_curr_desc->lower.data = 662 E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | 663 E1000_TXD_CMD_IFCS | iob_len ( iobuf ); 664 tx_curr_desc->upper.data = 0; 665 666 DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr, 667 tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) ); 668 669 /* Point to next free descriptor */ 670 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC; 671 adapter->tx_fill_ctr++; 672 673 /* Write new tail to NIC, making packet available for transmit 674 */ 675 wmb(); 676 E1000_WRITE_REG ( hw, TDT, adapter->tx_tail ); 677 678 return 0; 679 } 680 681 /** 682 * e1000_poll - Poll for received packets 683 * 684 * @v netdev Network device 685 */ 686 static void 687 e1000_poll ( struct net_device *netdev ) 688 { 689 struct e1000_adapter *adapter = netdev_priv( netdev ); 690 struct e1000_hw *hw = &adapter->hw; 691 692 uint32_t icr; 693 uint32_t tx_status; 694 uint32_t rx_status; 695 uint32_t rx_len; 696 uint32_t rx_err; 697 struct e1000_tx_desc *tx_curr_desc; 698 struct e1000_rx_desc *rx_curr_desc; 699 uint32_t i; 700 701 DBGP ( "e1000_poll\n" ); 702 703 /* Acknowledge interrupts */ 704 icr = E1000_READ_REG ( hw, ICR ); 705 if ( ! icr ) 706 return; 707 708 DBG ( "e1000_poll: intr_status = %#08x\n", icr ); 709 710 /* Check status of transmitted packets 711 */ 712 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) { 713 714 tx_curr_desc = ( void * ) ( adapter->tx_base ) + 715 ( i * sizeof ( *adapter->tx_base ) ); 716 717 tx_status = tx_curr_desc->upper.data; 718 719 /* if the packet at tx_head is not owned by hardware it is for us */ 720 if ( ! ( tx_status & E1000_TXD_STAT_DD ) ) 721 break; 722 723 DBG ( "Sent packet. tx_head: %d tx_tail: %d tx_status: %#08x\n", 724 adapter->tx_head, adapter->tx_tail, tx_status ); 725 726 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | 727 E1000_TXD_STAT_TU ) ) { 728 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL ); 729 DBG ( "Error transmitting packet, tx_status: %#08x\n", 730 tx_status ); 731 } else { 732 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] ); 733 DBG ( "Success transmitting packet, tx_status: %#08x\n", 734 tx_status ); 735 } 736 737 /* Decrement count of used descriptors, clear this descriptor 738 */ 739 adapter->tx_fill_ctr--; 740 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) ); 741 742 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC; 743 } 744 745 /* Process received packets 746 */ 747 while ( 1 ) { 748 749 i = adapter->rx_curr; 750 751 rx_curr_desc = ( void * ) ( adapter->rx_base ) + 752 ( i * sizeof ( *adapter->rx_base ) ); 753 rx_status = rx_curr_desc->status; 754 755 DBG2 ( "Before DD Check RX_status: %#08x\n", rx_status ); 756 757 if ( ! ( rx_status & E1000_RXD_STAT_DD ) ) 758 break; 759 760 if ( adapter->rx_iobuf[i] == NULL ) 761 break; 762 763 DBG ( "RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, RCTL ) ); 764 765 rx_len = rx_curr_desc->length; 766 767 DBG ( "Received packet, rx_curr: %d rx_status: %#08x rx_len: %d\n", 768 i, rx_status, rx_len ); 769 770 rx_err = rx_curr_desc->errors; 771 772 iob_put ( adapter->rx_iobuf[i], rx_len ); 773 774 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) { 775 776 netdev_rx_err ( netdev, adapter->rx_iobuf[i], -EINVAL ); 777 DBG ( "e1000_poll: Corrupted packet received!" 778 " rx_err: %#08x\n", rx_err ); 779 } else { 780 /* Add this packet to the receive queue. */ 781 netdev_rx ( netdev, adapter->rx_iobuf[i] ); 782 } 783 adapter->rx_iobuf[i] = NULL; 784 785 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) ); 786 787 adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC; 788 } 789 e1000_refill_rx_ring(adapter); 790 } 791 792 /** 793 * e1000_irq - enable or Disable interrupts 794 * 795 * @v adapter e1000 adapter 796 * @v action requested interrupt action 797 **/ 798 static void 799 e1000_irq ( struct net_device *netdev, int enable ) 800 { 801 struct e1000_adapter *adapter = netdev_priv(netdev); 802 803 DBG ( "e1000_irq\n" ); 804 805 if ( enable ) 806 e1000_irq_enable ( adapter ); 807 else 808 e1000_irq_disable ( adapter ); 809 } 810 811 static struct net_device_operations e1000_operations; 812 813 /** 814 * e1000_probe - Initial configuration of e1000 NIC 815 * 816 * @v pci PCI device 817 * @v id PCI IDs 818 * 819 * @ret rc Return status code 820 **/ 821 static int 822 e1000_probe ( struct pci_device *pdev, 823 const struct pci_device_id *id __unused ) 824 { 825 int i, err; 826 struct net_device *netdev; 827 struct e1000_adapter *adapter; 828 unsigned long mmio_start, mmio_len; 829 unsigned long flash_start, flash_len; 830 831 DBG ( "e1000_probe\n" ); 832 833 err = -ENOMEM; 834 835 /* Allocate net device ( also allocates memory for netdev->priv 836 and makes netdev-priv point to it ) */ 837 netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) ); 838 if ( ! netdev ) 839 goto err_alloc_etherdev; 840 841 /* Associate e1000-specific network operations operations with 842 * generic network device layer */ 843 netdev_init ( netdev, &e1000_operations ); 844 845 /* Associate this network device with given PCI device */ 846 pci_set_drvdata ( pdev, netdev ); 847 netdev->dev = &pdev->dev; 848 849 /* Initialize driver private storage */ 850 adapter = netdev_priv ( netdev ); 851 memset ( adapter, 0, ( sizeof ( *adapter ) ) ); 852 853 adapter->hw.io_base = pdev->ioaddr; 854 adapter->ioaddr = pdev->ioaddr; 855 adapter->irqno = pdev->irq; 856 adapter->netdev = netdev; 857 adapter->pdev = pdev; 858 adapter->hw.back = adapter; 859 860 adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC; 861 adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC; 862 863 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 ); 864 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 ); 865 866 DBG ( "mmio_start: %#08lx\n", mmio_start ); 867 DBG ( "mmio_len: %#08lx\n", mmio_len ); 868 869 /* Fix up PCI device */ 870 adjust_pci_device ( pdev ); 871 872 err = -EIO; 873 874 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len ); 875 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr ); 876 877 if ( ! adapter->hw.hw_addr ) 878 goto err_ioremap; 879 880 /* setup the private structure */ 881 if ( ( err = e1000_sw_init ( adapter ) ) ) 882 goto err_sw_init; 883 884 DBG ( "adapter->hw.mac_type: %#08x\n", adapter->hw.mac_type ); 885 886 /* Flash BAR mapping must happen after e1000_sw_init 887 * because it depends on mac_type 888 */ 889 if ( ( adapter->hw.mac_type == e1000_ich8lan ) && ( pdev->ioaddr ) ) { 890 flash_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_1 ); 891 flash_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_1 ); 892 adapter->hw.flash_address = ioremap ( flash_start, flash_len ); 893 if ( ! adapter->hw.flash_address ) 894 goto err_flashmap; 895 } 896 897 /* initialize eeprom parameters */ 898 if ( e1000_init_eeprom_params ( &adapter->hw ) ) { 899 DBG ( "EEPROM initialization failed\n" ); 900 goto err_eeprom; 901 } 902 903 /* before reading the EEPROM, reset the controller to 904 * put the device in a known good starting state 905 */ 906 err = e1000_reset_hw ( &adapter->hw ); 907 if ( err < 0 ) { 908 DBG ( "Hardware Initialization Failed\n" ); 909 goto err_reset; 910 } 911 912 /* make sure the EEPROM is good */ 913 if ( e1000_validate_eeprom_checksum( &adapter->hw ) < 0 ) { 914 DBG ( "The EEPROM Checksum Is Not Valid\n" ); 915 goto err_eeprom; 916 } 917 918 /* copy the MAC address out of the EEPROM */ 919 if ( e1000_read_mac_addr ( &adapter->hw ) ) 920 DBG ( "EEPROM Read Error\n" ); 921 922 memcpy ( netdev->hw_addr, adapter->hw.mac_addr, ETH_ALEN ); 923 924 /* print bus type/speed/width info */ 925 { 926 struct e1000_hw *hw = &adapter->hw; 927 DBG ( "(PCI%s:%s:%s) ", 928 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" : 929 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")), 930 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 931 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" : 932 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" : 933 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" : 934 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"), 935 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" : 936 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" : 937 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" : 938 "32-bit")); 939 } 940 for (i = 0; i < 6; i++) 941 DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":"); 942 943 /* reset the hardware with the new settings */ 944 e1000_reset ( adapter ); 945 946 e1000_get_hw_control ( adapter ); 947 948 /* Mark as link up; we don't yet handle link state */ 949 netdev_link_up ( netdev ); 950 951 if ( ( err = register_netdev ( netdev ) ) != 0) 952 goto err_register; 953 954 DBG ( "e1000_probe succeeded!\n" ); 955 956 /* No errors, return success */ 957 return 0; 958 959 /* Error return paths */ 960 err_reset: 961 err_register: 962 err_eeprom: 963 if ( ! e1000_check_phy_reset_block ( &adapter->hw ) ) 964 e1000_phy_hw_reset ( &adapter->hw ); 965 if ( adapter->hw.flash_address ) 966 iounmap ( adapter->hw.flash_address ); 967 err_flashmap: 968 err_sw_init: 969 iounmap ( adapter->hw.hw_addr ); 970 err_ioremap: 971 netdev_put ( netdev ); 972 err_alloc_etherdev: 973 return err; 974 } 975 976 /** 977 * e1000_remove - Device Removal Routine 978 * 979 * @v pdev PCI device information struct 980 * 981 **/ 982 static void 983 e1000_remove ( struct pci_device *pdev ) 984 { 985 struct net_device *netdev = pci_get_drvdata ( pdev ); 986 struct e1000_adapter *adapter = netdev_priv ( netdev ); 987 988 DBG ( "e1000_remove\n" ); 989 990 if ( adapter->hw.flash_address ) 991 iounmap ( adapter->hw.flash_address ); 992 if ( adapter->hw.hw_addr ) 993 iounmap ( adapter->hw.hw_addr ); 994 995 unregister_netdev ( netdev ); 996 e1000_reset_hw ( &adapter->hw ); 997 netdev_nullify ( netdev ); 998 netdev_put ( netdev ); 999 } 1000 1001 /** 1002 * e1000_open - Called when a network interface is made active 1003 * 1004 * @v netdev network interface device structure 1005 * @ret rc Return status code, 0 on success, negative value on failure 1006 * 1007 **/ 1008 static int 1009 e1000_open ( struct net_device *netdev ) 1010 { 1011 struct e1000_adapter *adapter = netdev_priv(netdev); 1012 int err; 1013 1014 DBG ( "e1000_open\n" ); 1015 1016 /* allocate transmit descriptors */ 1017 err = e1000_setup_tx_resources ( adapter ); 1018 if ( err ) { 1019 DBG ( "Error setting up TX resources!\n" ); 1020 goto err_setup_tx; 1021 } 1022 1023 /* allocate receive descriptors */ 1024 err = e1000_setup_rx_resources ( adapter ); 1025 if ( err ) { 1026 DBG ( "Error setting up RX resources!\n" ); 1027 goto err_setup_rx; 1028 } 1029 1030 e1000_configure_tx ( adapter ); 1031 1032 e1000_configure_rx ( adapter ); 1033 1034 DBG ( "RXDCTL: %#08x\n", E1000_READ_REG ( &adapter->hw, RXDCTL ) ); 1035 1036 return 0; 1037 1038 err_setup_rx: 1039 e1000_free_tx_resources ( adapter ); 1040 err_setup_tx: 1041 e1000_reset ( adapter ); 1042 1043 return err; 1044 } 1045 1046 /** e1000 net device operations */ 1047 static struct net_device_operations e1000_operations = { 1048 .open = e1000_open, 1049 .close = e1000_close, 1050 .transmit = e1000_transmit, 1051 .poll = e1000_poll, 1052 .irq = e1000_irq, 1053 }; 1054 1055 int32_t 1056 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 1057 { 1058 struct e1000_adapter *adapter = hw->back; 1059 uint16_t cap_offset; 1060 1061 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 1062 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 1063 if (!cap_offset) 1064 return -E1000_ERR_CONFIG; 1065 1066 pci_read_config_word(adapter->pdev, cap_offset + reg, value); 1067 1068 return 0; 1069 } 1070 1071 void 1072 e1000_pci_clear_mwi ( struct e1000_hw *hw ) 1073 { 1074 struct e1000_adapter *adapter = hw->back; 1075 1076 pci_write_config_word ( adapter->pdev, PCI_COMMAND, 1077 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE ); 1078 } 1079 1080 void 1081 e1000_pci_set_mwi ( struct e1000_hw *hw ) 1082 { 1083 struct e1000_adapter *adapter = hw->back; 1084 1085 pci_write_config_word ( adapter->pdev, PCI_COMMAND, hw->pci_cmd_word ); 1086 } 1087 1088 void 1089 e1000_read_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value ) 1090 { 1091 struct e1000_adapter *adapter = hw->back; 1092 1093 pci_read_config_word ( adapter->pdev, reg, value ); 1094 } 1095 1096 void 1097 e1000_write_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value ) 1098 { 1099 struct e1000_adapter *adapter = hw->back; 1100 1101 pci_write_config_word ( adapter->pdev, reg, *value ); 1102 } 1103 1104 void 1105 e1000_io_write ( struct e1000_hw *hw __unused, unsigned long port, uint32_t value ) 1106 { 1107 outl ( value, port ); 1108 } 1109 1110 static struct pci_device_id e1000_nics[] = { 1111 PCI_ROM(0x8086, 0x1000, "e1000-0x1000", "e1000-0x1000", 0), 1112 PCI_ROM(0x8086, 0x1001, "e1000-0x1001", "e1000-0x1001", 0), 1113 PCI_ROM(0x8086, 0x1004, "e1000-0x1004", "e1000-0x1004", 0), 1114 PCI_ROM(0x8086, 0x1008, "e1000-0x1008", "e1000-0x1008", 0), 1115 PCI_ROM(0x8086, 0x1009, "e1000-0x1009", "e1000-0x1009", 0), 1116 PCI_ROM(0x8086, 0x100c, "e1000-0x100c", "e1000-0x100c", 0), 1117 PCI_ROM(0x8086, 0x100d, "e1000-0x100d", "e1000-0x100d", 0), 1118 PCI_ROM(0x8086, 0x100e, "e1000-0x100e", "e1000-0x100e", 0), 1119 PCI_ROM(0x8086, 0x100f, "e1000-0x100f", "e1000-0x100f", 0), 1120 PCI_ROM(0x8086, 0x1010, "e1000-0x1010", "e1000-0x1010", 0), 1121 PCI_ROM(0x8086, 0x1011, "e1000-0x1011", "e1000-0x1011", 0), 1122 PCI_ROM(0x8086, 0x1012, "e1000-0x1012", "e1000-0x1012", 0), 1123 PCI_ROM(0x8086, 0x1013, "e1000-0x1013", "e1000-0x1013", 0), 1124 PCI_ROM(0x8086, 0x1014, "e1000-0x1014", "e1000-0x1014", 0), 1125 PCI_ROM(0x8086, 0x1015, "e1000-0x1015", "e1000-0x1015", 0), 1126 PCI_ROM(0x8086, 0x1016, "e1000-0x1016", "e1000-0x1016", 0), 1127 PCI_ROM(0x8086, 0x1017, "e1000-0x1017", "e1000-0x1017", 0), 1128 PCI_ROM(0x8086, 0x1018, "e1000-0x1018", "e1000-0x1018", 0), 1129 PCI_ROM(0x8086, 0x1019, "e1000-0x1019", "e1000-0x1019", 0), 1130 PCI_ROM(0x8086, 0x101a, "e1000-0x101a", "e1000-0x101a", 0), 1131 PCI_ROM(0x8086, 0x101d, "e1000-0x101d", "e1000-0x101d", 0), 1132 PCI_ROM(0x8086, 0x101e, "e1000-0x101e", "e1000-0x101e", 0), 1133 PCI_ROM(0x8086, 0x1026, "e1000-0x1026", "e1000-0x1026", 0), 1134 PCI_ROM(0x8086, 0x1027, "e1000-0x1027", "e1000-0x1027", 0), 1135 PCI_ROM(0x8086, 0x1028, "e1000-0x1028", "e1000-0x1028", 0), 1136 PCI_ROM(0x8086, 0x1049, "e1000-0x1049", "e1000-0x1049", 0), 1137 PCI_ROM(0x8086, 0x104a, "e1000-0x104a", "e1000-0x104a", 0), 1138 PCI_ROM(0x8086, 0x104b, "e1000-0x104b", "e1000-0x104b", 0), 1139 PCI_ROM(0x8086, 0x104c, "e1000-0x104c", "e1000-0x104c", 0), 1140 PCI_ROM(0x8086, 0x104d, "e1000-0x104d", "e1000-0x104d", 0), 1141 PCI_ROM(0x8086, 0x105e, "e1000-0x105e", "e1000-0x105e", 0), 1142 PCI_ROM(0x8086, 0x105f, "e1000-0x105f", "e1000-0x105f", 0), 1143 PCI_ROM(0x8086, 0x1060, "e1000-0x1060", "e1000-0x1060", 0), 1144 PCI_ROM(0x8086, 0x1075, "e1000-0x1075", "e1000-0x1075", 0), 1145 PCI_ROM(0x8086, 0x1076, "e1000-0x1076", "e1000-0x1076", 0), 1146 PCI_ROM(0x8086, 0x1077, "e1000-0x1077", "e1000-0x1077", 0), 1147 PCI_ROM(0x8086, 0x1078, "e1000-0x1078", "e1000-0x1078", 0), 1148 PCI_ROM(0x8086, 0x1079, "e1000-0x1079", "e1000-0x1079", 0), 1149 PCI_ROM(0x8086, 0x107a, "e1000-0x107a", "e1000-0x107a", 0), 1150 PCI_ROM(0x8086, 0x107b, "e1000-0x107b", "e1000-0x107b", 0), 1151 PCI_ROM(0x8086, 0x107c, "e1000-0x107c", "e1000-0x107c", 0), 1152 PCI_ROM(0x8086, 0x107d, "e1000-0x107d", "e1000-0x107d", 0), 1153 PCI_ROM(0x8086, 0x107e, "e1000-0x107e", "e1000-0x107e", 0), 1154 PCI_ROM(0x8086, 0x107f, "e1000-0x107f", "e1000-0x107f", 0), 1155 PCI_ROM(0x8086, 0x108a, "e1000-0x108a", "e1000-0x108a", 0), 1156 PCI_ROM(0x8086, 0x108b, "e1000-0x108b", "e1000-0x108b", 0), 1157 PCI_ROM(0x8086, 0x108c, "e1000-0x108c", "e1000-0x108c", 0), 1158 PCI_ROM(0x8086, 0x1096, "e1000-0x1096", "e1000-0x1096", 0), 1159 PCI_ROM(0x8086, 0x1098, "e1000-0x1098", "e1000-0x1098", 0), 1160 PCI_ROM(0x8086, 0x1099, "e1000-0x1099", "e1000-0x1099", 0), 1161 PCI_ROM(0x8086, 0x109a, "e1000-0x109a", "e1000-0x109a", 0), 1162 PCI_ROM(0x8086, 0x10a4, "e1000-0x10a4", "e1000-0x10a4", 0), 1163 PCI_ROM(0x8086, 0x10a5, "e1000-0x10a5", "e1000-0x10a5", 0), 1164 PCI_ROM(0x8086, 0x10b5, "e1000-0x10b5", "e1000-0x10b5", 0), 1165 PCI_ROM(0x8086, 0x10b9, "e1000-0x10b9", "e1000-0x10b9", 0), 1166 PCI_ROM(0x8086, 0x10ba, "e1000-0x10ba", "e1000-0x10ba", 0), 1167 PCI_ROM(0x8086, 0x10bb, "e1000-0x10bb", "e1000-0x10bb", 0), 1168 PCI_ROM(0x8086, 0x10bc, "e1000-0x10bc", "e1000-0x10bc", 0), 1169 PCI_ROM(0x8086, 0x10c4, "e1000-0x10c4", "e1000-0x10c4", 0), 1170 PCI_ROM(0x8086, 0x10c5, "e1000-0x10c5", "e1000-0x10c5", 0), 1171 PCI_ROM(0x8086, 0x10c9, "e1000-0x10c9", "e1000-0x10c9", 0), 1172 PCI_ROM(0x8086, 0x10d9, "e1000-0x10d9", "e1000-0x10d9", 0), 1173 PCI_ROM(0x8086, 0x10da, "e1000-0x10da", "e1000-0x10da", 0), 1174 }; 1175 1176 struct pci_driver e1000_driver __pci_driver = { 1177 .ids = e1000_nics, 1178 .id_count = (sizeof (e1000_nics) / sizeof (e1000_nics[0])), 1179 .probe = e1000_probe, 1180 .remove = e1000_remove, 1181 }; 1182 1183 /* 1184 * Local variables: 1185 * c-basic-offset: 8 1186 * c-indent-level: 8 1187 * tab-width: 8 1188 * End: 1189 */ 1190
