1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics (at) intel.com> 24 e1000-devel Mailing List <e1000-devel (at) lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 FILE_LICENCE ( GPL2_ONLY ); 30 31 /* e1000_hw.h 32 * Structures, enums, and macros for the MAC 33 */ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 40 41 /* Forward declarations of structures used by the shared code */ 42 struct e1000_hw; 43 struct e1000_hw_stats; 44 45 /* Enumerated types specific to the e1000 hardware */ 46 /* Media Access Controlers */ 47 typedef enum { 48 e1000_undefined = 0, 49 e1000_82542_rev2_0, 50 e1000_82542_rev2_1, 51 e1000_82543, 52 e1000_82544, 53 e1000_82540, 54 e1000_82545, 55 e1000_82545_rev_3, 56 e1000_82546, 57 e1000_82546_rev_3, 58 e1000_82541, 59 e1000_82541_rev_2, 60 e1000_82547, 61 e1000_82547_rev_2, 62 e1000_82571, 63 e1000_82572, 64 e1000_82573, 65 e1000_80003es2lan, 66 e1000_ich8lan, 67 e1000_82576, 68 e1000_num_macs 69 } e1000_mac_type; 70 71 typedef enum { 72 e1000_eeprom_uninitialized = 0, 73 e1000_eeprom_spi, 74 e1000_eeprom_microwire, 75 e1000_eeprom_flash, 76 e1000_eeprom_ich8, 77 e1000_eeprom_none, /* No NVM support */ 78 e1000_num_eeprom_types 79 } e1000_eeprom_type; 80 81 /* Media Types */ 82 typedef enum { 83 e1000_media_type_copper = 0, 84 e1000_media_type_fiber = 1, 85 e1000_media_type_internal_serdes = 2, 86 e1000_num_media_types 87 } e1000_media_type; 88 89 typedef enum { 90 e1000_10_half = 0, 91 e1000_10_full = 1, 92 e1000_100_half = 2, 93 e1000_100_full = 3 94 } e1000_speed_duplex_type; 95 96 /* Flow Control Settings */ 97 typedef enum { 98 E1000_FC_NONE = 0, 99 E1000_FC_RX_PAUSE = 1, 100 E1000_FC_TX_PAUSE = 2, 101 E1000_FC_FULL = 3, 102 E1000_FC_DEFAULT = 0xFF 103 } e1000_fc_type; 104 105 struct e1000_shadow_ram { 106 uint16_t eeprom_word; 107 boolean_t modified; 108 }; 109 110 /* PCI bus types */ 111 typedef enum { 112 e1000_bus_type_unknown = 0, 113 e1000_bus_type_pci, 114 e1000_bus_type_pcix, 115 e1000_bus_type_pci_express, 116 e1000_bus_type_reserved 117 } e1000_bus_type; 118 119 /* PCI bus speeds */ 120 typedef enum { 121 e1000_bus_speed_unknown = 0, 122 e1000_bus_speed_33, 123 e1000_bus_speed_66, 124 e1000_bus_speed_100, 125 e1000_bus_speed_120, 126 e1000_bus_speed_133, 127 e1000_bus_speed_2500, 128 e1000_bus_speed_reserved 129 } e1000_bus_speed; 130 131 /* PCI bus widths */ 132 typedef enum { 133 e1000_bus_width_unknown = 0, 134 /* These PCIe values should literally match the possible return values 135 * from config space */ 136 e1000_bus_width_pciex_1 = 1, 137 e1000_bus_width_pciex_2 = 2, 138 e1000_bus_width_pciex_4 = 4, 139 e1000_bus_width_32, 140 e1000_bus_width_64, 141 e1000_bus_width_reserved 142 } e1000_bus_width; 143 144 /* PHY status info structure and supporting enums */ 145 typedef enum { 146 e1000_cable_length_50 = 0, 147 e1000_cable_length_50_80, 148 e1000_cable_length_80_110, 149 e1000_cable_length_110_140, 150 e1000_cable_length_140, 151 e1000_cable_length_undefined = 0xFF 152 } e1000_cable_length; 153 154 typedef enum { 155 e1000_gg_cable_length_60 = 0, 156 e1000_gg_cable_length_60_115 = 1, 157 e1000_gg_cable_length_115_150 = 2, 158 e1000_gg_cable_length_150 = 4 159 } e1000_gg_cable_length; 160 161 typedef enum { 162 e1000_igp_cable_length_10 = 10, 163 e1000_igp_cable_length_20 = 20, 164 e1000_igp_cable_length_30 = 30, 165 e1000_igp_cable_length_40 = 40, 166 e1000_igp_cable_length_50 = 50, 167 e1000_igp_cable_length_60 = 60, 168 e1000_igp_cable_length_70 = 70, 169 e1000_igp_cable_length_80 = 80, 170 e1000_igp_cable_length_90 = 90, 171 e1000_igp_cable_length_100 = 100, 172 e1000_igp_cable_length_110 = 110, 173 e1000_igp_cable_length_115 = 115, 174 e1000_igp_cable_length_120 = 120, 175 e1000_igp_cable_length_130 = 130, 176 e1000_igp_cable_length_140 = 140, 177 e1000_igp_cable_length_150 = 150, 178 e1000_igp_cable_length_160 = 160, 179 e1000_igp_cable_length_170 = 170, 180 e1000_igp_cable_length_180 = 180 181 } e1000_igp_cable_length; 182 183 typedef enum { 184 e1000_10bt_ext_dist_enable_normal = 0, 185 e1000_10bt_ext_dist_enable_lower, 186 e1000_10bt_ext_dist_enable_undefined = 0xFF 187 } e1000_10bt_ext_dist_enable; 188 189 typedef enum { 190 e1000_rev_polarity_normal = 0, 191 e1000_rev_polarity_reversed, 192 e1000_rev_polarity_undefined = 0xFF 193 } e1000_rev_polarity; 194 195 typedef enum { 196 e1000_downshift_normal = 0, 197 e1000_downshift_activated, 198 e1000_downshift_undefined = 0xFF 199 } e1000_downshift; 200 201 typedef enum { 202 e1000_smart_speed_default = 0, 203 e1000_smart_speed_on, 204 e1000_smart_speed_off 205 } e1000_smart_speed; 206 207 typedef enum { 208 e1000_polarity_reversal_enabled = 0, 209 e1000_polarity_reversal_disabled, 210 e1000_polarity_reversal_undefined = 0xFF 211 } e1000_polarity_reversal; 212 213 typedef enum { 214 e1000_auto_x_mode_manual_mdi = 0, 215 e1000_auto_x_mode_manual_mdix, 216 e1000_auto_x_mode_auto1, 217 e1000_auto_x_mode_auto2, 218 e1000_auto_x_mode_undefined = 0xFF 219 } e1000_auto_x_mode; 220 221 typedef enum { 222 e1000_1000t_rx_status_not_ok = 0, 223 e1000_1000t_rx_status_ok, 224 e1000_1000t_rx_status_undefined = 0xFF 225 } e1000_1000t_rx_status; 226 227 typedef enum { 228 e1000_phy_m88 = 0, 229 e1000_phy_igp, 230 e1000_phy_igp_2, 231 e1000_phy_gg82563, 232 e1000_phy_igp_3, 233 e1000_phy_ife, 234 e1000_phy_undefined = 0xFF 235 } e1000_phy_type; 236 237 typedef enum { 238 e1000_ms_hw_default = 0, 239 e1000_ms_force_master, 240 e1000_ms_force_slave, 241 e1000_ms_auto 242 } e1000_ms_type; 243 244 typedef enum { 245 e1000_ffe_config_enabled = 0, 246 e1000_ffe_config_active, 247 e1000_ffe_config_blocked 248 } e1000_ffe_config; 249 250 typedef enum { 251 e1000_dsp_config_disabled = 0, 252 e1000_dsp_config_enabled, 253 e1000_dsp_config_activated, 254 e1000_dsp_config_undefined = 0xFF 255 } e1000_dsp_config; 256 257 struct e1000_phy_info { 258 e1000_cable_length cable_length; 259 e1000_10bt_ext_dist_enable extended_10bt_distance; 260 e1000_rev_polarity cable_polarity; 261 e1000_downshift downshift; 262 e1000_polarity_reversal polarity_correction; 263 e1000_auto_x_mode mdix_mode; 264 e1000_1000t_rx_status local_rx; 265 e1000_1000t_rx_status remote_rx; 266 }; 267 268 struct e1000_phy_stats { 269 uint32_t idle_errors; 270 uint32_t receive_errors; 271 }; 272 273 struct e1000_eeprom_info { 274 e1000_eeprom_type type; 275 uint16_t word_size; 276 uint16_t opcode_bits; 277 uint16_t address_bits; 278 uint16_t delay_usec; 279 uint16_t page_size; 280 boolean_t use_eerd; 281 boolean_t use_eewr; 282 }; 283 284 /* Flex ASF Information */ 285 #define E1000_HOST_IF_MAX_SIZE 2048 286 287 typedef enum { 288 e1000_byte_align = 0, 289 e1000_word_align = 1, 290 e1000_dword_align = 2 291 } e1000_align_type; 292 293 294 295 /* Error Codes */ 296 #define E1000_SUCCESS 0 297 #define E1000_ERR_EEPROM 1 298 #define E1000_ERR_PHY 2 299 #define E1000_ERR_CONFIG 3 300 #define E1000_ERR_PARAM 4 301 #define E1000_ERR_MAC_TYPE 5 302 #define E1000_ERR_PHY_TYPE 6 303 #define E1000_ERR_RESET 9 304 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 305 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 306 #define E1000_BLK_PHY_RESET 12 307 #define E1000_ERR_SWFW_SYNC 13 308 309 #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ 310 (((_value) & 0xff00) >> 8)) 311 312 /* Function prototypes */ 313 /* Initialization */ 314 int32_t e1000_reset_hw(struct e1000_hw *hw); 315 int32_t e1000_init_hw(struct e1000_hw *hw); 316 int32_t e1000_set_mac_type(struct e1000_hw *hw); 317 void e1000_set_media_type(struct e1000_hw *hw); 318 319 /* Link Configuration */ 320 int32_t e1000_setup_link(struct e1000_hw *hw); 321 int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw); 322 void e1000_config_collision_dist(struct e1000_hw *hw); 323 int32_t e1000_check_for_link(struct e1000_hw *hw); 324 int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex); 325 int32_t e1000_force_mac_fc(struct e1000_hw *hw); 326 327 /* PHY */ 328 int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 329 int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 330 int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 331 int32_t e1000_phy_reset(struct e1000_hw *hw); 332 int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 333 int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 334 335 void e1000_phy_powerdown_workaround(struct e1000_hw *hw); 336 337 /* EEPROM Functions */ 338 int32_t e1000_init_eeprom_params(struct e1000_hw *hw); 339 340 /* MNG HOST IF functions */ 341 uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); 342 343 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 344 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 345 346 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 347 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 348 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 349 #define E1000_MNG_IAMT_MODE 0x3 350 #define E1000_MNG_ICH_IAMT_MODE 0x2 351 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 352 353 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 354 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ 355 #define E1000_VFTA_ENTRY_SHIFT 0x5 356 #define E1000_VFTA_ENTRY_MASK 0x7F 357 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 358 359 struct e1000_host_mng_command_header { 360 uint8_t command_id; 361 uint8_t checksum; 362 uint16_t reserved1; 363 uint16_t reserved2; 364 uint16_t command_length; 365 }; 366 367 struct e1000_host_mng_command_info { 368 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 369 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 370 }; 371 #ifdef __BIG_ENDIAN 372 struct e1000_host_mng_dhcp_cookie{ 373 uint32_t signature; 374 uint16_t vlan_id; 375 uint8_t reserved0; 376 uint8_t status; 377 uint32_t reserved1; 378 uint8_t checksum; 379 uint8_t reserved3; 380 uint16_t reserved2; 381 }; 382 #else 383 struct e1000_host_mng_dhcp_cookie{ 384 uint32_t signature; 385 uint8_t status; 386 uint8_t reserved0; 387 uint16_t vlan_id; 388 uint32_t reserved1; 389 uint16_t reserved2; 390 uint8_t reserved3; 391 uint8_t checksum; 392 }; 393 #endif 394 395 int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, 396 uint16_t length); 397 boolean_t e1000_check_mng_mode(struct e1000_hw *hw); 398 boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 399 int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 400 int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 401 int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 402 int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 403 int32_t e1000_read_mac_addr(struct e1000_hw * hw); 404 405 /* Filters (multicast, vlan, receive) */ 406 uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr); 407 void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value); 408 void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index); 409 void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value); 410 411 /* LED functions */ 412 int32_t e1000_setup_led(struct e1000_hw *hw); 413 int32_t e1000_cleanup_led(struct e1000_hw *hw); 414 int32_t e1000_led_on(struct e1000_hw *hw); 415 int32_t e1000_led_off(struct e1000_hw *hw); 416 int32_t e1000_blink_led_start(struct e1000_hw *hw); 417 418 /* Adaptive IFS Functions */ 419 420 /* Everything else */ 421 void e1000_reset_adaptive(struct e1000_hw *hw); 422 void e1000_update_adaptive(struct e1000_hw *hw); 423 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); 424 void e1000_get_bus_info(struct e1000_hw *hw); 425 void e1000_pci_set_mwi(struct e1000_hw *hw); 426 void e1000_pci_clear_mwi(struct e1000_hw *hw); 427 void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); 428 void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); 429 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value); 430 /* Port I/O is only supported on 82544 and newer */ 431 void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); 432 int32_t e1000_disable_pciex_master(struct e1000_hw *hw); 433 int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 434 435 436 #define E1000_READ_REG_IO(a, reg) \ 437 e1000_read_reg_io((a), E1000_##reg) 438 #define E1000_WRITE_REG_IO(a, reg, val) \ 439 e1000_write_reg_io((a), E1000_##reg, val) 440 441 /* PCI Device IDs */ 442 #define E1000_DEV_ID_82542 0x1000 443 #define E1000_DEV_ID_82543GC_FIBER 0x1001 444 #define E1000_DEV_ID_82543GC_COPPER 0x1004 445 #define E1000_DEV_ID_82544EI_COPPER 0x1008 446 #define E1000_DEV_ID_82544EI_FIBER 0x1009 447 #define E1000_DEV_ID_82544GC_COPPER 0x100C 448 #define E1000_DEV_ID_82544GC_LOM 0x100D 449 #define E1000_DEV_ID_82540EM 0x100E 450 #define E1000_DEV_ID_82540EM_LOM 0x1015 451 #define E1000_DEV_ID_82540EP_LOM 0x1016 452 #define E1000_DEV_ID_82540EP 0x1017 453 #define E1000_DEV_ID_82540EP_LP 0x101E 454 #define E1000_DEV_ID_82545EM_COPPER 0x100F 455 #define E1000_DEV_ID_82545EM_FIBER 0x1011 456 #define E1000_DEV_ID_82545GM_COPPER 0x1026 457 #define E1000_DEV_ID_82545GM_FIBER 0x1027 458 #define E1000_DEV_ID_82545GM_SERDES 0x1028 459 #define E1000_DEV_ID_82546EB_COPPER 0x1010 460 #define E1000_DEV_ID_82546EB_FIBER 0x1012 461 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 462 #define E1000_DEV_ID_82541EI 0x1013 463 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 464 #define E1000_DEV_ID_82541ER_LOM 0x1014 465 #define E1000_DEV_ID_82541ER 0x1078 466 #define E1000_DEV_ID_82547GI 0x1075 467 #define E1000_DEV_ID_82541GI 0x1076 468 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 469 #define E1000_DEV_ID_82541GI_LF 0x107C 470 #define E1000_DEV_ID_82546GB_COPPER 0x1079 471 #define E1000_DEV_ID_82546GB_FIBER 0x107A 472 #define E1000_DEV_ID_82546GB_SERDES 0x107B 473 #define E1000_DEV_ID_82546GB_PCIE 0x108A 474 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 475 #define E1000_DEV_ID_82547EI 0x1019 476 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 477 #define E1000_DEV_ID_82571EB_COPPER 0x105E 478 #define E1000_DEV_ID_82571EB_FIBER 0x105F 479 #define E1000_DEV_ID_82571EB_SERDES 0x1060 480 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 481 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 482 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC 483 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 484 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 485 #define E1000_DEV_ID_82572EI_COPPER 0x107D 486 #define E1000_DEV_ID_82572EI_FIBER 0x107E 487 #define E1000_DEV_ID_82572EI_SERDES 0x107F 488 #define E1000_DEV_ID_82572EI 0x10B9 489 #define E1000_DEV_ID_82573E 0x108B 490 #define E1000_DEV_ID_82573E_IAMT 0x108C 491 #define E1000_DEV_ID_82573L 0x109A 492 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 493 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 494 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 495 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 496 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 497 498 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 499 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 500 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 501 #define E1000_DEV_ID_ICH8_IFE 0x104C 502 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 503 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 504 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 505 506 #define E1000_DEV_ID_82576 0x10C9 507 508 #define NODE_ADDRESS_SIZE 6 509 #define ETH_LENGTH_OF_ADDRESS 6 510 511 /* MAC decode size is 128K - This is the size of BAR0 */ 512 #define MAC_DECODE_SIZE (128 * 1024) 513 514 #define E1000_82542_2_0_REV_ID 2 515 #define E1000_82542_2_1_REV_ID 3 516 #define E1000_REVISION_0 0 517 #define E1000_REVISION_1 1 518 #define E1000_REVISION_2 2 519 #define E1000_REVISION_3 3 520 521 #define SPEED_10 10 522 #define SPEED_100 100 523 #define SPEED_1000 1000 524 #define HALF_DUPLEX 1 525 #define FULL_DUPLEX 2 526 527 /* The sizes (in bytes) of a ethernet packet */ 528 #define ENET_HEADER_SIZE 14 529 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 530 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 531 #define ETHERNET_FCS_SIZE 4 532 #define MAXIMUM_ETHERNET_PACKET_SIZE \ 533 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 534 #define MINIMUM_ETHERNET_PACKET_SIZE \ 535 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 536 #define CRC_LENGTH ETHERNET_FCS_SIZE 537 #define MAX_JUMBO_FRAME_SIZE 0x3F00 538 539 540 /* 802.1q VLAN Packet Sizes */ 541 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 542 543 /* Ethertype field values */ 544 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 545 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 546 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 547 548 /* Packet Header defines */ 549 #define IP_PROTOCOL_TCP 6 550 #define IP_PROTOCOL_UDP 0x11 551 552 /* This defines the bits that are set in the Interrupt Mask 553 * Set/Read Register. Each bit is documented below: 554 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 555 * o RXSEQ = Receive Sequence Error 556 */ 557 #define POLL_IMS_ENABLE_MASK ( \ 558 E1000_IMS_RXDMT0 | \ 559 E1000_IMS_RXSEQ) 560 561 /* This defines the bits that are set in the Interrupt Mask 562 * Set/Read Register. Each bit is documented below: 563 * o RXT0 = Receiver Timer Interrupt (ring 0) 564 * o TXDW = Transmit Descriptor Written Back 565 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 566 * o RXSEQ = Receive Sequence Error 567 * o LSC = Link Status Change 568 */ 569 #define IMS_ENABLE_MASK ( \ 570 E1000_IMS_RXT0 | \ 571 E1000_IMS_TXDW | \ 572 E1000_IMS_RXDMT0 | \ 573 E1000_IMS_RXSEQ | \ 574 E1000_IMS_LSC | \ 575 E1000_IMS_DOUTSYNC) 576 577 /* Additional interrupts need to be handled for e1000_ich8lan: 578 DSW = The FW changed the status of the DISSW bit in FWSM 579 PHYINT = The LAN connected device generates an interrupt 580 EPRST = Manageability reset event */ 581 #define IMS_ICH8LAN_ENABLE_MASK (\ 582 E1000_IMS_DSW | \ 583 E1000_IMS_PHYINT | \ 584 E1000_IMS_EPRST) 585 586 /* Number of high/low register pairs in the RAR. The RAR (Receive Address 587 * Registers) holds the directed and multicast addresses that we monitor. We 588 * reserve one of these spots for our directed address, allowing us room for 589 * E1000_RAR_ENTRIES - 1 multicast addresses. 590 */ 591 #define E1000_RAR_ENTRIES 15 592 593 #define E1000_RAR_ENTRIES_ICH8LAN 6 594 595 #define MIN_NUMBER_OF_DESCRIPTORS 8 596 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 597 598 /* Receive Descriptor */ 599 struct e1000_rx_desc { 600 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 601 uint16_t length; /* Length of data DMAed into data buffer */ 602 uint16_t csum; /* Packet checksum */ 603 uint8_t status; /* Descriptor status */ 604 uint8_t errors; /* Descriptor Errors */ 605 uint16_t special; 606 }; 607 608 /* Receive Descriptor - Extended */ 609 union e1000_rx_desc_extended { 610 struct { 611 uint64_t buffer_addr; 612 uint64_t reserved; 613 } read; 614 struct { 615 struct { 616 uint32_t mrq; /* Multiple Rx Queues */ 617 union { 618 uint32_t rss; /* RSS Hash */ 619 struct { 620 uint16_t ip_id; /* IP id */ 621 uint16_t csum; /* Packet Checksum */ 622 } csum_ip; 623 } hi_dword; 624 } lower; 625 struct { 626 uint32_t status_error; /* ext status/error */ 627 uint16_t length; 628 uint16_t vlan; /* VLAN tag */ 629 } upper; 630 } wb; /* writeback */ 631 }; 632 633 #define MAX_PS_BUFFERS 4 634 /* Receive Descriptor - Packet Split */ 635 union e1000_rx_desc_packet_split { 636 struct { 637 /* one buffer for protocol header(s), three data buffers */ 638 uint64_t buffer_addr[MAX_PS_BUFFERS]; 639 } read; 640 struct { 641 struct { 642 uint32_t mrq; /* Multiple Rx Queues */ 643 union { 644 uint32_t rss; /* RSS Hash */ 645 struct { 646 uint16_t ip_id; /* IP id */ 647 uint16_t csum; /* Packet Checksum */ 648 } csum_ip; 649 } hi_dword; 650 } lower; 651 struct { 652 uint32_t status_error; /* ext status/error */ 653 uint16_t length0; /* length of buffer 0 */ 654 uint16_t vlan; /* VLAN tag */ 655 } middle; 656 struct { 657 uint16_t header_status; 658 uint16_t length[3]; /* length of buffers 1-3 */ 659 } upper; 660 uint64_t reserved; 661 } wb; /* writeback */ 662 }; 663 664 /* Receive Decriptor bit definitions */ 665 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 666 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 667 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 668 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 669 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 670 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 671 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 672 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 673 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 674 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 675 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 676 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 677 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 678 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 679 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 680 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 681 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 682 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 683 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 684 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 685 #define E1000_RXD_SPC_PRI_SHIFT 13 686 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 687 #define E1000_RXD_SPC_CFI_SHIFT 12 688 689 #define E1000_RXDEXT_STATERR_CE 0x01000000 690 #define E1000_RXDEXT_STATERR_SE 0x02000000 691 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 692 #define E1000_RXDEXT_STATERR_CXE 0x10000000 693 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 694 #define E1000_RXDEXT_STATERR_IPE 0x40000000 695 #define E1000_RXDEXT_STATERR_RXE 0x80000000 696 697 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 698 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 699 700 /* mask to determine if packets should be dropped due to frame errors */ 701 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 702 E1000_RXD_ERR_CE | \ 703 E1000_RXD_ERR_SE | \ 704 E1000_RXD_ERR_SEQ | \ 705 E1000_RXD_ERR_CXE | \ 706 E1000_RXD_ERR_RXE) 707 708 709 /* Same mask, but for extended and packet split descriptors */ 710 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 711 E1000_RXDEXT_STATERR_CE | \ 712 E1000_RXDEXT_STATERR_SE | \ 713 E1000_RXDEXT_STATERR_SEQ | \ 714 E1000_RXDEXT_STATERR_CXE | \ 715 E1000_RXDEXT_STATERR_RXE) 716 717 718 /* Transmit Descriptor */ 719 struct e1000_tx_desc { 720 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 721 union { 722 uint32_t data; 723 struct { 724 uint16_t length; /* Data buffer length */ 725 uint8_t cso; /* Checksum offset */ 726 uint8_t cmd; /* Descriptor control */ 727 } flags; 728 } lower; 729 union { 730 uint32_t data; 731 struct { 732 uint8_t status; /* Descriptor status */ 733 uint8_t css; /* Checksum start */ 734 uint16_t special; 735 } fields; 736 } upper; 737 }; 738 739 /* Transmit Descriptor bit definitions */ 740 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 741 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 742 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 743 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 744 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 745 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 746 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 747 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 748 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 749 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 750 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 751 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 752 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 753 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 754 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 755 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 756 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 757 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 758 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 759 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 760 761 /* Offload Context Descriptor */ 762 struct e1000_context_desc { 763 union { 764 uint32_t ip_config; 765 struct { 766 uint8_t ipcss; /* IP checksum start */ 767 uint8_t ipcso; /* IP checksum offset */ 768 uint16_t ipcse; /* IP checksum end */ 769 } ip_fields; 770 } lower_setup; 771 union { 772 uint32_t tcp_config; 773 struct { 774 uint8_t tucss; /* TCP checksum start */ 775 uint8_t tucso; /* TCP checksum offset */ 776 uint16_t tucse; /* TCP checksum end */ 777 } tcp_fields; 778 } upper_setup; 779 uint32_t cmd_and_length; /* */ 780 union { 781 uint32_t data; 782 struct { 783 uint8_t status; /* Descriptor status */ 784 uint8_t hdr_len; /* Header length */ 785 uint16_t mss; /* Maximum segment size */ 786 } fields; 787 } tcp_seg_setup; 788 }; 789 790 /* Offload data descriptor */ 791 struct e1000_data_desc { 792 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 793 union { 794 uint32_t data; 795 struct { 796 uint16_t length; /* Data buffer length */ 797 uint8_t typ_len_ext; /* */ 798 uint8_t cmd; /* */ 799 } flags; 800 } lower; 801 union { 802 uint32_t data; 803 struct { 804 uint8_t status; /* Descriptor status */ 805 uint8_t popts; /* Packet Options */ 806 uint16_t special; /* */ 807 } fields; 808 } upper; 809 }; 810 811 /* Filters */ 812 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 813 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 814 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 815 816 #define E1000_NUM_UNICAST_ICH8LAN 7 817 #define E1000_MC_TBL_SIZE_ICH8LAN 32 818 819 820 /* Receive Address Register */ 821 struct e1000_rar { 822 volatile uint32_t low; /* receive address low */ 823 volatile uint32_t high; /* receive address high */ 824 }; 825 826 /* Number of entries in the Multicast Table Array (MTA). */ 827 #define E1000_NUM_MTA_REGISTERS 128 828 #define E1000_NUM_MTA_REGISTERS_ICH8LAN 32 829 830 /* IPv4 Address Table Entry */ 831 struct e1000_ipv4_at_entry { 832 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 833 volatile uint32_t reserved; 834 }; 835 836 /* Four wakeup IP addresses are supported */ 837 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 838 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 839 #define E1000_IP4AT_SIZE_ICH8LAN 3 840 #define E1000_IP6AT_SIZE 1 841 842 /* IPv6 Address Table Entry */ 843 struct e1000_ipv6_at_entry { 844 volatile uint8_t ipv6_addr[16]; 845 }; 846 847 /* Flexible Filter Length Table Entry */ 848 struct e1000_fflt_entry { 849 volatile uint32_t length; /* Flexible Filter Length (RW) */ 850 volatile uint32_t reserved; 851 }; 852 853 /* Flexible Filter Mask Table Entry */ 854 struct e1000_ffmt_entry { 855 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 856 volatile uint32_t reserved; 857 }; 858 859 /* Flexible Filter Value Table Entry */ 860 struct e1000_ffvt_entry { 861 volatile uint32_t value; /* Flexible Filter Value (RW) */ 862 volatile uint32_t reserved; 863 }; 864 865 /* Four Flexible Filters are supported */ 866 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 867 868 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 869 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 870 871 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 872 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 873 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 874 875 #define E1000_DISABLE_SERDES_LOOPBACK 0x0400 876 877 /* Register Set. (82543, 82544) 878 * 879 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 880 * These registers are physically located on the NIC, but are mapped into the 881 * host memory address space. 882 * 883 * RW - register is both readable and writable 884 * RO - register is read only 885 * WO - register is write only 886 * R/clr - register is read only and is cleared when read 887 * A - register array 888 */ 889 #define E1000_CTRL 0x00000 /* Device Control - RW */ 890 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 891 #define E1000_STATUS 0x00008 /* Device Status - RO */ 892 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 893 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 894 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 895 #define E1000_FLA 0x0001C /* Flash Access - RW */ 896 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 897 #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 898 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 899 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 900 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 901 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 902 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 903 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 904 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 905 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 906 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 907 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 908 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 909 #define E1000_RCTL 0x00100 /* RX Control - RW */ 910 #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 911 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 912 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 913 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 914 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ 915 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ 916 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 917 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 918 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 919 #define E1000_TCTL 0x00400 /* TX Control - RW */ 920 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 921 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 922 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 923 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 924 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 925 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 926 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 927 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 928 #define FEXTNVM_SW_CONFIG 0x0001 929 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 930 #define E1000_PBS 0x01008 /* Packet Buffer Size */ 931 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 932 #define E1000_FLASH_UPDATES 1000 933 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 934 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 935 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 936 #define E1000_FLSWCTL 0x01030 /* FLASH control register */ 937 #define E1000_FLSWDATA 0x01034 /* FLASH data register */ 938 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 939 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 940 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 941 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 942 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 943 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 944 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 945 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 946 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 947 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 948 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 949 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 950 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 951 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 952 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 953 #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 954 #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 955 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 956 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ 957 #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ 958 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 959 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 960 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 961 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 962 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 963 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 964 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 965 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 966 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 967 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 968 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 969 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 970 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 971 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 972 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 973 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 974 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 975 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 976 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 977 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 978 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 979 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 980 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 981 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 982 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 983 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 984 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 985 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 986 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 987 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 988 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 989 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 990 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 991 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 992 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 993 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 994 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 995 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 996 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 997 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 998 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 999 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 1000 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 1001 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 1002 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 1003 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 1004 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 1005 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 1006 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 1007 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 1008 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 1009 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 1010 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 1011 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 1012 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 1013 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 1014 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 1015 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 1016 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 1017 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 1018 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 1019 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 1020 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 1021 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 1022 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 1023 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 1024 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 1025 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 1026 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 1027 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 1028 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 1029 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 1030 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 1031 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 1032 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 1033 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 1034 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 1035 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 1036 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 1037 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 1038 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 1039 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 1040 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 1041 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 1042 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 1043 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 1044 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 1045 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 1046 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 1047 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 1048 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 1049 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 1050 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 1051 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 1052 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 1053 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 1054 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 1055 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 1056 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 1057 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 1058 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 1059 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 1060 #define E1000_MANC 0x05820 /* Management Control - RW */ 1061 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 1062 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 1063 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 1064 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 1065 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 1066 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 1067 #define E1000_HOST_IF 0x08800 /* Host Interface */ 1068 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 1069 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 1070 1071 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 1072 #define E1000_MDPHYA 0x0003C /* PHY address - RW */ 1073 #define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ 1074 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 1075 1076 #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 1077 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 1078 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 1079 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 1080 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 1081 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 1082 #define E1000_SWSM 0x05B50 /* SW Semaphore */ 1083 #define E1000_FWSM 0x05B54 /* FW Semaphore */ 1084 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 1085 #define E1000_HICR 0x08F00 /* Host Inteface Control */ 1086 1087 /* RSS registers */ 1088 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 1089 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 1090 #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 1091 #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 1092 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 1093 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 1094 /* Register Set (82542) 1095 * 1096 * Some of the 82542 registers are located at different offsets than they are 1097 * in more current versions of the 8254x. Despite the difference in location, 1098 * the registers function in the same manner. 1099 */ 1100 #define E1000_82542_CTRL E1000_CTRL 1101 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP 1102 #define E1000_82542_STATUS E1000_STATUS 1103 #define E1000_82542_EECD E1000_EECD 1104 #define E1000_82542_EERD E1000_EERD 1105 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT 1106 #define E1000_82542_FLA E1000_FLA 1107 #define E1000_82542_MDIC E1000_MDIC 1108 #define E1000_82542_SCTL E1000_SCTL 1109 #define E1000_82542_FEXTNVM E1000_FEXTNVM 1110 #define E1000_82542_FCAL E1000_FCAL 1111 #define E1000_82542_FCAH E1000_FCAH 1112 #define E1000_82542_FCT E1000_FCT 1113 #define E1000_82542_VET E1000_VET 1114 #define E1000_82542_RA 0x00040 1115 #define E1000_82542_ICR E1000_ICR 1116 #define E1000_82542_ITR E1000_ITR 1117 #define E1000_82542_ICS E1000_ICS 1118 #define E1000_82542_IMS E1000_IMS 1119 #define E1000_82542_IMC E1000_IMC 1120 #define E1000_82542_RCTL E1000_RCTL 1121 #define E1000_82542_RDTR 0x00108 1122 #define E1000_82542_RDBAL 0x00110 1123 #define E1000_82542_RDBAH 0x00114 1124 #define E1000_82542_RDLEN 0x00118 1125 #define E1000_82542_RDH 0x00120 1126 #define E1000_82542_RDT 0x00128 1127 #define E1000_82542_RDTR0 E1000_82542_RDTR 1128 #define E1000_82542_RDBAL0 E1000_82542_RDBAL 1129 #define E1000_82542_RDBAH0 E1000_82542_RDBAH 1130 #define E1000_82542_RDLEN0 E1000_82542_RDLEN 1131 #define E1000_82542_RDH0 E1000_82542_RDH 1132 #define E1000_82542_RDT0 E1000_82542_RDT 1133 #define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication 1134 * RX Control - RW */ 1135 #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) 1136 #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ 1137 #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ 1138 #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ 1139 #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ 1140 #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ 1141 #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ 1142 #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ 1143 #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ 1144 #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ 1145 #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ 1146 #define E1000_82542_RDTR1 0x00130 1147 #define E1000_82542_RDBAL1 0x00138 1148 #define E1000_82542_RDBAH1 0x0013C 1149 #define E1000_82542_RDLEN1 0x00140 1150 #define E1000_82542_RDH1 0x00148 1151 #define E1000_82542_RDT1 0x00150 1152 #define E1000_82542_FCRTH 0x00160 1153 #define E1000_82542_FCRTL 0x00168 1154 #define E1000_82542_FCTTV E1000_FCTTV 1155 #define E1000_82542_TXCW E1000_TXCW 1156 #define E1000_82542_RXCW E1000_RXCW 1157 #define E1000_82542_MTA 0x00200 1158 #define E1000_82542_TCTL E1000_TCTL 1159 #define E1000_82542_TCTL_EXT E1000_TCTL_EXT 1160 #define E1000_82542_TIPG E1000_TIPG 1161 #define E1000_82542_TDBAL 0x00420 1162 #define E1000_82542_TDBAH 0x00424 1163 #define E1000_82542_TDLEN 0x00428 1164 #define E1000_82542_TDH 0x00430 1165 #define E1000_82542_TDT 0x00438 1166 #define E1000_82542_TIDV 0x00440 1167 #define E1000_82542_TBT E1000_TBT 1168 #define E1000_82542_AIT E1000_AIT 1169 #define E1000_82542_VFTA 0x00600 1170 #define E1000_82542_LEDCTL E1000_LEDCTL 1171 #define E1000_82542_PBA E1000_PBA 1172 #define E1000_82542_PBS E1000_PBS 1173 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL 1174 #define E1000_82542_EEARBC E1000_EEARBC 1175 #define E1000_82542_FLASHT E1000_FLASHT 1176 #define E1000_82542_EEWR E1000_EEWR 1177 #define E1000_82542_FLSWCTL E1000_FLSWCTL 1178 #define E1000_82542_FLSWDATA E1000_FLSWDATA 1179 #define E1000_82542_FLSWCNT E1000_FLSWCNT 1180 #define E1000_82542_FLOP E1000_FLOP 1181 #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL 1182 #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE 1183 #define E1000_82542_PHY_CTRL E1000_PHY_CTRL 1184 #define E1000_82542_ERT E1000_ERT 1185 #define E1000_82542_RXDCTL E1000_RXDCTL 1186 #define E1000_82542_RXDCTL1 E1000_RXDCTL1 1187 #define E1000_82542_RADV E1000_RADV 1188 #define E1000_82542_RSRPD E1000_RSRPD 1189 #define E1000_82542_TXDMAC E1000_TXDMAC 1190 #define E1000_82542_KABGTXD E1000_KABGTXD 1191 #define E1000_82542_TDFHS E1000_TDFHS 1192 #define E1000_82542_TDFTS E1000_TDFTS 1193 #define E1000_82542_TDFPC E1000_TDFPC 1194 #define E1000_82542_TXDCTL E1000_TXDCTL 1195 #define E1000_82542_TADV E1000_TADV 1196 #define E1000_82542_TSPMT E1000_TSPMT 1197 #define E1000_82542_CRCERRS E1000_CRCERRS 1198 #define E1000_82542_ALGNERRC E1000_ALGNERRC 1199 #define E1000_82542_SYMERRS E1000_SYMERRS 1200 #define E1000_82542_RXERRC E1000_RXERRC 1201 #define E1000_82542_MPC E1000_MPC 1202 #define E1000_82542_SCC E1000_SCC 1203 #define E1000_82542_ECOL E1000_ECOL 1204 #define E1000_82542_MCC E1000_MCC 1205 #define E1000_82542_LATECOL E1000_LATECOL 1206 #define E1000_82542_COLC E1000_COLC 1207 #define E1000_82542_DC E1000_DC 1208 #define E1000_82542_TNCRS E1000_TNCRS 1209 #define E1000_82542_SEC E1000_SEC 1210 #define E1000_82542_CEXTERR E1000_CEXTERR 1211 #define E1000_82542_RLEC E1000_RLEC 1212 #define E1000_82542_XONRXC E1000_XONRXC 1213 #define E1000_82542_XONTXC E1000_XONTXC 1214 #define E1000_82542_XOFFRXC E1000_XOFFRXC 1215 #define E1000_82542_XOFFTXC E1000_XOFFTXC 1216 #define E1000_82542_FCRUC E1000_FCRUC 1217 #define E1000_82542_PRC64 E1000_PRC64 1218 #define E1000_82542_PRC127 E1000_PRC127 1219 #define E1000_82542_PRC255 E1000_PRC255 1220 #define E1000_82542_PRC511 E1000_PRC511 1221 #define E1000_82542_PRC1023 E1000_PRC1023 1222 #define E1000_82542_PRC1522 E1000_PRC1522 1223 #define E1000_82542_GPRC E1000_GPRC 1224 #define E1000_82542_BPRC E1000_BPRC 1225 #define E1000_82542_MPRC E1000_MPRC 1226 #define E1000_82542_GPTC E1000_GPTC 1227 #define E1000_82542_GORCL E1000_GORCL 1228 #define E1000_82542_GORCH E1000_GORCH 1229 #define E1000_82542_GOTCL E1000_GOTCL 1230 #define E1000_82542_GOTCH E1000_GOTCH 1231 #define E1000_82542_RNBC E1000_RNBC 1232 #define E1000_82542_RUC E1000_RUC 1233 #define E1000_82542_RFC E1000_RFC 1234 #define E1000_82542_ROC E1000_ROC 1235 #define E1000_82542_RJC E1000_RJC 1236 #define E1000_82542_MGTPRC E1000_MGTPRC 1237 #define E1000_82542_MGTPDC E1000_MGTPDC 1238 #define E1000_82542_MGTPTC E1000_MGTPTC 1239 #define E1000_82542_TORL E1000_TORL 1240 #define E1000_82542_TORH E1000_TORH 1241 #define E1000_82542_TOTL E1000_TOTL 1242 #define E1000_82542_TOTH E1000_TOTH 1243 #define E1000_82542_TPR E1000_TPR 1244 #define E1000_82542_TPT E1000_TPT 1245 #define E1000_82542_PTC64 E1000_PTC64 1246 #define E1000_82542_PTC127 E1000_PTC127 1247 #define E1000_82542_PTC255 E1000_PTC255 1248 #define E1000_82542_PTC511 E1000_PTC511 1249 #define E1000_82542_PTC1023 E1000_PTC1023 1250 #define E1000_82542_PTC1522 E1000_PTC1522 1251 #define E1000_82542_MPTC E1000_MPTC 1252 #define E1000_82542_BPTC E1000_BPTC 1253 #define E1000_82542_TSCTC E1000_TSCTC 1254 #define E1000_82542_TSCTFC E1000_TSCTFC 1255 #define E1000_82542_RXCSUM E1000_RXCSUM 1256 #define E1000_82542_WUC E1000_WUC 1257 #define E1000_82542_WUFC E1000_WUFC 1258 #define E1000_82542_WUS E1000_WUS 1259 #define E1000_82542_MANC E1000_MANC 1260 #define E1000_82542_IPAV E1000_IPAV 1261 #define E1000_82542_IP4AT E1000_IP4AT 1262 #define E1000_82542_IP6AT E1000_IP6AT 1263 #define E1000_82542_WUPL E1000_WUPL 1264 #define E1000_82542_WUPM E1000_WUPM 1265 #define E1000_82542_FFLT E1000_FFLT 1266 #define E1000_82542_TDFH 0x08010 1267 #define E1000_82542_TDFT 0x08018 1268 #define E1000_82542_FFMT E1000_FFMT 1269 #define E1000_82542_FFVT E1000_FFVT 1270 #define E1000_82542_HOST_IF E1000_HOST_IF 1271 #define E1000_82542_IAM E1000_IAM 1272 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL 1273 #define E1000_82542_PSRCTL E1000_PSRCTL 1274 #define E1000_82542_RAID E1000_RAID 1275 #define E1000_82542_TARC0 E1000_TARC0 1276 #define E1000_82542_TDBAL1 E1000_TDBAL1 1277 #define E1000_82542_TDBAH1 E1000_TDBAH1 1278 #define E1000_82542_TDLEN1 E1000_TDLEN1 1279 #define E1000_82542_TDH1 E1000_TDH1 1280 #define E1000_82542_TDT1 E1000_TDT1 1281 #define E1000_82542_TXDCTL1 E1000_TXDCTL1 1282 #define E1000_82542_TARC1 E1000_TARC1 1283 #define E1000_82542_RFCTL E1000_RFCTL 1284 #define E1000_82542_GCR E1000_GCR 1285 #define E1000_82542_GSCL_1 E1000_GSCL_1 1286 #define E1000_82542_GSCL_2 E1000_GSCL_2 1287 #define E1000_82542_GSCL_3 E1000_GSCL_3 1288 #define E1000_82542_GSCL_4 E1000_GSCL_4 1289 #define E1000_82542_FACTPS E1000_FACTPS 1290 #define E1000_82542_SWSM E1000_SWSM 1291 #define E1000_82542_FWSM E1000_FWSM 1292 #define E1000_82542_FFLT_DBG E1000_FFLT_DBG 1293 #define E1000_82542_IAC E1000_IAC 1294 #define E1000_82542_ICRXPTC E1000_ICRXPTC 1295 #define E1000_82542_ICRXATC E1000_ICRXATC 1296 #define E1000_82542_ICTXPTC E1000_ICTXPTC 1297 #define E1000_82542_ICTXATC E1000_ICTXATC 1298 #define E1000_82542_ICTXQEC E1000_ICTXQEC 1299 #define E1000_82542_ICTXQMTC E1000_ICTXQMTC 1300 #define E1000_82542_ICRXDMTC E1000_ICRXDMTC 1301 #define E1000_82542_ICRXOC E1000_ICRXOC 1302 #define E1000_82542_HICR E1000_HICR 1303 1304 #define E1000_82542_CPUVEC E1000_CPUVEC 1305 #define E1000_82542_MRQC E1000_MRQC 1306 #define E1000_82542_RETA E1000_RETA 1307 #define E1000_82542_RSSRK E1000_RSSRK 1308 #define E1000_82542_RSSIM E1000_RSSIM 1309 #define E1000_82542_RSSIR E1000_RSSIR 1310 #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA 1311 #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC 1312 #define E1000_82542_MANC2H E1000_MANC2H 1313 1314 /* Statistics counters collected by the MAC */ 1315 struct e1000_hw_stats { 1316 uint64_t crcerrs; 1317 uint64_t algnerrc; 1318 uint64_t symerrs; 1319 uint64_t rxerrc; 1320 uint64_t txerrc; 1321 uint64_t mpc; 1322 uint64_t scc; 1323 uint64_t ecol; 1324 uint64_t mcc; 1325 uint64_t latecol; 1326 uint64_t colc; 1327 uint64_t dc; 1328 uint64_t tncrs; 1329 uint64_t sec; 1330 uint64_t cexterr; 1331 uint64_t rlec; 1332 uint64_t xonrxc; 1333 uint64_t xontxc; 1334 uint64_t xoffrxc; 1335 uint64_t xofftxc; 1336 uint64_t fcruc; 1337 uint64_t prc64; 1338 uint64_t prc127; 1339 uint64_t prc255; 1340 uint64_t prc511; 1341 uint64_t prc1023; 1342 uint64_t prc1522; 1343 uint64_t gprc; 1344 uint64_t bprc; 1345 uint64_t mprc; 1346 uint64_t gptc; 1347 uint64_t gorcl; 1348 uint64_t gorch; 1349 uint64_t gotcl; 1350 uint64_t gotch; 1351 uint64_t rnbc; 1352 uint64_t ruc; 1353 uint64_t rfc; 1354 uint64_t roc; 1355 uint64_t rlerrc; 1356 uint64_t rjc; 1357 uint64_t mgprc; 1358 uint64_t mgpdc; 1359 uint64_t mgptc; 1360 uint64_t torl; 1361 uint64_t torh; 1362 uint64_t totl; 1363 uint64_t toth; 1364 uint64_t tpr; 1365 uint64_t tpt; 1366 uint64_t ptc64; 1367 uint64_t ptc127; 1368 uint64_t ptc255; 1369 uint64_t ptc511; 1370 uint64_t ptc1023; 1371 uint64_t ptc1522; 1372 uint64_t mptc; 1373 uint64_t bptc; 1374 uint64_t tsctc; 1375 uint64_t tsctfc; 1376 uint64_t iac; 1377 uint64_t icrxptc; 1378 uint64_t icrxatc; 1379 uint64_t ictxptc; 1380 uint64_t ictxatc; 1381 uint64_t ictxqec; 1382 uint64_t ictxqmtc; 1383 uint64_t icrxdmtc; 1384 uint64_t icrxoc; 1385 }; 1386 1387 /* Structure containing variables used by the shared code (e1000_hw.c) */ 1388 struct e1000_hw { 1389 uint8_t *hw_addr; 1390 uint8_t *flash_address; 1391 e1000_mac_type mac_type; 1392 e1000_phy_type phy_type; 1393 uint32_t phy_init_script; 1394 e1000_media_type media_type; 1395 void *back; 1396 struct e1000_shadow_ram *eeprom_shadow_ram; 1397 uint32_t flash_bank_size; 1398 uint32_t flash_base_addr; 1399 e1000_fc_type fc; 1400 e1000_bus_speed bus_speed; 1401 e1000_bus_width bus_width; 1402 e1000_bus_type bus_type; 1403 struct e1000_eeprom_info eeprom; 1404 e1000_ms_type master_slave; 1405 e1000_ms_type original_master_slave; 1406 e1000_ffe_config ffe_config_state; 1407 uint32_t asf_firmware_present; 1408 uint32_t eeprom_semaphore_present; 1409 uint32_t swfw_sync_present; 1410 uint32_t swfwhw_semaphore_present; 1411 unsigned long io_base; 1412 uint32_t phy_id; 1413 uint32_t phy_revision; 1414 uint32_t phy_addr; 1415 uint32_t original_fc; 1416 uint32_t txcw; 1417 uint32_t autoneg_failed; 1418 uint32_t max_frame_size; 1419 uint32_t min_frame_size; 1420 uint32_t mc_filter_type; 1421 uint32_t num_mc_addrs; 1422 uint32_t collision_delta; 1423 uint32_t tx_packet_delta; 1424 uint32_t ledctl_default; 1425 uint32_t ledctl_mode1; 1426 uint32_t ledctl_mode2; 1427 boolean_t tx_pkt_filtering; 1428 struct e1000_host_mng_dhcp_cookie mng_cookie; 1429 uint16_t phy_spd_default; 1430 uint16_t autoneg_advertised; 1431 uint16_t pci_cmd_word; 1432 uint16_t fc_high_water; 1433 uint16_t fc_low_water; 1434 uint16_t fc_pause_time; 1435 uint16_t current_ifs_val; 1436 uint16_t ifs_min_val; 1437 uint16_t ifs_max_val; 1438 uint16_t ifs_step_size; 1439 uint16_t ifs_ratio; 1440 uint16_t device_id; 1441 uint16_t vendor_id; 1442 uint16_t subsystem_id; 1443 uint16_t subsystem_vendor_id; 1444 uint8_t revision_id; 1445 uint8_t autoneg; 1446 uint8_t mdix; 1447 uint8_t forced_speed_duplex; 1448 uint8_t wait_autoneg_complete; 1449 uint8_t dma_fairness; 1450 uint8_t mac_addr[NODE_ADDRESS_SIZE]; 1451 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 1452 boolean_t disable_polarity_correction; 1453 boolean_t speed_downgraded; 1454 e1000_smart_speed smart_speed; 1455 e1000_dsp_config dsp_config_state; 1456 boolean_t get_link_status; 1457 boolean_t serdes_link_down; 1458 boolean_t tbi_compatibility_en; 1459 boolean_t tbi_compatibility_on; 1460 boolean_t laa_is_present; 1461 boolean_t phy_reset_disable; 1462 boolean_t initialize_hw_bits_disable; 1463 boolean_t fc_send_xon; 1464 boolean_t fc_strict_ieee; 1465 boolean_t report_tx_early; 1466 boolean_t adaptive_ifs; 1467 boolean_t ifs_params_forced; 1468 boolean_t in_ifs_mode; 1469 boolean_t mng_reg_access_disabled; 1470 boolean_t leave_av_bit_off; 1471 boolean_t kmrn_lock_loss_workaround_disabled; 1472 boolean_t bad_tx_carr_stats_fd; 1473 boolean_t has_manc2h; 1474 boolean_t rx_needs_kicking; 1475 boolean_t has_smbus; 1476 }; 1477 1478 1479 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1480 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1481 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 1482 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1483 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 1484 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1485 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 1486 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ 1487 /* Register Bit Masks */ 1488 /* Device Control */ 1489 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1490 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1491 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1492 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 1493 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1494 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1495 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1496 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1497 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1498 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1499 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1500 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1501 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1502 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1503 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1504 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1505 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1506 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 1507 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 1508 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 1509 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 1510 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1511 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1512 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1513 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1514 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1515 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1516 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1517 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1518 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 1519 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1520 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1521 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1522 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1523 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1524 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 1525 1526 /* Device Status */ 1527 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1528 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1529 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1530 #define E1000_STATUS_FUNC_SHIFT 2 1531 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1532 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1533 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1534 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1535 #define E1000_STATUS_SPEED_MASK 0x000000C0 1536 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1537 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1538 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1539 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 1540 by EEPROM/Flash */ 1541 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1542 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1543 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1544 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1545 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1546 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1547 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1548 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1549 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 1550 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 1551 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 1552 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 1553 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 1554 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 1555 #define E1000_STATUS_FUSE_8 0x04000000 1556 #define E1000_STATUS_FUSE_9 0x08000000 1557 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 1558 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 1559 1560 /* Constants used to intrepret the masked PCI-X bus speed. */ 1561 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1562 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1563 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1564 1565 /* EEPROM/Flash Control */ 1566 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1567 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1568 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1569 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1570 #define E1000_EECD_FWE_MASK 0x00000030 1571 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1572 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1573 #define E1000_EECD_FWE_SHIFT 4 1574 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1575 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1576 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1577 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1578 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1579 * (0-small, 1-large) */ 1580 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1581 #ifndef E1000_EEPROM_GRANT_ATTEMPTS 1582 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1583 #endif 1584 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1585 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1586 #define E1000_EECD_SIZE_EX_SHIFT 11 1587 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1588 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1589 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1590 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1591 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1592 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1593 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1594 #define E1000_EECD_SECVAL_SHIFT 22 1595 #define E1000_STM_OPCODE 0xDB00 1596 #define E1000_HICR_FW_RESET 0xC0 1597 1598 #define E1000_SHADOW_RAM_WORDS 2048 1599 #define E1000_ICH_NVM_SIG_WORD 0x13 1600 #define E1000_ICH_NVM_SIG_MASK 0xC0 1601 1602 /* EEPROM Read */ 1603 #define E1000_EERD_START 0x00000001 /* Start Read */ 1604 #define E1000_EERD_DONE 0x00000010 /* Read Done */ 1605 #define E1000_EERD_ADDR_SHIFT 8 1606 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1607 #define E1000_EERD_DATA_SHIFT 16 1608 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1609 1610 /* SPI EEPROM Status Register */ 1611 #define EEPROM_STATUS_RDY_SPI 0x01 1612 #define EEPROM_STATUS_WEN_SPI 0x02 1613 #define EEPROM_STATUS_BP0_SPI 0x04 1614 #define EEPROM_STATUS_BP1_SPI 0x08 1615 #define EEPROM_STATUS_WPEN_SPI 0x80 1616 1617 /* Extended Device Control */ 1618 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1619 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1620 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1621 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1622 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1623 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1624 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1625 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1626 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1627 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1628 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1629 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1630 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1631 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1632 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1633 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1634 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1635 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1636 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1637 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1638 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1639 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1640 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 1641 #define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000 1642 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 1643 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 1644 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 1645 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1646 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1647 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1648 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1649 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1650 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1651 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 1652 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 1653 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 1654 1655 /* MDI Control */ 1656 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1657 #define E1000_MDIC_REG_MASK 0x001F0000 1658 #define E1000_MDIC_REG_SHIFT 16 1659 #define E1000_MDIC_PHY_MASK 0x03E00000 1660 #define E1000_MDIC_PHY_SHIFT 21 1661 #define E1000_MDIC_OP_WRITE 0x04000000 1662 #define E1000_MDIC_OP_READ 0x08000000 1663 #define E1000_MDIC_READY 0x10000000 1664 #define E1000_MDIC_INT_EN 0x20000000 1665 #define E1000_MDIC_ERROR 0x40000000 1666 1667 #define E1000_KUMCTRLSTA_MASK 0x0000FFFF 1668 #define E1000_KUMCTRLSTA_OFFSET 0x001F0000 1669 #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 1670 #define E1000_KUMCTRLSTA_REN 0x00200000 1671 1672 #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 1673 #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 1674 #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 1675 #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 1676 #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 1677 #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 1678 #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 1679 #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 1680 #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 1681 1682 /* FIFO Control */ 1683 #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 1684 #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1685 1686 /* In-Band Control */ 1687 #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 1688 #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1689 1690 /* Half-Duplex Control */ 1691 #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1692 #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1693 1694 #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E 1695 1696 #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 1697 #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 1698 1699 #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 1700 #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 1701 #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 1702 1703 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 1704 1705 #define E1000_PHY_CTRL_SPD_EN 0x00000001 1706 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 1707 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 1708 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 1709 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 1710 #define E1000_PHY_CTRL_B2B_EN 0x00000080 1711 1712 /* LED Control */ 1713 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1714 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 1715 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 1716 #define E1000_LEDCTL_LED0_IVRT 0x00000040 1717 #define E1000_LEDCTL_LED0_BLINK 0x00000080 1718 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1719 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 1720 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 1721 #define E1000_LEDCTL_LED1_IVRT 0x00004000 1722 #define E1000_LEDCTL_LED1_BLINK 0x00008000 1723 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1724 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 1725 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 1726 #define E1000_LEDCTL_LED2_IVRT 0x00400000 1727 #define E1000_LEDCTL_LED2_BLINK 0x00800000 1728 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1729 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 1730 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 1731 #define E1000_LEDCTL_LED3_IVRT 0x40000000 1732 #define E1000_LEDCTL_LED3_BLINK 0x80000000 1733 1734 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 1735 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 1736 #define E1000_LEDCTL_MODE_LINK_UP 0x2 1737 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 1738 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 1739 #define E1000_LEDCTL_MODE_LINK_10 0x5 1740 #define E1000_LEDCTL_MODE_LINK_100 0x6 1741 #define E1000_LEDCTL_MODE_LINK_1000 0x7 1742 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 1743 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 1744 #define E1000_LEDCTL_MODE_COLLISION 0xA 1745 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 1746 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 1747 #define E1000_LEDCTL_MODE_PAUSED 0xD 1748 #define E1000_LEDCTL_MODE_LED_ON 0xE 1749 #define E1000_LEDCTL_MODE_LED_OFF 0xF 1750 1751 /* Receive Address */ 1752 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1753 1754 #define E1000_RAH_POOL_1 0x00040000 1755 1756 /* Interrupt Cause Read */ 1757 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1758 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1759 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1760 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1761 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1762 /* LAN connected device generates an interrupt */ 1763 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 1764 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1765 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1766 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1767 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1768 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1769 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1770 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1771 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1772 #define E1000_ICR_TXD_LOW 0x00008000 1773 #define E1000_ICR_SRPD 0x00010000 1774 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 1775 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 1776 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 1777 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 1778 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 1779 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 1780 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 1781 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 1782 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1783 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1784 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1785 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 1786 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 1787 #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 1788 1789 /* Interrupt Cause Set */ 1790 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1791 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1792 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1793 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1794 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1795 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1796 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1797 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1798 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1799 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1800 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1801 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1802 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1803 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1804 #define E1000_ICS_SRPD E1000_ICR_SRPD 1805 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1806 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1807 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1808 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1809 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1810 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1811 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1812 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1813 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1814 #define E1000_ICS_DSW E1000_ICR_DSW 1815 #define E1000_ICS_PHYINT E1000_ICR_PHYINT 1816 #define E1000_ICS_EPRST E1000_ICR_EPRST 1817 1818 /* Interrupt Mask Set */ 1819 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1820 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1821 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1822 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1823 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1824 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1825 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 1826 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1827 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1828 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1829 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1830 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1831 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1832 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1833 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1834 #define E1000_IMS_SRPD E1000_ICR_SRPD 1835 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1836 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 1837 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1838 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1839 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1840 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1841 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1842 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1843 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1844 #define E1000_IMS_DSW E1000_ICR_DSW 1845 #define E1000_IMS_PHYINT E1000_ICR_PHYINT 1846 #define E1000_IMS_EPRST E1000_ICR_EPRST 1847 1848 /* Interrupt Mask Clear */ 1849 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1850 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1851 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1852 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1853 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1854 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1855 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1856 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1857 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1858 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1859 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1860 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1861 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1862 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1863 #define E1000_IMC_SRPD E1000_ICR_SRPD 1864 #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 1865 #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 1866 #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1867 #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1868 #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1869 #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1870 #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1871 #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1872 #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1873 #define E1000_IMC_DSW E1000_ICR_DSW 1874 #define E1000_IMC_PHYINT E1000_ICR_PHYINT 1875 #define E1000_IMC_EPRST E1000_ICR_EPRST 1876 1877 /* Receive Control */ 1878 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 1879 #define E1000_RCTL_EN 0x00000002 /* enable */ 1880 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1881 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1882 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1883 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1884 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1885 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1886 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1887 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1888 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 1889 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 1890 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1891 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1892 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1893 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1894 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1895 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1896 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1897 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1898 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1899 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1900 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1901 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1902 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1903 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1904 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1905 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1906 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1907 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1908 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1909 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1910 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1911 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1912 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1913 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1914 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1915 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1916 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 1917 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 1918 1919 /* Use byte values for the following shift parameters 1920 * Usage: 1921 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 1922 * E1000_PSRCTL_BSIZE0_MASK) | 1923 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 1924 * E1000_PSRCTL_BSIZE1_MASK) | 1925 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 1926 * E1000_PSRCTL_BSIZE2_MASK) | 1927 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 1928 * E1000_PSRCTL_BSIZE3_MASK)) 1929 * where value0 = [128..16256], default=256 1930 * value1 = [1024..64512], default=4096 1931 * value2 = [0..64512], default=4096 1932 * value3 = [0..64512], default=0 1933 */ 1934 1935 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 1936 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 1937 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 1938 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 1939 1940 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 1941 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 1942 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 1943 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 1944 1945 /* SW_W_SYNC definitions */ 1946 #define E1000_SWFW_EEP_SM 0x0001 1947 #define E1000_SWFW_PHY0_SM 0x0002 1948 #define E1000_SWFW_PHY1_SM 0x0004 1949 #define E1000_SWFW_MAC_CSR_SM 0x0008 1950 1951 /* Receive Descriptor */ 1952 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1953 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1954 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1955 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1956 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1957 1958 /* Flow Control */ 1959 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1960 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1961 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1962 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1963 1964 /* Header split receive */ 1965 #define E1000_RFCTL_ISCSI_DIS 0x00000001 1966 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 1967 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 1968 #define E1000_RFCTL_NFSW_DIS 0x00000040 1969 #define E1000_RFCTL_NFSR_DIS 0x00000080 1970 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 1971 #define E1000_RFCTL_NFS_VER_SHIFT 8 1972 #define E1000_RFCTL_IPV6_DIS 0x00000400 1973 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 1974 #define E1000_RFCTL_ACK_DIS 0x00001000 1975 #define E1000_RFCTL_ACKD_DIS 0x00002000 1976 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 1977 #define E1000_RFCTL_EXTEN 0x00008000 1978 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 1979 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1980 1981 /* Receive Descriptor Control */ 1982 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1983 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1984 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1985 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1986 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 1987 #define IGB_RX_PTHRESH 16 1988 #define IGB_RX_HTHRESH 8 1989 #define IGB_RX_WTHRESH 1 1990 1991 /* Transmit Descriptor Control */ 1992 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1993 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1994 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 1995 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1996 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1997 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1998 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 1999 still to be processed. */ 2000 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 2001 /* Transmit Configuration Word */ 2002 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 2003 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 2004 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 2005 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 2006 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 2007 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 2008 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 2009 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 2010 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 2011 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 2012 2013 /* Receive Configuration Word */ 2014 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 2015 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 2016 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 2017 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 2018 #define E1000_RXCW_C 0x20000000 /* Receive config */ 2019 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 2020 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 2021 2022 /* Transmit Control */ 2023 #define E1000_TCTL_RST 0x00000001 /* software reset */ 2024 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 2025 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 2026 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 2027 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 2028 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 2029 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 2030 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 2031 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 2032 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 2033 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 2034 /* Extended Transmit Control */ 2035 #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 2036 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 2037 2038 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 2039 2040 /* Receive Checksum Control */ 2041 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 2042 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 2043 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 2044 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 2045 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 2046 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 2047 2048 /* Multiple Receive Queue Control */ 2049 #define E1000_MRQC_ENABLE_MASK 0x00000003 2050 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 2051 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 2052 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 2053 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 2054 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2055 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 2056 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 2057 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2058 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 2059 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2060 2061 /* Definitions for power management and wakeup registers */ 2062 /* Wake Up Control */ 2063 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 2064 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 2065 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 2066 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 2067 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 2068 2069 /* Wake Up Filter Control */ 2070 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 2071 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 2072 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 2073 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 2074 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 2075 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 2076 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 2077 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 2078 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 2079 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 2080 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 2081 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 2082 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 2083 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 2084 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 2085 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 2086 2087 /* Wake Up Status */ 2088 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 2089 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 2090 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 2091 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 2092 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 2093 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 2094 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 2095 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 2096 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 2097 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 2098 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 2099 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 2100 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 2101 2102 /* Management Control */ 2103 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 2104 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 2105 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 2106 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 2107 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 2108 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 2109 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 2110 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 2111 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 2112 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 2113 * Filtering */ 2114 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 2115 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 2116 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 2117 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 2118 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 2119 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2120 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 2121 * filtering */ 2122 #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 2123 * memory */ 2124 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2125 * filtering */ 2126 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2127 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2128 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2129 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2130 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2131 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 2132 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 2133 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 2134 2135 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 2136 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 2137 2138 /* SW Semaphore Register */ 2139 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2140 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2141 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2142 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2143 2144 /* FW Semaphore Register */ 2145 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2146 #define E1000_FWSM_MODE_SHIFT 1 2147 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2148 2149 #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2150 #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2151 #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2152 #define E1000_FWSM_SKUEL_SHIFT 29 2153 #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2154 #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2155 #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2156 #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2157 2158 /* FFLT Debug Register */ 2159 #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2160 2161 typedef enum { 2162 e1000_mng_mode_none = 0, 2163 e1000_mng_mode_asf, 2164 e1000_mng_mode_pt, 2165 e1000_mng_mode_ipmi, 2166 e1000_mng_mode_host_interface_only 2167 } e1000_mng_mode; 2168 2169 /* Host Inteface Control Register */ 2170 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ 2171 #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done 2172 * to put command in RAM */ 2173 #define E1000_HICR_SV 0x00000004 /* Status Validity */ 2174 #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ 2175 2176 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ 2177 #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ 2178 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ 2179 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ 2180 #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2181 2182 struct e1000_host_command_header { 2183 uint8_t command_id; 2184 uint8_t command_length; 2185 uint8_t command_options; /* I/F bits for command, status for return */ 2186 uint8_t checksum; 2187 }; 2188 struct e1000_host_command_info { 2189 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2190 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2191 }; 2192 2193 /* Host SMB register #0 */ 2194 #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ 2195 #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ 2196 #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ 2197 #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ 2198 2199 /* Host SMB register #1 */ 2200 #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN 2201 #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN 2202 #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT 2203 #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT 2204 2205 /* FW Status Register */ 2206 #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ 2207 2208 /* Wake Up Packet Length */ 2209 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 2210 2211 #define E1000_MDALIGN 4096 2212 2213 /* PCI-Ex registers*/ 2214 2215 /* PCI-Ex Control Register */ 2216 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 2217 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 2218 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 2219 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 2220 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 2221 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 2222 2223 #define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 2224 E1000_GCR_RXDSCW_NO_SNOOP | \ 2225 E1000_GCR_RXDSCR_NO_SNOOP | \ 2226 E1000_GCR_TXD_NO_SNOOP | \ 2227 E1000_GCR_TXDSCW_NO_SNOOP | \ 2228 E1000_GCR_TXDSCR_NO_SNOOP) 2229 2230 #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL 2231 2232 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2233 /* Function Active and Power State to MNG */ 2234 #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2235 #define E1000_FACTPS_LAN0_VALID 0x00000004 2236 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 2237 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 2238 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 2239 #define E1000_FACTPS_LAN1_VALID 0x00000100 2240 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 2241 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 2242 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 2243 #define E1000_FACTPS_IDE_ENABLE 0x00004000 2244 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 2245 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 2246 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 2247 #define E1000_FACTPS_SP_ENABLE 0x00100000 2248 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 2249 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 2250 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 2251 #define E1000_FACTPS_IPMI_ENABLE 0x04000000 2252 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 2253 #define E1000_FACTPS_MNGCG 0x20000000 2254 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 2255 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 2256 2257 /* PCI-Ex Config Space */ 2258 #define PCI_EX_LINK_STATUS 0x12 2259 #define PCI_EX_LINK_WIDTH_MASK 0x3F0 2260 #define PCI_EX_LINK_WIDTH_SHIFT 4 2261 2262 /* EEPROM Commands - Microwire */ 2263 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 2264 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 2265 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 2266 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 2267 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2268 2269 /* EEPROM Commands - SPI */ 2270 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2271 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2272 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2273 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2274 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 2275 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 2276 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 2277 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 2278 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2279 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2280 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2281 2282 /* EEPROM Size definitions */ 2283 #define EEPROM_WORD_SIZE_SHIFT 6 2284 #define EEPROM_SIZE_SHIFT 10 2285 #define EEPROM_SIZE_MASK 0x1C00 2286 2287 /* EEPROM Word Offsets */ 2288 #define EEPROM_COMPAT 0x0003 2289 #define EEPROM_ID_LED_SETTINGS 0x0004 2290 #define EEPROM_VERSION 0x0005 2291 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 2292 #define EEPROM_PHY_CLASS_WORD 0x0007 2293 #define EEPROM_INIT_CONTROL1_REG 0x000A 2294 #define EEPROM_INIT_CONTROL2_REG 0x000F 2295 #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 2296 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2297 #define EEPROM_INIT_3GIO_3 0x001A 2298 #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 2299 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2300 #define EEPROM_CFG 0x0012 2301 #define EEPROM_FLASH_VERSION 0x0032 2302 #define EEPROM_ALT_MAC_ADDR_PTR 0x0037 2303 #define EEPROM_CHECKSUM_REG 0x003F 2304 2305 #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 2306 #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 2307 2308 /* Word definitions for ID LED Settings */ 2309 #define ID_LED_RESERVED_0000 0x0000 2310 #define ID_LED_RESERVED_FFFF 0xFFFF 2311 #define ID_LED_RESERVED_82573 0xF746 2312 #define ID_LED_DEFAULT_82573 0x1811 2313 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2314 (ID_LED_OFF1_OFF2 << 8) | \ 2315 (ID_LED_DEF1_DEF2 << 4) | \ 2316 (ID_LED_DEF1_DEF2)) 2317 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 2318 (ID_LED_DEF1_OFF2 << 8) | \ 2319 (ID_LED_DEF1_ON2 << 4) | \ 2320 (ID_LED_DEF1_DEF2)) 2321 #define ID_LED_DEF1_DEF2 0x1 2322 #define ID_LED_DEF1_ON2 0x2 2323 #define ID_LED_DEF1_OFF2 0x3 2324 #define ID_LED_ON1_DEF2 0x4 2325 #define ID_LED_ON1_ON2 0x5 2326 #define ID_LED_ON1_OFF2 0x6 2327 #define ID_LED_OFF1_DEF2 0x7 2328 #define ID_LED_OFF1_ON2 0x8 2329 #define ID_LED_OFF1_OFF2 0x9 2330 2331 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 2332 #define IGP_ACTIVITY_LED_ENABLE 0x0300 2333 #define IGP_LED3_MODE 0x07000000 2334 2335 2336 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 2337 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 2338 2339 /* Mask bit for PHY class in Word 7 of the EEPROM */ 2340 #define EEPROM_PHY_CLASS_A 0x8000 2341 2342 /* Mask bits for fields in Word 0x0a of the EEPROM */ 2343 #define EEPROM_WORD0A_ILOS 0x0010 2344 #define EEPROM_WORD0A_SWDPIO 0x01E0 2345 #define EEPROM_WORD0A_LRST 0x0200 2346 #define EEPROM_WORD0A_FD 0x0400 2347 #define EEPROM_WORD0A_66MHZ 0x0800 2348 2349 /* Mask bits for fields in Word 0x0f of the EEPROM */ 2350 #define EEPROM_WORD0F_PAUSE_MASK 0x3000 2351 #define EEPROM_WORD0F_PAUSE 0x1000 2352 #define EEPROM_WORD0F_ASM_DIR 0x2000 2353 #define EEPROM_WORD0F_ANE 0x0800 2354 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2355 #define EEPROM_WORD0F_LPLU 0x0001 2356 2357 /* Mask bits for fields in Word 0x10/0x20 of the EEPROM */ 2358 #define EEPROM_WORD1020_GIGA_DISABLE 0x0010 2359 #define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008 2360 2361 /* Mask bits for fields in Word 0x1a of the EEPROM */ 2362 #define EEPROM_WORD1A_ASPM_MASK 0x000C 2363 2364 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 2365 #define EEPROM_SUM 0xBABA 2366 2367 /* EEPROM Map defines (WORD OFFSETS)*/ 2368 #define EEPROM_NODE_ADDRESS_BYTE_0 0 2369 #define EEPROM_PBA_BYTE_1 8 2370 2371 #define EEPROM_RESERVED_WORD 0xFFFF 2372 2373 /* EEPROM Map Sizes (Byte Counts) */ 2374 #define PBA_SIZE 4 2375 2376 /* Collision related configuration parameters */ 2377 #define E1000_COLLISION_THRESHOLD 15 2378 #define E1000_CT_SHIFT 4 2379 /* Collision distance is a 0-based value that applies to 2380 * half-duplex-capable hardware only. */ 2381 #define E1000_COLLISION_DISTANCE 63 2382 #define E1000_COLLISION_DISTANCE_82542 64 2383 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 2384 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 2385 #define E1000_COLD_SHIFT 12 2386 2387 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2388 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 2389 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 2390 2391 /* Default values for the transmit IPG register */ 2392 #define DEFAULT_82542_TIPG_IPGT 10 2393 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 2394 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 2395 2396 #define E1000_TIPG_IPGT_MASK 0x000003FF 2397 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 2398 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 2399 2400 #define DEFAULT_82542_TIPG_IPGR1 2 2401 #define DEFAULT_82543_TIPG_IPGR1 8 2402 #define E1000_TIPG_IPGR1_SHIFT 10 2403 2404 #define DEFAULT_82542_TIPG_IPGR2 10 2405 #define DEFAULT_82543_TIPG_IPGR2 6 2406 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 2407 #define E1000_TIPG_IPGR2_SHIFT 20 2408 2409 #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 2410 #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 2411 #define E1000_TXDMAC_DPP 0x00000001 2412 2413 /* Adaptive IFS defines */ 2414 #define TX_THRESHOLD_START 8 2415 #define TX_THRESHOLD_INCREMENT 10 2416 #define TX_THRESHOLD_DECREMENT 1 2417 #define TX_THRESHOLD_STOP 190 2418 #define TX_THRESHOLD_DISABLE 0 2419 #define TX_THRESHOLD_TIMER_MS 10000 2420 #define MIN_NUM_XMITS 1000 2421 #define IFS_MAX 80 2422 #define IFS_STEP 10 2423 #define IFS_MIN 40 2424 #define IFS_RATIO 4 2425 2426 /* Extended Configuration Control and Size */ 2427 #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 2428 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 2429 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 2430 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 2431 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2432 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2433 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2434 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000 2435 2436 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2437 #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2438 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2439 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 2440 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 2441 2442 /* PBA constants */ 2443 #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 2444 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2445 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2446 #define E1000_PBA_20K 0x0014 2447 #define E1000_PBA_22K 0x0016 2448 #define E1000_PBA_24K 0x0018 2449 #define E1000_PBA_30K 0x001E 2450 #define E1000_PBA_32K 0x0020 2451 #define E1000_PBA_34K 0x0022 2452 #define E1000_PBA_38K 0x0026 2453 #define E1000_PBA_40K 0x0028 2454 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2455 #define E1000_PBA_64K 0x0040 /* 64KB */ 2456 2457 #define E1000_PBS_16K E1000_PBA_16K 2458 2459 /* Flow Control Constants */ 2460 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2461 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2462 #define FLOW_CONTROL_TYPE 0x8808 2463 2464 /* The historical defaults for the flow control values are given below. */ 2465 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 2466 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 2467 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 2468 2469 /* PCIX Config space */ 2470 #define PCIX_COMMAND_REGISTER 0xE6 2471 #define PCIX_STATUS_REGISTER_LO 0xE8 2472 #define PCIX_STATUS_REGISTER_HI 0xEA 2473 2474 #define PCIX_COMMAND_MMRBC_MASK 0x000C 2475 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 2476 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 2477 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 2478 #define PCIX_STATUS_HI_MMRBC_4K 0x3 2479 #define PCIX_STATUS_HI_MMRBC_2K 0x2 2480 2481 2482 /* Number of bits required to shift right the "pause" bits from the 2483 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 2484 */ 2485 #define PAUSE_SHIFT 5 2486 2487 /* Number of bits required to shift left the "SWDPIO" bits from the 2488 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. 2489 */ 2490 #define SWDPIO_SHIFT 17 2491 2492 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the 2493 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. 2494 */ 2495 #define SWDPIO__EXT_SHIFT 4 2496 2497 /* Number of bits required to shift left the "ILOS" bit from the EEPROM 2498 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. 2499 */ 2500 #define ILOS_SHIFT 3 2501 2502 2503 #define RECEIVE_BUFFER_ALIGN_SIZE (256) 2504 2505 /* Number of milliseconds we wait for auto-negotiation to complete */ 2506 #define LINK_UP_TIMEOUT 500 2507 2508 /* Number of 100 microseconds we wait for PCI Express master disable */ 2509 #define MASTER_DISABLE_TIMEOUT 800 2510 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2511 #define AUTO_READ_DONE_TIMEOUT 10 2512 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2513 #define PHY_CFG_TIMEOUT 100 2514 2515 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2516 2517 /* The carrier extension symbol, as received by the NIC. */ 2518 #define CARRIER_EXTENSION 0x0F 2519 2520 /* TBI_ACCEPT macro definition: 2521 * 2522 * This macro requires: 2523 * adapter = a pointer to struct e1000_hw 2524 * status = the 8 bit status field of the RX descriptor with EOP set 2525 * error = the 8 bit error field of the RX descriptor with EOP set 2526 * length = the sum of all the length fields of the RX descriptors that 2527 * make up the current frame 2528 * last_byte = the last byte of the frame DMAed by the hardware 2529 * max_frame_length = the maximum frame length we want to accept. 2530 * min_frame_length = the minimum frame length we want to accept. 2531 * 2532 * This macro is a conditional that should be used in the interrupt 2533 * handler's Rx processing routine when RxErrors have been detected. 2534 * 2535 * Typical use: 2536 * ... 2537 * if (TBI_ACCEPT) { 2538 * accept_frame = TRUE; 2539 * e1000_tbi_adjust_stats(adapter, MacAddress); 2540 * frame_length--; 2541 * } else { 2542 * accept_frame = FALSE; 2543 * } 2544 * ... 2545 */ 2546 2547 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ 2548 ((adapter)->tbi_compatibility_on && \ 2549 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 2550 ((last_byte) == CARRIER_EXTENSION) && \ 2551 (((status) & E1000_RXD_STAT_VP) ? \ 2552 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ 2553 ((length) <= ((adapter)->max_frame_size + 1))) : \ 2554 (((length) > (adapter)->min_frame_size) && \ 2555 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 2556 2557 2558 /* Structures, enums, and macros for the PHY */ 2559 2560 /* Bit definitions for the Management Data IO (MDIO) and Management Data 2561 * Clock (MDC) pins in the Device Control Register. 2562 */ 2563 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 2564 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 2565 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 2566 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 2567 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 2568 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 2569 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 2570 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 2571 2572 /* PHY 1000 MII Register/Bit Definitions */ 2573 /* PHY Registers defined by IEEE */ 2574 #define PHY_CTRL 0x00 /* Control Register */ 2575 #define PHY_STATUS 0x01 /* Status Regiser */ 2576 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 2577 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 2578 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 2579 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 2580 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 2581 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 2582 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 2583 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 2584 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 2585 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 2586 2587 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 2588 #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 2589 2590 /* M88E1000 Specific Registers */ 2591 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 2592 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 2593 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 2594 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 2595 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 2596 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 2597 2598 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 2599 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 2600 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 2601 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 2602 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 2603 2604 #define IGP01E1000_IEEE_REGS_PAGE 0x0000 2605 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 2606 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 2607 2608 /* IGP01E1000 Specific Registers */ 2609 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 2610 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 2611 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 2612 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2613 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2614 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2615 #define IGP02E1000_PHY_POWER_MGMT 0x19 2616 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2617 2618 /* IGP01E1000 AGC Registers - stores the cable length values*/ 2619 #define IGP01E1000_PHY_AGC_A 0x1172 2620 #define IGP01E1000_PHY_AGC_B 0x1272 2621 #define IGP01E1000_PHY_AGC_C 0x1472 2622 #define IGP01E1000_PHY_AGC_D 0x1872 2623 2624 /* IGP02E1000 AGC Registers for cable length values */ 2625 #define IGP02E1000_PHY_AGC_A 0x11B1 2626 #define IGP02E1000_PHY_AGC_B 0x12B1 2627 #define IGP02E1000_PHY_AGC_C 0x14B1 2628 #define IGP02E1000_PHY_AGC_D 0x18B1 2629 2630 /* IGP01E1000 DSP Reset Register */ 2631 #define IGP01E1000_PHY_DSP_RESET 0x1F33 2632 #define IGP01E1000_PHY_DSP_SET 0x1F71 2633 #define IGP01E1000_PHY_DSP_FFE 0x1F35 2634 2635 #define IGP01E1000_PHY_CHANNEL_NUM 4 2636 #define IGP02E1000_PHY_CHANNEL_NUM 4 2637 2638 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 2639 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 2640 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 2641 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 2642 2643 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 2644 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 2645 2646 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 2647 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 2648 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 2649 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 2650 2651 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 2652 /* IGP01E1000 PCS Initialization register - stores the polarity status when 2653 * speed = 1000 Mbps. */ 2654 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 2655 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 2656 2657 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 2658 2659 /* Bits... 2660 * 15-5: page 2661 * 4-0: register offset 2662 */ 2663 #define GG82563_PAGE_SHIFT 5 2664 #define GG82563_REG(page, reg) \ 2665 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2666 #define GG82563_MIN_ALT_REG 30 2667 2668 /* GG82563 Specific Registers */ 2669 #define GG82563_PHY_SPEC_CTRL \ 2670 GG82563_REG(0, 16) /* PHY Specific Control */ 2671 #define GG82563_PHY_SPEC_STATUS \ 2672 GG82563_REG(0, 17) /* PHY Specific Status */ 2673 #define GG82563_PHY_INT_ENABLE \ 2674 GG82563_REG(0, 18) /* Interrupt Enable */ 2675 #define GG82563_PHY_SPEC_STATUS_2 \ 2676 GG82563_REG(0, 19) /* PHY Specific Status 2 */ 2677 #define GG82563_PHY_RX_ERR_CNTR \ 2678 GG82563_REG(0, 21) /* Receive Error Counter */ 2679 #define GG82563_PHY_PAGE_SELECT \ 2680 GG82563_REG(0, 22) /* Page Select */ 2681 #define GG82563_PHY_SPEC_CTRL_2 \ 2682 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 2683 #define GG82563_PHY_PAGE_SELECT_ALT \ 2684 GG82563_REG(0, 29) /* Alternate Page Select */ 2685 #define GG82563_PHY_TEST_CLK_CTRL \ 2686 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ 2687 2688 #define GG82563_PHY_MAC_SPEC_CTRL \ 2689 GG82563_REG(2, 21) /* MAC Specific Control Register */ 2690 #define GG82563_PHY_MAC_SPEC_CTRL_2 \ 2691 GG82563_REG(2, 26) /* MAC Specific Control 2 */ 2692 2693 #define GG82563_PHY_DSP_DISTANCE \ 2694 GG82563_REG(5, 26) /* DSP Distance */ 2695 2696 /* Page 193 - Port Control Registers */ 2697 #define GG82563_PHY_KMRN_MODE_CTRL \ 2698 GG82563_REG(193, 16) /* Kumeran Mode Control */ 2699 #define GG82563_PHY_PORT_RESET \ 2700 GG82563_REG(193, 17) /* Port Reset */ 2701 #define GG82563_PHY_REVISION_ID \ 2702 GG82563_REG(193, 18) /* Revision ID */ 2703 #define GG82563_PHY_DEVICE_ID \ 2704 GG82563_REG(193, 19) /* Device ID */ 2705 #define GG82563_PHY_PWR_MGMT_CTRL \ 2706 GG82563_REG(193, 20) /* Power Management Control */ 2707 #define GG82563_PHY_RATE_ADAPT_CTRL \ 2708 GG82563_REG(193, 25) /* Rate Adaptation Control */ 2709 2710 /* Page 194 - KMRN Registers */ 2711 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 2712 GG82563_REG(194, 16) /* FIFO's Control/Status */ 2713 #define GG82563_PHY_KMRN_CTRL \ 2714 GG82563_REG(194, 17) /* Control */ 2715 #define GG82563_PHY_INBAND_CTRL \ 2716 GG82563_REG(194, 18) /* Inband Control */ 2717 #define GG82563_PHY_KMRN_DIAGNOSTIC \ 2718 GG82563_REG(194, 19) /* Diagnostic */ 2719 #define GG82563_PHY_ACK_TIMEOUTS \ 2720 GG82563_REG(194, 20) /* Acknowledge Timeouts */ 2721 #define GG82563_PHY_ADV_ABILITY \ 2722 GG82563_REG(194, 21) /* Advertised Ability */ 2723 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 2724 GG82563_REG(194, 23) /* Link Partner Advertised Ability */ 2725 #define GG82563_PHY_ADV_NEXT_PAGE \ 2726 GG82563_REG(194, 24) /* Advertised Next Page */ 2727 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 2728 GG82563_REG(194, 25) /* Link Partner Advertised Next page */ 2729 #define GG82563_PHY_KMRN_MISC \ 2730 GG82563_REG(194, 26) /* Misc. */ 2731 2732 /* PHY Control Register */ 2733 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2734 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 2735 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 2736 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 2737 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 2738 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 2739 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 2740 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2741 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 2742 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 2743 2744 /* PHY Status Register */ 2745 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 2746 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 2747 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 2748 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 2749 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 2750 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 2751 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 2752 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 2753 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 2754 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 2755 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 2756 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 2757 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 2758 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 2759 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 2760 2761 /* Autoneg Advertisement Register */ 2762 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 2763 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 2764 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 2765 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 2766 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 2767 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 2768 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 2769 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 2770 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 2771 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2772 2773 /* Link Partner Ability Register (Base Page) */ 2774 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 2775 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 2776 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 2777 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 2778 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 2779 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 2780 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 2781 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 2782 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 2783 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 2784 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2785 2786 /* Autoneg Expansion Register */ 2787 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 2788 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 2789 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 2790 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 2791 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 2792 2793 /* Next Page TX Register */ 2794 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2795 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 2796 * of different NP 2797 */ 2798 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2799 * 0 = cannot comply with msg 2800 */ 2801 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2802 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2803 * 0 = sending last NP 2804 */ 2805 2806 /* Link Partner Next Page Register */ 2807 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2808 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 2809 * of different NP 2810 */ 2811 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2812 * 0 = cannot comply with msg 2813 */ 2814 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2815 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 2816 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2817 * 0 = sending last NP 2818 */ 2819 2820 /* 1000BASE-T Control Register */ 2821 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 2822 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 2823 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 2824 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 2825 /* 0=DTE device */ 2826 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 2827 /* 0=Configure PHY as Slave */ 2828 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 2829 /* 0=Automatic Master/Slave config */ 2830 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 2831 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 2832 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 2833 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 2834 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 2835 2836 /* 1000BASE-T Status Register */ 2837 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 2838 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 2839 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 2840 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 2841 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 2842 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 2843 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 2844 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 2845 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 2846 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 2847 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 2848 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 2849 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 2850 2851 /* Extended Status Register */ 2852 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 2853 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 2854 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 2855 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 2856 2857 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 2858 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 2859 2860 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 2861 /* (0=enable, 1=disable) */ 2862 2863 /* M88E1000 PHY Specific Control Register */ 2864 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 2865 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 2866 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 2867 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 2868 * 0=CLK125 toggling 2869 */ 2870 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 2871 /* Manual MDI configuration */ 2872 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 2873 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 2874 * 100BASE-TX/10BASE-T: 2875 * MDI Mode 2876 */ 2877 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 2878 * all speeds. 2879 */ 2880 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 2881 /* 1=Enable Extended 10BASE-T distance 2882 * (Lower 10BASE-T RX Threshold) 2883 * 0=Normal 10BASE-T RX Threshold */ 2884 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 2885 /* 1=5-Bit interface in 100BASE-TX 2886 * 0=MII interface in 100BASE-TX */ 2887 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 2888 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 2889 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 2890 2891 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 2892 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 2893 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 2894 2895 /* M88E1000 PHY Specific Status Register */ 2896 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 2897 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 2898 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 2899 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 2900 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 2901 * 3=110-140M;4=>140M */ 2902 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 2903 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 2904 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 2905 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 2906 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 2907 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 2908 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 2909 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 2910 2911 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 2912 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 2913 #define M88E1000_PSSR_MDIX_SHIFT 6 2914 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 2915 2916 /* M88E1000 Extended PHY Specific Control Register */ 2917 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 2918 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 2919 * Will assert lost lock and bring 2920 * link down if idle not seen 2921 * within 1ms in 1000BASE-T 2922 */ 2923 /* Number of times we will attempt to autonegotiate before downshifting if we 2924 * are the master */ 2925 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 2926 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 2927 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 2928 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 2929 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 2930 /* Number of times we will attempt to autonegotiate before downshifting if we 2931 * are the slave */ 2932 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 2933 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 2934 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 2935 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 2936 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 2937 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 2938 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2939 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2940 2941 /* M88EC018 Rev 2 specific DownShift settings */ 2942 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 2943 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 2944 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 2945 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 2946 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 2947 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 2948 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 2949 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 2950 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 2951 2952 /* IGP01E1000 Specific Port Config Register - R/W */ 2953 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2954 #define IGP01E1000_PSCFR_PRE_EN 0x0020 2955 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 2956 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 2957 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 2958 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 2959 2960 /* IGP01E1000 Specific Port Status Register - R/O */ 2961 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 2962 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 2963 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 2964 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 2965 #define IGP01E1000_PSSR_LINK_UP 0x0400 2966 #define IGP01E1000_PSSR_MDIX 0x0800 2967 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 2968 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 2969 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 2970 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 2971 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 2972 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 2973 2974 /* IGP01E1000 Specific Port Control Register - R/W */ 2975 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 2976 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 2977 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2978 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2979 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2980 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2981 2982 /* IGP01E1000 Specific Port Link Health Register */ 2983 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 2984 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 2985 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000 2986 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 2987 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 2988 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 2989 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 2990 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 2991 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 2992 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 2993 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008 2994 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004 2995 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002 2996 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001 2997 2998 /* IGP01E1000 Channel Quality Register */ 2999 #define IGP01E1000_MSE_CHANNEL_D 0x000F 3000 #define IGP01E1000_MSE_CHANNEL_C 0x00F0 3001 #define IGP01E1000_MSE_CHANNEL_B 0x0F00 3002 #define IGP01E1000_MSE_CHANNEL_A 0xF000 3003 3004 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 3005 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ 3006 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ 3007 3008 /* IGP01E1000 DSP reset macros */ 3009 #define DSP_RESET_ENABLE 0x0 3010 #define DSP_RESET_DISABLE 0x2 3011 #define E1000_MAX_DSP_RESETS 10 3012 3013 /* IGP01E1000 & IGP02E1000 AGC Registers */ 3014 3015 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 3016 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ 3017 3018 /* IGP02E1000 AGC Register Length 9-bit mask */ 3019 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 3020 3021 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 3022 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 3023 #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113 3024 3025 /* The precision error of the cable length is +/- 10 meters */ 3026 #define IGP01E1000_AGC_RANGE 10 3027 #define IGP02E1000_AGC_RANGE 15 3028 3029 /* IGP01E1000 PCS Initialization register */ 3030 /* bits 3:6 in the PCS registers stores the channels polarity */ 3031 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 3032 3033 /* IGP01E1000 GMII FIFO Register */ 3034 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 3035 * on Link-Up */ 3036 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 3037 3038 /* IGP01E1000 Analog Register */ 3039 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 3040 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 3041 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 3042 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 3043 3044 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 3045 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 3046 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 3047 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 3048 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 3049 3050 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 3051 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 3052 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 3053 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 3054 3055 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 3056 #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ 3057 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ 3058 #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ 3059 #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ 3060 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 3061 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ 3062 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ 3063 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ 3064 #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ 3065 #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 3066 #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ 3067 #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ 3068 #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ 3069 #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ 3070 #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ 3071 #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 3072 #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 3073 3074 /* PHY Specific Status Register (Page 0, Register 17) */ 3075 #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ 3076 #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ 3077 #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ 3078 #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ 3079 #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ 3080 #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ 3081 #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ 3082 #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ 3083 #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ 3084 #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ 3085 #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ 3086 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ 3087 #define GG82563_PSSR_SPEED_MASK 0xC000 3088 #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ 3089 #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ 3090 #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ 3091 3092 /* PHY Specific Status Register 2 (Page 0, Register 19) */ 3093 #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ 3094 #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ 3095 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ 3096 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ 3097 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ 3098 #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ 3099 #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ 3100 #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ 3101 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ 3102 #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ 3103 #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ 3104 #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ 3105 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ 3106 3107 /* PHY Specific Control Register 2 (Page 0, Register 26) */ 3108 #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */ 3109 #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C 3110 #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */ 3111 #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */ 3112 #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */ 3113 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */ 3114 #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */ 3115 #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 3116 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ 3117 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ 3118 3119 /* MAC Specific Control Register (Page 2, Register 21) */ 3120 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 3121 #define GG82563_MSCR_TX_CLK_MASK 0x0007 3122 #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 3123 #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 3124 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 3125 #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 3126 3127 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 3128 3129 /* DSP Distance Register (Page 5, Register 26) */ 3130 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; 3131 1 = 50-80M; 3132 2 = 80-110M; 3133 3 = 110-140M; 3134 4 = >140M */ 3135 3136 /* Kumeran Mode Control Register (Page 193, Register 16) */ 3137 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ 3138 #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ 3139 #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 3140 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 3141 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */ 3142 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 3143 3144 /* Power Management Control Register (Page 193, Register 20) */ 3145 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */ 3146 #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ 3147 #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ 3148 #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */ 3149 #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */ 3150 #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */ 3151 #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */ 3152 #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ 3153 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 3154 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ 3155 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ 3156 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ 3157 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ 3158 3159 /* In-Band Control Register (Page 194, Register 18) */ 3160 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ 3161 3162 3163 /* Bit definitions for valid PHY IDs. */ 3164 /* I = Integrated 3165 * E = External 3166 */ 3167 #define M88_VENDOR 0x0141 3168 #define M88E1000_E_PHY_ID 0x01410C50 3169 #define M88E1000_I_PHY_ID 0x01410C30 3170 #define M88E1011_I_PHY_ID 0x01410C20 3171 #define IGP01E1000_I_PHY_ID 0x02A80380 3172 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 3173 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 3174 #define M88E1011_I_REV_4 0x04 3175 #define M88E1111_I_PHY_ID 0x01410CC0 3176 #define L1LXT971A_PHY_ID 0x001378E0 3177 #define GG82563_E_PHY_ID 0x01410CA0 3178 3179 3180 /* Bits... 3181 * 15-5: page 3182 * 4-0: register offset 3183 */ 3184 #define PHY_PAGE_SHIFT 5 3185 #define PHY_REG(page, reg) \ 3186 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 3187 3188 #define IGP3_PHY_PORT_CTRL \ 3189 PHY_REG(769, 17) /* Port General Configuration */ 3190 #define IGP3_PHY_RATE_ADAPT_CTRL \ 3191 PHY_REG(769, 25) /* Rate Adapter Control Register */ 3192 3193 #define IGP3_KMRN_FIFO_CTRL_STATS \ 3194 PHY_REG(770, 16) /* KMRN FIFO's control/status register */ 3195 #define IGP3_KMRN_POWER_MNG_CTRL \ 3196 PHY_REG(770, 17) /* KMRN Power Management Control Register */ 3197 #define IGP3_KMRN_INBAND_CTRL \ 3198 PHY_REG(770, 18) /* KMRN Inband Control Register */ 3199 #define IGP3_KMRN_DIAG \ 3200 PHY_REG(770, 19) /* KMRN Diagnostic register */ 3201 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ 3202 #define IGP3_KMRN_ACK_TIMEOUT \ 3203 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ 3204 3205 #define IGP3_VR_CTRL \ 3206 PHY_REG(776, 18) /* Voltage regulator control register */ 3207 #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 3208 #define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ 3209 3210 #define IGP3_CAPABILITY \ 3211 PHY_REG(776, 19) /* IGP3 Capability Register */ 3212 3213 /* Capabilities for SKU Control */ 3214 #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ 3215 #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ 3216 #define IGP3_CAP_ASF 0x0004 /* Support ASF */ 3217 #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ 3218 #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ 3219 #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ 3220 #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ 3221 #define IGP3_CAP_RSS 0x0080 /* Support RSS */ 3222 #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ 3223 #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ 3224 3225 #define IGP3_PPC_JORDAN_EN 0x0001 3226 #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 3227 3228 #define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001 3229 #define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E 3230 #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 3231 #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 3232 3233 #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ 3234 #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ 3235 3236 #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) 3237 #define IGP3_KMRN_EC_DIS_INBAND 0x0080 3238 3239 #define IGP03E1000_E_PHY_ID 0x02A80390 3240 #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 3241 #define IFE_PLUS_E_PHY_ID 0x02A80320 3242 #define IFE_C_E_PHY_ID 0x02A80310 3243 3244 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ 3245 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ 3246 #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ 3247 #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ 3248 #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ 3249 #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ 3250 #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ 3251 #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ 3252 #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ 3253 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ 3254 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ 3255 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 3256 #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ 3257 3258 #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ 3259 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ 3260 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ 3261 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ 3262 #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ 3263 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ 3264 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ 3265 #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 3266 3267 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ 3268 #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ 3269 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ 3270 #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ 3271 #define IFE_PSC_FORCE_POLARITY_SHIFT 5 3272 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 3273 3274 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ 3275 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ 3276 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 3277 #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ 3278 #define IFE_PMC_MDIX_MODE_SHIFT 6 3279 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 3280 3281 #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ 3282 #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ 3283 #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ 3284 #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 3285 #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 3286 #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ 3287 #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ 3288 #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 3289 #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 3290 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 3291 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 3292 3293 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 3294 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 3295 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 3296 #define ICH_FLASH_SEG_SIZE_256 256 3297 #define ICH_FLASH_SEG_SIZE_4K 4096 3298 #define ICH_FLASH_SEG_SIZE_64K 65536 3299 3300 #define ICH_CYCLE_READ 0x0 3301 #define ICH_CYCLE_RESERVED 0x1 3302 #define ICH_CYCLE_WRITE 0x2 3303 #define ICH_CYCLE_ERASE 0x3 3304 3305 #define ICH_FLASH_GFPREG 0x0000 3306 #define ICH_FLASH_HSFSTS 0x0004 3307 #define ICH_FLASH_HSFCTL 0x0006 3308 #define ICH_FLASH_FADDR 0x0008 3309 #define ICH_FLASH_FDATA0 0x0010 3310 #define ICH_FLASH_FRACC 0x0050 3311 #define ICH_FLASH_FREG0 0x0054 3312 #define ICH_FLASH_FREG1 0x0058 3313 #define ICH_FLASH_FREG2 0x005C 3314 #define ICH_FLASH_FREG3 0x0060 3315 #define ICH_FLASH_FPR0 0x0074 3316 #define ICH_FLASH_FPR1 0x0078 3317 #define ICH_FLASH_SSFSTS 0x0090 3318 #define ICH_FLASH_SSFCTL 0x0092 3319 #define ICH_FLASH_PREOP 0x0094 3320 #define ICH_FLASH_OPTYPE 0x0096 3321 #define ICH_FLASH_OPMENU 0x0098 3322 3323 #define ICH_FLASH_REG_MAPSIZE 0x00A0 3324 #define ICH_FLASH_SECTOR_SIZE 4096 3325 #define ICH_GFPREG_BASE_MASK 0x1FFF 3326 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 3327 3328 /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 3329 /* Offset 04h HSFSTS */ 3330 union ich8_hws_flash_status { 3331 struct ich8_hsfsts { 3332 #ifdef E1000_BIG_ENDIAN 3333 uint16_t reserved2 :6; 3334 uint16_t fldesvalid :1; 3335 uint16_t flockdn :1; 3336 uint16_t flcdone :1; 3337 uint16_t flcerr :1; 3338 uint16_t dael :1; 3339 uint16_t berasesz :2; 3340 uint16_t flcinprog :1; 3341 uint16_t reserved1 :2; 3342 #else 3343 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */ 3344 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */ 3345 uint16_t dael :1; /* bit 2 Direct Access error Log */ 3346 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */ 3347 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */ 3348 uint16_t reserved1 :2; /* bit 13:6 Reserved */ 3349 uint16_t reserved2 :6; /* bit 13:6 Reserved */ 3350 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 3351 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */ 3352 #endif 3353 } hsf_status; 3354 uint16_t regval; 3355 }; 3356 3357 /* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 3358 /* Offset 06h FLCTL */ 3359 union ich8_hws_flash_ctrl { 3360 struct ich8_hsflctl { 3361 #ifdef E1000_BIG_ENDIAN 3362 uint16_t fldbcount :2; 3363 uint16_t flockdn :6; 3364 uint16_t flcgo :1; 3365 uint16_t flcycle :2; 3366 uint16_t reserved :5; 3367 #else 3368 uint16_t flcgo :1; /* 0 Flash Cycle Go */ 3369 uint16_t flcycle :2; /* 2:1 Flash Cycle */ 3370 uint16_t reserved :5; /* 7:3 Reserved */ 3371 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */ 3372 uint16_t flockdn :6; /* 15:10 Reserved */ 3373 #endif 3374 } hsf_ctrl; 3375 uint16_t regval; 3376 }; 3377 3378 /* ICH8 Flash Region Access Permissions */ 3379 union ich8_hws_flash_regacc { 3380 struct ich8_flracc { 3381 #ifdef E1000_BIG_ENDIAN 3382 uint32_t gmwag :8; 3383 uint32_t gmrag :8; 3384 uint32_t grwa :8; 3385 uint32_t grra :8; 3386 #else 3387 uint32_t grra :8; /* 0:7 GbE region Read Access */ 3388 uint32_t grwa :8; /* 8:15 GbE region Write Access */ 3389 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */ 3390 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */ 3391 #endif 3392 } hsf_flregacc; 3393 uint16_t regval; 3394 }; 3395 3396 /* Miscellaneous PHY bit definitions. */ 3397 #define PHY_PREAMBLE 0xFFFFFFFF 3398 #define PHY_SOF 0x01 3399 #define PHY_OP_READ 0x02 3400 #define PHY_OP_WRITE 0x01 3401 #define PHY_TURNAROUND 0x02 3402 #define PHY_PREAMBLE_SIZE 32 3403 #define MII_CR_SPEED_1000 0x0040 3404 #define MII_CR_SPEED_100 0x2000 3405 #define MII_CR_SPEED_10 0x0000 3406 #define E1000_PHY_ADDRESS 0x01 3407 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 3408 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 3409 #define PHY_REVISION_MASK 0xFFFFFFF0 3410 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 3411 #define REG4_SPEED_MASK 0x01E0 3412 #define REG9_SPEED_MASK 0x0300 3413 #define ADVERTISE_10_HALF 0x0001 3414 #define ADVERTISE_10_FULL 0x0002 3415 #define ADVERTISE_100_HALF 0x0004 3416 #define ADVERTISE_100_FULL 0x0008 3417 #define ADVERTISE_1000_HALF 0x0010 3418 #define ADVERTISE_1000_FULL 0x0020 3419 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 3420 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 3421 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 3422 3423 #endif /* _E1000_HW_H_ */ 3424 3425 /* 3426 * Local variables: 3427 * c-basic-offset: 8 3428 * c-indent-level: 8 3429 * tab-width: 8 3430 * End: 3431 */ 3432
