1 /* -*- Mode:C; c-basic-offset:4; -*- */ 2 3 /* Definitions for SiS ethernet controllers including 7014/7016 and 900 4 * References: 5 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support, 6 * preliminary Rev. 1.0 Jan. 14, 1998 7 * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support, 8 * preliminary Rev. 1.0 Nov. 10, 1998 9 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution, 10 * preliminary Rev. 1.0 Jan. 18, 1998 11 * http://www.sis.com.tw/support/databook.htm 12 */ 13 14 FILE_LICENCE ( GPL_ANY ); 15 16 /* MAC operationl registers of SiS 7016 and SiS 900 ethernet controller */ 17 /* The I/O extent, SiS 900 needs 256 bytes of io address */ 18 #define SIS900_TOTAL_SIZE 0x100 19 20 /* Symbolic offsets to registers. */ 21 enum sis900_registers { 22 cr=0x0, /* Command Register */ 23 cfg=0x4, /* Configuration Register */ 24 mear=0x8, /* EEPROM Access Register */ 25 ptscr=0xc, /* PCI Test Control Register */ 26 isr=0x10, /* Interrupt Status Register */ 27 imr=0x14, /* Interrupt Mask Register */ 28 ier=0x18, /* Interrupt Enable Register */ 29 epar=0x18, /* Enhanced PHY Access Register */ 30 txdp=0x20, /* Transmit Descriptor Pointer Register */ 31 txcfg=0x24, /* Transmit Configuration Register */ 32 rxdp=0x30, /* Receive Descriptor Pointer Register */ 33 rxcfg=0x34, /* Receive Configuration Register */ 34 flctrl=0x38, /* Flow Control Register */ 35 rxlen=0x3c, /* Receive Packet Length Register */ 36 rfcr=0x48, /* Receive Filter Control Register */ 37 rfdr=0x4C, /* Receive Filter Data Register */ 38 pmctrl=0xB0, /* Power Management Control Register */ 39 pmer=0xB4 /* Power Management Wake-up Event Register */ 40 }; 41 42 /* Symbolic names for bits in various registers */ 43 enum sis900_command_register_bits { 44 RELOAD = 0x00000400, 45 ACCESSMODE = 0x00000200, 46 RESET = 0x00000100, 47 SWI = 0x00000080, 48 RxRESET = 0x00000020, 49 TxRESET = 0x00000010, 50 RxDIS = 0x00000008, 51 RxENA = 0x00000004, 52 TxDIS = 0x00000002, 53 TxENA = 0x00000001 54 }; 55 56 enum sis900_configuration_register_bits { 57 DESCRFMT = 0x00000100, /* 7016 specific */ 58 REQALG = 0x00000080, 59 SB = 0x00000040, 60 POW = 0x00000020, 61 EXD = 0x00000010, 62 PESEL = 0x00000008, 63 LPM = 0x00000004, 64 BEM = 0x00000001, 65 RND_CNT = 0x00000400, 66 FAIR_BACKOFF = 0x00000200, 67 EDB_MASTER_EN = 0x00002000 68 }; 69 70 enum sis900_eeprom_access_reigster_bits { 71 MDC = 0x00000040, 72 MDDIR = 0x00000020, 73 MDIO = 0x00000010, /* 7016 specific */ 74 EECS = 0x00000008, 75 EECLK = 0x00000004, 76 EEDO = 0x00000002, 77 EEDI = 0x00000001 78 }; 79 80 enum sis900_interrupt_register_bits { 81 WKEVT = 0x10000000, 82 TxPAUSEEND = 0x08000000, 83 TxPAUSE = 0x04000000, 84 TxRCMP = 0x02000000, 85 RxRCMP = 0x01000000, 86 DPERR = 0x00800000, 87 SSERR = 0x00400000, 88 RMABT = 0x00200000, 89 RTABT = 0x00100000, 90 RxSOVR = 0x00010000, 91 HIBERR = 0x00008000, 92 SWINT = 0x00001000, 93 MIBINT = 0x00000800, 94 TxURN = 0x00000400, 95 TxIDLE = 0x00000200, 96 TxERR = 0x00000100, 97 TxDESC = 0x00000080, 98 TxOK = 0x00000040, 99 RxORN = 0x00000020, 100 RxIDLE = 0x00000010, 101 RxEARLY = 0x00000008, 102 RxERR = 0x00000004, 103 RxDESC = 0x00000002, 104 RxOK = 0x00000001 105 }; 106 107 enum sis900_interrupt_enable_reigster_bits { 108 IE = 0x00000001 109 }; 110 111 /* maximum dma burst fro transmission and receive*/ 112 #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */ 113 #define TxMXDMA_shift 20 114 #define RxMXDMA_shift 20 115 #define TX_DMA_BURST 0 116 #define RX_DMA_BURST 0 117 118 enum sis900_tx_rx_dma{ 119 DMA_BURST_512 = 0, DMA_BURST_64 = 5 120 }; 121 122 /* transmit FIFO threshholds */ 123 #define TX_FILL_THRESH 16 /* 1/4 FIFO size */ 124 #define TxFILLT_shift 8 125 #define TxDRNT_shift 0 126 #define TxDRNT_100 48 /* 3/4 FIFO size */ 127 #define TxDRNT_10 16 /* 1/2 FIFO size */ 128 129 enum sis900_transmit_config_register_bits { 130 TxCSI = 0x80000000, 131 TxHBI = 0x40000000, 132 TxMLB = 0x20000000, 133 TxATP = 0x10000000, 134 TxIFG = 0x0C000000, 135 TxFILLT = 0x00003F00, 136 TxDRNT = 0x0000003F 137 }; 138 139 /* recevie FIFO thresholds */ 140 #define RxDRNT_shift 1 141 #define RxDRNT_100 16 /* 1/2 FIFO size */ 142 #define RxDRNT_10 24 /* 3/4 FIFO size */ 143 144 enum sis900_reveive_config_register_bits { 145 RxAEP = 0x80000000, 146 RxARP = 0x40000000, 147 RxATX = 0x10000000, 148 RxAJAB = 0x08000000, 149 RxDRNT = 0x0000007F 150 }; 151 152 #define RFAA_shift 28 153 #define RFADDR_shift 16 154 155 enum sis900_receive_filter_control_register_bits { 156 RFEN = 0x80000000, 157 RFAAB = 0x40000000, 158 RFAAM = 0x20000000, 159 RFAAP = 0x10000000, 160 RFPromiscuous = (RFAAB|RFAAM|RFAAP) 161 }; 162 163 enum sis900_reveive_filter_data_mask { 164 RFDAT = 0x0000FFFF 165 }; 166 167 /* EEPROM Addresses */ 168 enum sis900_eeprom_address { 169 EEPROMSignature = 0x00, 170 EEPROMVendorID = 0x02, 171 EEPROMDeviceID = 0x03, 172 EEPROMMACAddr = 0x08, 173 EEPROMChecksum = 0x0b 174 }; 175 176 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */ 177 enum sis900_eeprom_command { 178 EEread = 0x0180, 179 EEwrite = 0x0140, 180 EEerase = 0x01C0, 181 EEwriteEnable = 0x0130, 182 EEwriteDisable = 0x0100, 183 EEeraseAll = 0x0120, 184 EEwriteAll = 0x0110, 185 EEaddrMask = 0x013F, 186 EEcmdShift = 16 187 }; 188 /* For SiS962 or SiS963, request the eeprom software access */ 189 enum sis96x_eeprom_command { 190 EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100 191 }; 192 193 /* Manamgement Data I/O (mdio) frame */ 194 #define MIIread 0x6000 195 #define MIIwrite 0x5002 196 #define MIIpmdShift 7 197 #define MIIregShift 2 198 #define MIIcmdLen 16 199 #define MIIcmdShift 16 200 201 /* Buffer Descriptor Status*/ 202 enum sis900_buffer_status { 203 OWN = 0x80000000, 204 MORE = 0x40000000, 205 INTR = 0x20000000, 206 SUPCRC = 0x10000000, 207 INCCRC = 0x10000000, 208 OK = 0x08000000, 209 DSIZE = 0x00000FFF 210 }; 211 212 /* Status for TX Buffers */ 213 enum sis900_tx_buffer_status { 214 ABORT = 0x04000000, 215 UNDERRUN = 0x02000000, 216 NOCARRIER = 0x01000000, 217 DEFERD = 0x00800000, 218 EXCDEFER = 0x00400000, 219 OWCOLL = 0x00200000, 220 EXCCOLL = 0x00100000, 221 COLCNT = 0x000F0000 222 }; 223 224 enum sis900_rx_bufer_status { 225 OVERRUN = 0x02000000, 226 DEST = 0x00800000, 227 BCAST = 0x01800000, 228 MCAST = 0x01000000, 229 UNIMATCH = 0x00800000, 230 TOOLONG = 0x00400000, 231 RUNT = 0x00200000, 232 RXISERR = 0x00100000, 233 CRCERR = 0x00080000, 234 FAERR = 0x00040000, 235 LOOPBK = 0x00020000, 236 RXCOL = 0x00010000 237 }; 238 239 /* MII register offsets */ 240 enum mii_registers { 241 MII_CONTROL = 0x0000, 242 MII_STATUS = 0x0001, 243 MII_PHY_ID0 = 0x0002, 244 MII_PHY_ID1 = 0x0003, 245 MII_ANADV = 0x0004, 246 MII_ANLPAR = 0x0005, 247 MII_ANEXT = 0x0006 248 }; 249 250 /* mii registers specific to SiS 900 */ 251 enum sis_mii_registers { 252 MII_CONFIG1 = 0x0010, 253 MII_CONFIG2 = 0x0011, 254 MII_STSOUT = 0x0012, 255 MII_MASK = 0x0013, 256 MII_RESV = 0x0014 257 }; 258 259 /* mii registers specific to AMD 79C901 */ 260 enum amd_mii_registers { 261 MII_STATUS_SUMMARY = 0x0018 262 }; 263 264 /* mii registers specific to ICS 1893 */ 265 enum ics_mii_registers { 266 MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012, 267 MII_EXTCTRL2 = 0x0013 268 }; 269 270 271 272 /* MII Control register bit definitions. */ 273 enum mii_control_register_bits { 274 MII_CNTL_FDX = 0x0100, 275 MII_CNTL_RST_AUTO = 0x0200, 276 MII_CNTL_ISOLATE = 0x0400, 277 MII_CNTL_PWRDWN = 0x0800, 278 MII_CNTL_AUTO = 0x1000, 279 MII_CNTL_SPEED = 0x2000, 280 MII_CNTL_LPBK = 0x4000, 281 MII_CNTL_RESET = 0x8000 282 }; 283 284 /* MII Status register bit */ 285 enum mii_status_register_bits { 286 MII_STAT_EXT = 0x0001, 287 MII_STAT_JAB = 0x0002, 288 MII_STAT_LINK = 0x0004, 289 MII_STAT_CAN_AUTO = 0x0008, 290 MII_STAT_FAULT = 0x0010, 291 MII_STAT_AUTO_DONE = 0x0020, 292 MII_STAT_CAN_T = 0x0800, 293 MII_STAT_CAN_T_FDX = 0x1000, 294 MII_STAT_CAN_TX = 0x2000, 295 MII_STAT_CAN_TX_FDX = 0x4000, 296 MII_STAT_CAN_T4 = 0x8000 297 }; 298 299 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */ 300 #define MII_ID1_MODEL 0x03F0 /* model number */ 301 #define MII_ID1_REV 0x000F /* model number */ 302 303 /* MII NWAY Register Bits ... 304 valid for the ANAR (Auto-Negotiation Advertisement) and 305 ANLPAR (Auto-Negotiation Link Partner) registers */ 306 enum mii_nway_register_bits { 307 MII_NWAY_NODE_SEL = 0x001f, 308 MII_NWAY_CSMA_CD = 0x0001, 309 MII_NWAY_T = 0x0020, 310 MII_NWAY_T_FDX = 0x0040, 311 MII_NWAY_TX = 0x0080, 312 MII_NWAY_TX_FDX = 0x0100, 313 MII_NWAY_T4 = 0x0200, 314 MII_NWAY_PAUSE = 0x0400, 315 MII_NWAY_RF = 0x2000, 316 MII_NWAY_ACK = 0x4000, 317 MII_NWAY_NP = 0x8000 318 }; 319 320 enum mii_stsout_register_bits { 321 MII_STSOUT_LINK_FAIL = 0x4000, 322 MII_STSOUT_SPD = 0x0080, 323 MII_STSOUT_DPLX = 0x0040 324 }; 325 326 enum mii_stsics_register_bits { 327 MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000, 328 MII_STSICS_LINKSTS = 0x0001 329 }; 330 331 enum mii_stssum_register_bits { 332 MII_STSSUM_LINK = 0x0008, 333 MII_STSSUM_DPLX = 0x0004, 334 MII_STSSUM_AUTO = 0x0002, 335 MII_STSSUM_SPD = 0x0001 336 }; 337 338 enum sis900_revision_id { 339 SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81, 340 SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83, 341 SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90, 342 SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03 343 }; 344 345 enum sis630_revision_id { 346 SIS630A0 = 0x00, SIS630A1 = 0x01, 347 SIS630B0 = 0x10, SIS630B1 = 0x11 348 }; 349 350 #define FDX_CAPABLE_DUPLEX_UNKNOWN 0 351 #define FDX_CAPABLE_HALF_SELECTED 1 352 #define FDX_CAPABLE_FULL_SELECTED 2 353 354 #define HW_SPEED_UNCONFIG 0 355 #define HW_SPEED_HOME 1 356 #define HW_SPEED_10_MBPS 10 357 #define HW_SPEED_100_MBPS 100 358 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS) 359 360 #define CRC_SIZE 4 361 #define MAC_HEADER_SIZE 14 362 363 #define TX_BUF_SIZE 1536 364 #define RX_BUF_SIZE 1536 365 366 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ 367 368 /* Time in ticks before concluding the transmitter is hung. */ 369 #define TX_TIMEOUT (4*TICKS_PER_SEC) 370 371 typedef struct _BufferDesc { 372 u32 link; 373 volatile u32 cmdsts; 374 u32 bufptr; 375 } BufferDesc; 376
