1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file This file implements the LiveInterval analysis pass. Given some 11 /// numbering of each the machine instructions (in this implemention depth-first 12 /// order) an interval [i, j) is said to be a live interval for register v if 13 /// there is no instruction with number j' > j such that v is live at j' and 14 /// there is no instruction with number i' < i such that v is live at i'. In 15 /// this implementation intervals can have holes, i.e. an interval might look 16 /// like [1,20), [50,65), [1000,1001). 17 // 18 //===----------------------------------------------------------------------===// 19 20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H 21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H 22 23 #include "llvm/ADT/IndexedMap.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/Analysis/AliasAnalysis.h" 26 #include "llvm/CodeGen/LiveInterval.h" 27 #include "llvm/CodeGen/MachineBasicBlock.h" 28 #include "llvm/CodeGen/MachineFunctionPass.h" 29 #include "llvm/CodeGen/SlotIndexes.h" 30 #include "llvm/Support/Allocator.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Target/TargetRegisterInfo.h" 33 #include <cmath> 34 35 namespace llvm { 36 37 extern cl::opt<bool> UseSegmentSetForPhysRegs; 38 39 class BitVector; 40 class BlockFrequency; 41 class LiveRangeCalc; 42 class LiveVariables; 43 class MachineDominatorTree; 44 class MachineLoopInfo; 45 class TargetRegisterInfo; 46 class MachineRegisterInfo; 47 class TargetInstrInfo; 48 class TargetRegisterClass; 49 class VirtRegMap; 50 class MachineBlockFrequencyInfo; 51 52 class LiveIntervals : public MachineFunctionPass { 53 MachineFunction* MF; 54 MachineRegisterInfo* MRI; 55 const TargetRegisterInfo* TRI; 56 const TargetInstrInfo* TII; 57 AliasAnalysis *AA; 58 SlotIndexes* Indexes; 59 MachineDominatorTree *DomTree; 60 LiveRangeCalc *LRCalc; 61 62 /// Special pool allocator for VNInfo's (LiveInterval val#). 63 VNInfo::Allocator VNInfoAllocator; 64 65 /// Live interval pointers for all the virtual registers. 66 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals; 67 68 /// Sorted list of instructions with register mask operands. Always use the 69 /// 'r' slot, RegMasks are normal clobbers, not early clobbers. 70 SmallVector<SlotIndex, 8> RegMaskSlots; 71 72 /// This vector is parallel to RegMaskSlots, it holds a pointer to the 73 /// corresponding register mask. This pointer can be recomputed as: 74 /// 75 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]); 76 /// unsigned OpNum = findRegMaskOperand(MI); 77 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask(); 78 /// 79 /// This is kept in a separate vector partly because some standard 80 /// libraries don't support lower_bound() with mixed objects, partly to 81 /// improve locality when searching in RegMaskSlots. 82 /// Also see the comment in LiveInterval::find(). 83 SmallVector<const uint32_t*, 8> RegMaskBits; 84 85 /// For each basic block number, keep (begin, size) pairs indexing into the 86 /// RegMaskSlots and RegMaskBits arrays. 87 /// Note that basic block numbers may not be layout contiguous, that's why 88 /// we can't just keep track of the first register mask in each basic 89 /// block. 90 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks; 91 92 /// Keeps a live range set for each register unit to track fixed physreg 93 /// interference. 94 SmallVector<LiveRange*, 0> RegUnitRanges; 95 96 public: 97 static char ID; 98 LiveIntervals(); 99 ~LiveIntervals() override; 100 101 /// Calculate the spill weight to assign to a single instruction. 102 static float getSpillWeight(bool isDef, bool isUse, 103 const MachineBlockFrequencyInfo *MBFI, 104 const MachineInstr &Instr); 105 106 LiveInterval &getInterval(unsigned Reg) { 107 if (hasInterval(Reg)) 108 return *VirtRegIntervals[Reg]; 109 else 110 return createAndComputeVirtRegInterval(Reg); 111 } 112 113 const LiveInterval &getInterval(unsigned Reg) const { 114 return const_cast<LiveIntervals*>(this)->getInterval(Reg); 115 } 116 117 bool hasInterval(unsigned Reg) const { 118 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; 119 } 120 121 /// Interval creation. 122 LiveInterval &createEmptyInterval(unsigned Reg) { 123 assert(!hasInterval(Reg) && "Interval already exists!"); 124 VirtRegIntervals.grow(Reg); 125 VirtRegIntervals[Reg] = createInterval(Reg); 126 return *VirtRegIntervals[Reg]; 127 } 128 129 LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) { 130 LiveInterval &LI = createEmptyInterval(Reg); 131 computeVirtRegInterval(LI); 132 return LI; 133 } 134 135 /// Interval removal. 136 void removeInterval(unsigned Reg) { 137 delete VirtRegIntervals[Reg]; 138 VirtRegIntervals[Reg] = nullptr; 139 } 140 141 /// Given a register and an instruction, adds a live segment from that 142 /// instruction to the end of its MBB. 143 LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, 144 MachineInstr &startInst); 145 146 /// After removing some uses of a register, shrink its live range to just 147 /// the remaining uses. This method does not compute reaching defs for new 148 /// uses, and it doesn't remove dead defs. 149 /// Dead PHIDef values are marked as unused. New dead machine instructions 150 /// are added to the dead vector. Returns true if the interval may have been 151 /// separated into multiple connected components. 152 bool shrinkToUses(LiveInterval *li, 153 SmallVectorImpl<MachineInstr*> *dead = nullptr); 154 155 /// Specialized version of 156 /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead) 157 /// that works on a subregister live range and only looks at uses matching 158 /// the lane mask of the subregister range. 159 /// This may leave the subrange empty which needs to be cleaned up with 160 /// LiveInterval::removeEmptySubranges() afterwards. 161 void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg); 162 163 /// Extend the live range \p LR to reach all points in \p Indices. The 164 /// points in the \p Indices array must be jointly dominated by the union 165 /// of the existing defs in \p LR and points in \p Undefs. 166 /// 167 /// PHI-defs are added as needed to maintain SSA form. 168 /// 169 /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR 170 /// will be extended to be live out of the basic block. 171 /// If a SlotIndex in \p Indices is jointy dominated only by points in 172 /// \p Undefs, the live range will not be extended to that point. 173 /// 174 /// See also LiveRangeCalc::extend(). 175 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices, 176 ArrayRef<SlotIndex> Undefs); 177 178 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) { 179 extendToIndices(LR, Indices, /*Undefs=*/{}); 180 } 181 182 /// If \p LR has a live value at \p Kill, prune its live range by removing 183 /// any liveness reachable from Kill. Add live range end points to 184 /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the 185 /// value's live range. 186 /// 187 /// Calling pruneValue() and extendToIndices() can be used to reconstruct 188 /// SSA form after adding defs to a virtual register. 189 void pruneValue(LiveRange &LR, SlotIndex Kill, 190 SmallVectorImpl<SlotIndex> *EndPoints); 191 192 /// This function should be used. Its intend is to tell you that 193 /// you are doing something wrong if you call pruveValue directly on a 194 /// LiveInterval. Indeed, you are supposed to call pruneValue on the main 195 /// LiveRange and all the LiveRange of the subranges if any. 196 LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex, 197 SmallVectorImpl<SlotIndex> *) { 198 llvm_unreachable( 199 "Use pruneValue on the main LiveRange and on each subrange"); 200 } 201 202 SlotIndexes *getSlotIndexes() const { 203 return Indexes; 204 } 205 206 AliasAnalysis *getAliasAnalysis() const { 207 return AA; 208 } 209 210 /// Returns true if the specified machine instr has been removed or was 211 /// never entered in the map. 212 bool isNotInMIMap(const MachineInstr &Instr) const { 213 return !Indexes->hasIndex(Instr); 214 } 215 216 /// Returns the base index of the given instruction. 217 SlotIndex getInstructionIndex(const MachineInstr &Instr) const { 218 return Indexes->getInstructionIndex(Instr); 219 } 220 221 /// Returns the instruction associated with the given index. 222 MachineInstr* getInstructionFromIndex(SlotIndex index) const { 223 return Indexes->getInstructionFromIndex(index); 224 } 225 226 /// Return the first index in the given basic block. 227 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const { 228 return Indexes->getMBBStartIdx(mbb); 229 } 230 231 /// Return the last index in the given basic block. 232 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const { 233 return Indexes->getMBBEndIdx(mbb); 234 } 235 236 bool isLiveInToMBB(const LiveRange &LR, 237 const MachineBasicBlock *mbb) const { 238 return LR.liveAt(getMBBStartIdx(mbb)); 239 } 240 241 bool isLiveOutOfMBB(const LiveRange &LR, 242 const MachineBasicBlock *mbb) const { 243 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); 244 } 245 246 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { 247 return Indexes->getMBBFromIndex(index); 248 } 249 250 void insertMBBInMaps(MachineBasicBlock *MBB) { 251 Indexes->insertMBBInMaps(MBB); 252 assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() && 253 "Blocks must be added in order."); 254 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0)); 255 } 256 257 SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) { 258 return Indexes->insertMachineInstrInMaps(MI); 259 } 260 261 void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B, 262 MachineBasicBlock::iterator E) { 263 for (MachineBasicBlock::iterator I = B; I != E; ++I) 264 Indexes->insertMachineInstrInMaps(*I); 265 } 266 267 void RemoveMachineInstrFromMaps(MachineInstr &MI) { 268 Indexes->removeMachineInstrFromMaps(MI); 269 } 270 271 SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) { 272 return Indexes->replaceMachineInstrInMaps(MI, NewMI); 273 } 274 275 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; } 276 277 void getAnalysisUsage(AnalysisUsage &AU) const override; 278 void releaseMemory() override; 279 280 /// Pass entry point; Calculates LiveIntervals. 281 bool runOnMachineFunction(MachineFunction&) override; 282 283 /// Implement the dump method. 284 void print(raw_ostream &O, const Module* = nullptr) const override; 285 286 /// If LI is confined to a single basic block, return a pointer to that 287 /// block. If LI is live in to or out of any block, return NULL. 288 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const; 289 290 /// Returns true if VNI is killed by any PHI-def values in LI. 291 /// This may conservatively return true to avoid expensive computations. 292 bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const; 293 294 /// Add kill flags to any instruction that kills a virtual register. 295 void addKillFlags(const VirtRegMap*); 296 297 /// Call this method to notify LiveIntervals that instruction \p MI has been 298 /// moved within a basic block. This will update the live intervals for all 299 /// operands of \p MI. Moves between basic blocks are not supported. 300 /// 301 /// \param UpdateFlags Update live intervals for nonallocatable physregs. 302 void handleMove(MachineInstr &MI, bool UpdateFlags = false); 303 304 /// Update intervals for operands of \p MI so that they begin/end on the 305 /// SlotIndex for \p BundleStart. 306 /// 307 /// \param UpdateFlags Update live intervals for nonallocatable physregs. 308 /// 309 /// Requires MI and BundleStart to have SlotIndexes, and assumes 310 /// existing liveness is accurate. BundleStart should be the first 311 /// instruction in the Bundle. 312 void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart, 313 bool UpdateFlags = false); 314 315 /// Update live intervals for instructions in a range of iterators. It is 316 /// intended for use after target hooks that may insert or remove 317 /// instructions, and is only efficient for a small number of instructions. 318 /// 319 /// OrigRegs is a vector of registers that were originally used by the 320 /// instructions in the range between the two iterators. 321 /// 322 /// Currently, the only only changes that are supported are simple removal 323 /// and addition of uses. 324 void repairIntervalsInRange(MachineBasicBlock *MBB, 325 MachineBasicBlock::iterator Begin, 326 MachineBasicBlock::iterator End, 327 ArrayRef<unsigned> OrigRegs); 328 329 // Register mask functions. 330 // 331 // Machine instructions may use a register mask operand to indicate that a 332 // large number of registers are clobbered by the instruction. This is 333 // typically used for calls. 334 // 335 // For compile time performance reasons, these clobbers are not recorded in 336 // the live intervals for individual physical registers. Instead, 337 // LiveIntervalAnalysis maintains a sorted list of instructions with 338 // register mask operands. 339 340 /// Returns a sorted array of slot indices of all instructions with 341 /// register mask operands. 342 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } 343 344 /// Returns a sorted array of slot indices of all instructions with register 345 /// mask operands in the basic block numbered \p MBBNum. 346 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const { 347 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum]; 348 return getRegMaskSlots().slice(P.first, P.second); 349 } 350 351 /// Returns an array of register mask pointers corresponding to 352 /// getRegMaskSlots(). 353 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; } 354 355 /// Returns an array of mask pointers corresponding to 356 /// getRegMaskSlotsInBlock(MBBNum). 357 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const { 358 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum]; 359 return getRegMaskBits().slice(P.first, P.second); 360 } 361 362 /// Test if \p LI is live across any register mask instructions, and 363 /// compute a bit mask of physical registers that are not clobbered by any 364 /// of them. 365 /// 366 /// Returns false if \p LI doesn't cross any register mask instructions. In 367 /// that case, the bit vector is not filled in. 368 bool checkRegMaskInterference(LiveInterval &LI, 369 BitVector &UsableRegs); 370 371 // Register unit functions. 372 // 373 // Fixed interference occurs when MachineInstrs use physregs directly 374 // instead of virtual registers. This typically happens when passing 375 // arguments to a function call, or when instructions require operands in 376 // fixed registers. 377 // 378 // Each physreg has one or more register units, see MCRegisterInfo. We 379 // track liveness per register unit to handle aliasing registers more 380 // efficiently. 381 382 /// Return the live range for register unit \p Unit. It will be computed if 383 /// it doesn't exist. 384 LiveRange &getRegUnit(unsigned Unit) { 385 LiveRange *LR = RegUnitRanges[Unit]; 386 if (!LR) { 387 // Compute missing ranges on demand. 388 // Use segment set to speed-up initial computation of the live range. 389 RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs); 390 computeRegUnitRange(*LR, Unit); 391 } 392 return *LR; 393 } 394 395 /// Return the live range for register unit \p Unit if it has already been 396 /// computed, or nullptr if it hasn't been computed yet. 397 LiveRange *getCachedRegUnit(unsigned Unit) { 398 return RegUnitRanges[Unit]; 399 } 400 401 const LiveRange *getCachedRegUnit(unsigned Unit) const { 402 return RegUnitRanges[Unit]; 403 } 404 405 /// Remove computed live range for register unit \p Unit. Subsequent uses 406 /// should rely on on-demand recomputation. 407 void removeRegUnit(unsigned Unit) { 408 delete RegUnitRanges[Unit]; 409 RegUnitRanges[Unit] = nullptr; 410 } 411 412 /// Remove value numbers and related live segments starting at position 413 /// \p Pos that are part of any liverange of physical register \p Reg or one 414 /// of its subregisters. 415 void removePhysRegDefAt(unsigned Reg, SlotIndex Pos); 416 417 /// Remove value number and related live segments of \p LI and its subranges 418 /// that start at position \p Pos. 419 void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos); 420 421 /// Split separate components in LiveInterval \p LI into separate intervals. 422 void splitSeparateComponents(LiveInterval &LI, 423 SmallVectorImpl<LiveInterval*> &SplitLIs); 424 425 /// For live interval \p LI with correct SubRanges construct matching 426 /// information for the main live range. Expects the main live range to not 427 /// have any segments or value numbers. 428 void constructMainRangeFromSubranges(LiveInterval &LI); 429 430 private: 431 /// Compute live intervals for all virtual registers. 432 void computeVirtRegs(); 433 434 /// Compute RegMaskSlots and RegMaskBits. 435 void computeRegMasks(); 436 437 /// Walk the values in \p LI and check for dead values: 438 /// - Dead PHIDef values are marked as unused. 439 /// - Dead operands are marked as such. 440 /// - Completely dead machine instructions are added to the \p dead vector 441 /// if it is not nullptr. 442 /// Returns true if any PHI value numbers have been removed which may 443 /// have separated the interval into multiple connected components. 444 bool computeDeadValues(LiveInterval &LI, 445 SmallVectorImpl<MachineInstr*> *dead); 446 447 static LiveInterval* createInterval(unsigned Reg); 448 449 void printInstrs(raw_ostream &O) const; 450 void dumpInstrs() const; 451 452 void computeLiveInRegUnits(); 453 void computeRegUnitRange(LiveRange&, unsigned Unit); 454 void computeVirtRegInterval(LiveInterval&); 455 456 457 /// Helper function for repairIntervalsInRange(), walks backwards and 458 /// creates/modifies live segments in \p LR to match the operands found. 459 /// Only full operands or operands with subregisters matching \p LaneMask 460 /// are considered. 461 void repairOldRegInRange(MachineBasicBlock::iterator Begin, 462 MachineBasicBlock::iterator End, 463 const SlotIndex endIdx, LiveRange &LR, 464 unsigned Reg, 465 LaneBitmask LaneMask = LaneBitmask::getAll()); 466 467 class HMEditor; 468 }; 469 } // End llvm namespace 470 471 #endif 472