1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target-independent interfaces used by SelectionDAG 11 // instruction selection generators. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // Selection DAG Type Constraint definitions. 17 // 18 // Note that the semantics of these constraints are hard coded into tblgen. To 19 // modify or add constraints, you have to hack tblgen. 20 // 21 22 class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24 } 25 26 // SDTCisVT - The specified operand has exactly this VT. 27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29 } 30 31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33 // SDTCisInt - The specified operand has integer type. 34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36 // SDTCisFP - The specified operand has floating-point type. 37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39 // SDTCisVec - The specified operand has a vector type. 40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42 // SDTCisSameAs - The two specified operands have identical types. 43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45 } 46 47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48 // smaller than the 'Other' operand. 49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51 } 52 53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55 } 56 57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58 /// type as the element type of OtherOp, which is a vector type. 59 class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62 } 63 64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65 /// with length less that of OtherOp, which is a vector type. 66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69 } 70 71 // SDTCVecEltisVT - The specified operand is vector type with element type 72 // of VT. 73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 74 ValueType VT = vt; 75 } 76 77 // SDTCisSameNumEltsAs - The two specified operands have identical number 78 // of elements. 79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 80 int OtherOperandNum = OtherOp; 81 } 82 83 // SDTCisSameSizeAs - The two specified operands have identical size. 84 class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 85 int OtherOperandNum = OtherOp; 86 } 87 88 //===----------------------------------------------------------------------===// 89 // Selection DAG Type Profile definitions. 90 // 91 // These use the constraints defined above to describe the type requirements of 92 // the various nodes. These are not hard coded into tblgen, allowing targets to 93 // add their own if needed. 94 // 95 96 // SDTypeProfile - This profile describes the type requirements of a Selection 97 // DAG node. 98 class SDTypeProfile<int numresults, int numoperands, 99 list<SDTypeConstraint> constraints> { 100 int NumResults = numresults; 101 int NumOperands = numoperands; 102 list<SDTypeConstraint> Constraints = constraints; 103 } 104 105 // Builtin profiles. 106 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 107 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 108 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 109 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 110 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 111 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 112 113 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 115 ]>; 116 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 117 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 118 ]>; 119 def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 120 SDTCisSameAs<0, 1>, SDTCisInt<2> 121 ]>; 122 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 123 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 124 ]>; 125 126 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 127 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 128 ]>; 129 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 130 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 131 ]>; 132 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 133 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 134 ]>; 135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 136 SDTCisSameAs<0, 1>, SDTCisInt<0> 137 ]>; 138 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 139 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 140 ]>; 141 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 142 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 143 ]>; 144 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 145 SDTCisSameAs<0, 1>, SDTCisFP<0> 146 ]>; 147 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 148 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 149 ]>; 150 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 151 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 152 ]>; 153 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 154 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 155 ]>; 156 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 157 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 158 ]>; 159 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 160 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 161 SDTCisVTSmallerThanOp<2, 1> 162 ]>; 163 def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 164 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 165 SDTCisOpSmallerThanOp<1, 0>, SDTCisSameSizeAs<0,1> 166 ]>; 167 168 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 169 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 170 ]>; 171 172 def SDTSelect : SDTypeProfile<1, 3, [ // select 173 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 174 ]>; 175 176 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 177 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 178 ]>; 179 180 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 181 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 182 SDTCisVT<5, OtherVT> 183 ]>; 184 185 def SDTBr : SDTypeProfile<0, 1, [ // br 186 SDTCisVT<0, OtherVT> 187 ]>; 188 189 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 190 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 191 ]>; 192 193 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 194 SDTCisInt<0>, SDTCisVT<1, OtherVT> 195 ]>; 196 197 def SDTBrind : SDTypeProfile<0, 1, [ // brind 198 SDTCisPtrTy<0> 199 ]>; 200 201 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 202 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 203 ]>; 204 205 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 206 207 def SDTLoad : SDTypeProfile<1, 1, [ // load 208 SDTCisPtrTy<1> 209 ]>; 210 211 def SDTStore : SDTypeProfile<0, 2, [ // store 212 SDTCisPtrTy<1> 213 ]>; 214 215 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 216 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 217 ]>; 218 219 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store 220 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2> 221 ]>; 222 223 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load 224 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 225 SDTCisSameNumEltsAs<0, 2> 226 ]>; 227 228 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather 229 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>, 230 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1> 231 ]>; 232 233 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter 234 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>, 235 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3> 236 ]>; 237 238 def SDTVecShuffle : SDTypeProfile<1, 2, [ 239 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 240 ]>; 241 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 242 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 243 ]>; 244 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 245 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 246 ]>; 247 248 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 249 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 250 ]>; 251 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 252 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 253 ]>; 254 255 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 256 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 257 ]>; 258 259 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 260 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 261 SDTCisInt<0> 262 ]>; 263 def SDTAtomicFence : SDTypeProfile<0, 2, [ 264 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 265 ]>; 266 def SDTAtomic3 : SDTypeProfile<1, 3, [ 267 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 268 ]>; 269 def SDTAtomic2 : SDTypeProfile<1, 2, [ 270 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 271 ]>; 272 def SDTAtomicStore : SDTypeProfile<0, 2, [ 273 SDTCisPtrTy<0>, SDTCisInt<1> 274 ]>; 275 def SDTAtomicLoad : SDTypeProfile<1, 1, [ 276 SDTCisInt<0>, SDTCisPtrTy<1> 277 ]>; 278 279 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 280 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 281 ]>; 282 283 class SDCallSeqStart<list<SDTypeConstraint> constraints> : 284 SDTypeProfile<0, 1, constraints>; 285 class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 286 SDTypeProfile<0, 2, constraints>; 287 288 //===----------------------------------------------------------------------===// 289 // Selection DAG Node Properties. 290 // 291 // Note: These are hard coded into tblgen. 292 // 293 class SDNodeProperty; 294 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 295 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 296 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 297 def SDNPOutGlue : SDNodeProperty; // Write a flag result 298 def SDNPInGlue : SDNodeProperty; // Read a flag operand 299 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 300 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 301 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 302 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 303 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 304 def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 305 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 306 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 307 308 //===----------------------------------------------------------------------===// 309 // Selection DAG Pattern Operations 310 class SDPatternOperator { 311 list<SDNodeProperty> Properties = []; 312 } 313 314 //===----------------------------------------------------------------------===// 315 // Selection DAG Node definitions. 316 // 317 class SDNode<string opcode, SDTypeProfile typeprof, 318 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 319 : SDPatternOperator { 320 string Opcode = opcode; 321 string SDClass = sdclass; 322 let Properties = props; 323 SDTypeProfile TypeProfile = typeprof; 324 } 325 326 // Special TableGen-recognized dag nodes 327 def set; 328 def implicit; 329 def node; 330 def srcvalue; 331 332 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 333 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 334 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 335 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 336 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 337 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 338 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 339 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 340 "GlobalAddressSDNode">; 341 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 342 "GlobalAddressSDNode">; 343 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 344 "GlobalAddressSDNode">; 345 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 346 "GlobalAddressSDNode">; 347 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 348 "ConstantPoolSDNode">; 349 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 350 "ConstantPoolSDNode">; 351 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 352 "JumpTableSDNode">; 353 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 354 "JumpTableSDNode">; 355 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 356 "FrameIndexSDNode">; 357 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 358 "FrameIndexSDNode">; 359 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 360 "ExternalSymbolSDNode">; 361 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 362 "ExternalSymbolSDNode">; 363 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 364 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 365 "BlockAddressSDNode">; 366 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 367 "BlockAddressSDNode">; 368 369 def add : SDNode<"ISD::ADD" , SDTIntBinOp , 370 [SDNPCommutative, SDNPAssociative]>; 371 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 372 def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 373 [SDNPCommutative, SDNPAssociative]>; 374 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 375 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 376 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 377 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 378 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 379 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 380 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 381 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 382 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 383 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 384 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 385 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 386 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 387 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 388 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 389 def and : SDNode<"ISD::AND" , SDTIntBinOp, 390 [SDNPCommutative, SDNPAssociative]>; 391 def or : SDNode<"ISD::OR" , SDTIntBinOp, 392 [SDNPCommutative, SDNPAssociative]>; 393 def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 394 [SDNPCommutative, SDNPAssociative]>; 395 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 396 [SDNPCommutative, SDNPOutGlue]>; 397 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 398 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 399 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 400 [SDNPOutGlue]>; 401 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 402 [SDNPOutGlue, SDNPInGlue]>; 403 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 404 [SDNPCommutative, SDNPAssociative]>; 405 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 406 [SDNPCommutative, SDNPAssociative]>; 407 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 408 [SDNPCommutative, SDNPAssociative]>; 409 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 410 [SDNPCommutative, SDNPAssociative]>; 411 412 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 413 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 414 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 415 416 def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 417 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 418 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 419 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 420 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 421 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 422 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 423 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 424 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 425 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 426 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 427 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 428 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 429 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 430 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 431 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 432 433 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 434 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 435 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 436 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 437 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 438 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 439 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; 440 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 441 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 442 [SDNPCommutative, SDNPAssociative]>; 443 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 444 [SDNPCommutative, SDNPAssociative]>; 445 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>; 446 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>; 447 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 448 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 449 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 450 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 451 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 452 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 453 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 454 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 455 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 456 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 457 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 458 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 459 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 460 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 461 def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 462 463 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 464 def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 465 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 466 467 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 468 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 469 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 470 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 471 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 472 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 473 474 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 475 def select : SDNode<"ISD::SELECT" , SDTSelect>; 476 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 477 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 478 479 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 480 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 481 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 482 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 483 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 484 [SDNPHasChain, SDNPSideEffect]>; 485 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 486 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone, 487 [SDNPHasChain, SDNPSideEffect]>; 488 489 def trap : SDNode<"ISD::TRAP" , SDTNone, 490 [SDNPHasChain, SDNPSideEffect]>; 491 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 492 [SDNPHasChain, SDNPSideEffect]>; 493 494 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 495 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 496 SDNPMemOperand]>; 497 498 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 499 [SDNPHasChain, SDNPSideEffect]>; 500 501 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 502 [SDNPHasChain, SDNPSideEffect]>; 503 504 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 505 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 506 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 507 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 508 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 509 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 510 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 511 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 512 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 513 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 514 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 515 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 516 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 517 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 518 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 519 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 520 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 521 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 522 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 523 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 524 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 525 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 526 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 527 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 528 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 529 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 530 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 531 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 532 533 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore, 534 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 535 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad, 536 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 537 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter, 538 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 539 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, 540 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 541 542 // Do not use ld, st directly. Use load, extload, sextload, zextload, store, 543 // and truncst (see below). 544 def ld : SDNode<"ISD::LOAD" , SDTLoad, 545 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 546 def st : SDNode<"ISD::STORE" , SDTStore, 547 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 548 def ist : SDNode<"ISD::STORE" , SDTIStore, 549 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 550 551 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 552 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 553 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 554 []>; 555 556 // vector_extract/vector_insert are deprecated. extractelt/insertelt 557 // are preferred. 558 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 559 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 560 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 561 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 562 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 563 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 564 565 // This operator does not do subvector type checking. The ARM 566 // backend, at least, needs it. 567 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 568 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 569 []>; 570 571 // This operator does subvector type checking. 572 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 573 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 574 575 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 576 // these internally. Don't reference these directly. 577 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 578 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 579 [SDNPHasChain]>; 580 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 581 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 582 [SDNPHasChain]>; 583 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 584 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 585 586 def SDT_assertext : SDTypeProfile<1, 1, 587 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 588 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>; 589 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>; 590 591 592 //===----------------------------------------------------------------------===// 593 // Selection DAG Condition Codes 594 595 class CondCode; // ISD::CondCode enums 596 def SETOEQ : CondCode; def SETOGT : CondCode; 597 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 598 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 599 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 600 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 601 602 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 603 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 604 605 606 //===----------------------------------------------------------------------===// 607 // Selection DAG Node Transformation Functions. 608 // 609 // This mechanism allows targets to manipulate nodes in the output DAG once a 610 // match has been formed. This is typically used to manipulate immediate 611 // values. 612 // 613 class SDNodeXForm<SDNode opc, code xformFunction> { 614 SDNode Opcode = opc; 615 code XFormFunction = xformFunction; 616 } 617 618 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 619 620 //===----------------------------------------------------------------------===// 621 // PatPred Subclasses. 622 // 623 // These allow specifying different sorts of predicates that control whether a 624 // node is matched. 625 // 626 class PatPred; 627 628 class CodePatPred<code predicate> : PatPred { 629 code PredicateCode = predicate; 630 } 631 632 633 //===----------------------------------------------------------------------===// 634 // Selection DAG Pattern Fragments. 635 // 636 // Pattern fragments are reusable chunks of dags that match specific things. 637 // They can take arguments and have C++ predicates that control whether they 638 // match. They are intended to make the patterns for common instructions more 639 // compact and readable. 640 // 641 642 /// PatFrag - Represents a pattern fragment. This can match something on the 643 /// DAG, from a single node to multiple nested other fragments. 644 /// 645 class PatFrag<dag ops, dag frag, code pred = [{}], 646 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 647 dag Operands = ops; 648 dag Fragment = frag; 649 code PredicateCode = pred; 650 code ImmediateCode = [{}]; 651 SDNodeXForm OperandTransform = xform; 652 } 653 654 // OutPatFrag is a pattern fragment that is used as part of an output pattern 655 // (not an input pattern). These do not have predicates or transforms, but are 656 // used to avoid repeated subexpressions in output patterns. 657 class OutPatFrag<dag ops, dag frag> 658 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 659 660 // PatLeaf's are pattern fragments that have no operands. This is just a helper 661 // to define immediates and other common things concisely. 662 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 663 : PatFrag<(ops), frag, pred, xform>; 664 665 666 // ImmLeaf is a pattern fragment with a constraint on the immediate. The 667 // constraint is a function that is run on the immediate (always with the value 668 // sign extended out to an int64_t) as Imm. For example: 669 // 670 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 671 // 672 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also 673 // is preferred over using PatLeaf because it allows the code generator to 674 // reason more about the constraint. 675 // 676 // If FastIsel should ignore all instructions that have an operand of this type, 677 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce 678 // the code size of the generated fast instruction selector. 679 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 680 : PatFrag<(ops), (vt imm), [{}], xform> { 681 let ImmediateCode = pred; 682 bit FastIselShouldIgnore = 0; 683 } 684 685 686 // Leaf fragments. 687 688 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 689 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 690 691 def immAllOnesV: PatLeaf<(build_vector), [{ 692 return ISD::isBuildVectorAllOnes(N); 693 }]>; 694 def immAllZerosV: PatLeaf<(build_vector), [{ 695 return ISD::isBuildVectorAllZeros(N); 696 }]>; 697 698 699 700 // Other helper fragments. 701 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 702 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 703 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 704 705 // null_frag - The null pattern operator is used in multiclass instantiations 706 // which accept an SDPatternOperator for use in matching patterns for internal 707 // definitions. When expanding a pattern, if the null fragment is referenced 708 // in the expansion, the pattern is discarded and it is as-if '[]' had been 709 // specified. This allows multiclasses to have the isel patterns be optional. 710 def null_frag : SDPatternOperator; 711 712 // load fragments. 713 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 714 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 715 }]>; 716 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 717 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 718 }]>; 719 720 // extending load fragments. 721 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 722 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 723 }]>; 724 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 725 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 726 }]>; 727 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 728 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 729 }]>; 730 731 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 732 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 733 }]>; 734 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 735 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 736 }]>; 737 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 738 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 739 }]>; 740 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 741 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 742 }]>; 743 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 744 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 745 }]>; 746 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 747 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 748 }]>; 749 750 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 751 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 752 }]>; 753 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 754 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 755 }]>; 756 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 757 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 758 }]>; 759 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 760 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 761 }]>; 762 763 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 764 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 765 }]>; 766 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 767 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 768 }]>; 769 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 770 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 771 }]>; 772 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 773 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 774 }]>; 775 776 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 777 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 778 }]>; 779 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 780 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 781 }]>; 782 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 783 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 784 }]>; 785 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 786 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 787 }]>; 788 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 789 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32; 790 }]>; 791 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 792 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64; 793 }]>; 794 795 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 796 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 797 }]>; 798 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 799 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 800 }]>; 801 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 802 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 803 }]>; 804 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 805 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 806 }]>; 807 808 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 809 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 810 }]>; 811 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 812 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 813 }]>; 814 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 815 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 816 }]>; 817 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 818 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 819 }]>; 820 821 // store fragments. 822 def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 823 (st node:$val, node:$ptr), [{ 824 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 825 }]>; 826 def store : PatFrag<(ops node:$val, node:$ptr), 827 (unindexedstore node:$val, node:$ptr), [{ 828 return !cast<StoreSDNode>(N)->isTruncatingStore(); 829 }]>; 830 831 // truncstore fragments. 832 def truncstore : PatFrag<(ops node:$val, node:$ptr), 833 (unindexedstore node:$val, node:$ptr), [{ 834 return cast<StoreSDNode>(N)->isTruncatingStore(); 835 }]>; 836 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 837 (truncstore node:$val, node:$ptr), [{ 838 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 839 }]>; 840 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 841 (truncstore node:$val, node:$ptr), [{ 842 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 843 }]>; 844 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 845 (truncstore node:$val, node:$ptr), [{ 846 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 847 }]>; 848 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 849 (truncstore node:$val, node:$ptr), [{ 850 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 851 }]>; 852 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 853 (truncstore node:$val, node:$ptr), [{ 854 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 855 }]>; 856 857 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 858 (truncstore node:$val, node:$ptr), [{ 859 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 860 }]>; 861 862 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 863 (truncstore node:$val, node:$ptr), [{ 864 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 865 }]>; 866 867 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 868 (truncstore node:$val, node:$ptr), [{ 869 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 870 }]>; 871 872 // indexed store fragments. 873 def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 874 (ist node:$val, node:$base, node:$offset), [{ 875 return !cast<StoreSDNode>(N)->isTruncatingStore(); 876 }]>; 877 878 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 879 (istore node:$val, node:$base, node:$offset), [{ 880 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 881 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 882 }]>; 883 884 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 885 (ist node:$val, node:$base, node:$offset), [{ 886 return cast<StoreSDNode>(N)->isTruncatingStore(); 887 }]>; 888 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 889 (itruncstore node:$val, node:$base, node:$offset), [{ 890 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 891 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 892 }]>; 893 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 894 (pre_truncst node:$val, node:$base, node:$offset), [{ 895 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 896 }]>; 897 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 898 (pre_truncst node:$val, node:$base, node:$offset), [{ 899 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 900 }]>; 901 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 902 (pre_truncst node:$val, node:$base, node:$offset), [{ 903 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 904 }]>; 905 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 906 (pre_truncst node:$val, node:$base, node:$offset), [{ 907 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 908 }]>; 909 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 910 (pre_truncst node:$val, node:$base, node:$offset), [{ 911 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 912 }]>; 913 914 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 915 (istore node:$val, node:$ptr, node:$offset), [{ 916 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 917 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 918 }]>; 919 920 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 921 (itruncstore node:$val, node:$base, node:$offset), [{ 922 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 923 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 924 }]>; 925 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 926 (post_truncst node:$val, node:$base, node:$offset), [{ 927 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 928 }]>; 929 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 930 (post_truncst node:$val, node:$base, node:$offset), [{ 931 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 932 }]>; 933 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 934 (post_truncst node:$val, node:$base, node:$offset), [{ 935 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 936 }]>; 937 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 938 (post_truncst node:$val, node:$base, node:$offset), [{ 939 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 940 }]>; 941 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 942 (post_truncst node:$val, node:$base, node:$offset), [{ 943 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 944 }]>; 945 946 // nontemporal store fragments. 947 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 948 (store node:$val, node:$ptr), [{ 949 return cast<StoreSDNode>(N)->isNonTemporal(); 950 }]>; 951 952 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 953 (nontemporalstore node:$val, node:$ptr), [{ 954 StoreSDNode *St = cast<StoreSDNode>(N); 955 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 956 }]>; 957 958 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 959 (nontemporalstore node:$val, node:$ptr), [{ 960 StoreSDNode *St = cast<StoreSDNode>(N); 961 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 962 }]>; 963 964 // nontemporal load fragments. 965 def nontemporalload : PatFrag<(ops node:$ptr), 966 (load node:$ptr), [{ 967 return cast<LoadSDNode>(N)->isNonTemporal(); 968 }]>; 969 970 def alignednontemporalload : PatFrag<(ops node:$ptr), 971 (nontemporalload node:$ptr), [{ 972 LoadSDNode *Ld = cast<LoadSDNode>(N); 973 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 974 }]>; 975 976 // setcc convenience fragments. 977 def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 978 (setcc node:$lhs, node:$rhs, SETOEQ)>; 979 def setogt : PatFrag<(ops node:$lhs, node:$rhs), 980 (setcc node:$lhs, node:$rhs, SETOGT)>; 981 def setoge : PatFrag<(ops node:$lhs, node:$rhs), 982 (setcc node:$lhs, node:$rhs, SETOGE)>; 983 def setolt : PatFrag<(ops node:$lhs, node:$rhs), 984 (setcc node:$lhs, node:$rhs, SETOLT)>; 985 def setole : PatFrag<(ops node:$lhs, node:$rhs), 986 (setcc node:$lhs, node:$rhs, SETOLE)>; 987 def setone : PatFrag<(ops node:$lhs, node:$rhs), 988 (setcc node:$lhs, node:$rhs, SETONE)>; 989 def seto : PatFrag<(ops node:$lhs, node:$rhs), 990 (setcc node:$lhs, node:$rhs, SETO)>; 991 def setuo : PatFrag<(ops node:$lhs, node:$rhs), 992 (setcc node:$lhs, node:$rhs, SETUO)>; 993 def setueq : PatFrag<(ops node:$lhs, node:$rhs), 994 (setcc node:$lhs, node:$rhs, SETUEQ)>; 995 def setugt : PatFrag<(ops node:$lhs, node:$rhs), 996 (setcc node:$lhs, node:$rhs, SETUGT)>; 997 def setuge : PatFrag<(ops node:$lhs, node:$rhs), 998 (setcc node:$lhs, node:$rhs, SETUGE)>; 999 def setult : PatFrag<(ops node:$lhs, node:$rhs), 1000 (setcc node:$lhs, node:$rhs, SETULT)>; 1001 def setule : PatFrag<(ops node:$lhs, node:$rhs), 1002 (setcc node:$lhs, node:$rhs, SETULE)>; 1003 def setune : PatFrag<(ops node:$lhs, node:$rhs), 1004 (setcc node:$lhs, node:$rhs, SETUNE)>; 1005 def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1006 (setcc node:$lhs, node:$rhs, SETEQ)>; 1007 def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1008 (setcc node:$lhs, node:$rhs, SETGT)>; 1009 def setge : PatFrag<(ops node:$lhs, node:$rhs), 1010 (setcc node:$lhs, node:$rhs, SETGE)>; 1011 def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1012 (setcc node:$lhs, node:$rhs, SETLT)>; 1013 def setle : PatFrag<(ops node:$lhs, node:$rhs), 1014 (setcc node:$lhs, node:$rhs, SETLE)>; 1015 def setne : PatFrag<(ops node:$lhs, node:$rhs), 1016 (setcc node:$lhs, node:$rhs, SETNE)>; 1017 1018 def atomic_cmp_swap_8 : 1019 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1020 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1021 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1022 }]>; 1023 def atomic_cmp_swap_16 : 1024 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1025 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1026 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1027 }]>; 1028 def atomic_cmp_swap_32 : 1029 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1030 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1031 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1032 }]>; 1033 def atomic_cmp_swap_64 : 1034 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1035 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1036 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1037 }]>; 1038 1039 multiclass binary_atomic_op<SDNode atomic_op> { 1040 def _8 : PatFrag<(ops node:$ptr, node:$val), 1041 (atomic_op node:$ptr, node:$val), [{ 1042 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1043 }]>; 1044 def _16 : PatFrag<(ops node:$ptr, node:$val), 1045 (atomic_op node:$ptr, node:$val), [{ 1046 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1047 }]>; 1048 def _32 : PatFrag<(ops node:$ptr, node:$val), 1049 (atomic_op node:$ptr, node:$val), [{ 1050 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1051 }]>; 1052 def _64 : PatFrag<(ops node:$ptr, node:$val), 1053 (atomic_op node:$ptr, node:$val), [{ 1054 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1055 }]>; 1056 } 1057 1058 defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1059 defm atomic_swap : binary_atomic_op<atomic_swap>; 1060 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1061 defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1062 defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1063 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1064 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1065 defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1066 defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1067 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1068 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1069 defm atomic_store : binary_atomic_op<atomic_store>; 1070 1071 def atomic_load_8 : 1072 PatFrag<(ops node:$ptr), 1073 (atomic_load node:$ptr), [{ 1074 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1075 }]>; 1076 def atomic_load_16 : 1077 PatFrag<(ops node:$ptr), 1078 (atomic_load node:$ptr), [{ 1079 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1080 }]>; 1081 def atomic_load_32 : 1082 PatFrag<(ops node:$ptr), 1083 (atomic_load node:$ptr), [{ 1084 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1085 }]>; 1086 def atomic_load_64 : 1087 PatFrag<(ops node:$ptr), 1088 (atomic_load node:$ptr), [{ 1089 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1090 }]>; 1091 1092 //===----------------------------------------------------------------------===// 1093 // Selection DAG Pattern Support. 1094 // 1095 // Patterns are what are actually matched against by the target-flavored 1096 // instruction selection DAG. Instructions defined by the target implicitly 1097 // define patterns in most cases, but patterns can also be explicitly added when 1098 // an operation is defined by a sequence of instructions (e.g. loading a large 1099 // immediate value on RISC targets that do not support immediates as large as 1100 // their GPRs). 1101 // 1102 1103 class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1104 dag PatternToMatch = patternToMatch; 1105 list<dag> ResultInstrs = resultInstrs; 1106 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1107 int AddedComplexity = 0; // See class Instruction in Target.td. 1108 } 1109 1110 // Pat - A simple (but common) form of a pattern, which produces a simple result 1111 // not needing a full list. 1112 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1113 1114 //===----------------------------------------------------------------------===// 1115 // Complex pattern definitions. 1116 // 1117 1118 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1119 // in C++. NumOperands is the number of operands returned by the select function; 1120 // SelectFunc is the name of the function used to pattern match the max. pattern; 1121 // RootNodes are the list of possible root nodes of the sub-dags to match. 1122 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1123 // 1124 class ComplexPattern<ValueType ty, int numops, string fn, 1125 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1126 int complexity = -1> { 1127 ValueType Ty = ty; 1128 int NumOperands = numops; 1129 string SelectFunc = fn; 1130 list<SDNode> RootNodes = roots; 1131 list<SDNodeProperty> Properties = props; 1132 int Complexity = complexity; 1133 } 1134