1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Lowering arithmetic 6 (AddPtr x y) -> (ADDL x y) 7 (Add32 x y) -> (ADDL x y) 8 (Add16 x y) -> (ADDL x y) 9 (Add8 x y) -> (ADDL x y) 10 (Add32F x y) -> (ADDSS x y) 11 (Add64F x y) -> (ADDSD x y) 12 13 (Add32carry x y) -> (ADDLcarry x y) 14 (Add32withcarry x y c) -> (ADCL x y c) 15 16 (SubPtr x y) -> (SUBL x y) 17 (Sub32 x y) -> (SUBL x y) 18 (Sub16 x y) -> (SUBL x y) 19 (Sub8 x y) -> (SUBL x y) 20 (Sub32F x y) -> (SUBSS x y) 21 (Sub64F x y) -> (SUBSD x y) 22 23 (Sub32carry x y) -> (SUBLcarry x y) 24 (Sub32withcarry x y c) -> (SBBL x y c) 25 26 (Mul32 x y) -> (MULL x y) 27 (Mul16 x y) -> (MULL x y) 28 (Mul8 x y) -> (MULL x y) 29 (Mul32F x y) -> (MULSS x y) 30 (Mul64F x y) -> (MULSD x y) 31 32 (Mul32uhilo x y) -> (MULLQU x y) 33 34 (Div32F x y) -> (DIVSS x y) 35 (Div64F x y) -> (DIVSD x y) 36 37 (Div32 x y) -> (DIVL x y) 38 (Div32u x y) -> (DIVLU x y) 39 (Div16 x y) -> (DIVW x y) 40 (Div16u x y) -> (DIVWU x y) 41 (Div8 x y) -> (DIVW (SignExt8to16 x) (SignExt8to16 y)) 42 (Div8u x y) -> (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)) 43 44 (Hmul32 x y) -> (HMULL x y) 45 (Hmul32u x y) -> (HMULLU x y) 46 (Hmul16 x y) -> (HMULW x y) 47 (Hmul16u x y) -> (HMULWU x y) 48 (Hmul8 x y) -> (HMULB x y) 49 (Hmul8u x y) -> (HMULBU x y) 50 51 (Mod32 x y) -> (MODL x y) 52 (Mod32u x y) -> (MODLU x y) 53 (Mod16 x y) -> (MODW x y) 54 (Mod16u x y) -> (MODWU x y) 55 (Mod8 x y) -> (MODW (SignExt8to16 x) (SignExt8to16 y)) 56 (Mod8u x y) -> (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y)) 57 58 (And32 x y) -> (ANDL x y) 59 (And16 x y) -> (ANDL x y) 60 (And8 x y) -> (ANDL x y) 61 62 (Or32 x y) -> (ORL x y) 63 (Or16 x y) -> (ORL x y) 64 (Or8 x y) -> (ORL x y) 65 66 (Xor32 x y) -> (XORL x y) 67 (Xor16 x y) -> (XORL x y) 68 (Xor8 x y) -> (XORL x y) 69 70 (Neg32 x) -> (NEGL x) 71 (Neg16 x) -> (NEGL x) 72 (Neg8 x) -> (NEGL x) 73 (Neg32F x) && !config.use387 -> (PXOR x (MOVSSconst <config.Frontend().TypeFloat32()> [f2i(math.Copysign(0, -1))])) 74 (Neg64F x) && !config.use387 -> (PXOR x (MOVSDconst <config.Frontend().TypeFloat64()> [f2i(math.Copysign(0, -1))])) 75 (Neg32F x) && config.use387 -> (FCHS x) 76 (Neg64F x) && config.use387 -> (FCHS x) 77 78 (Com32 x) -> (NOTL x) 79 (Com16 x) -> (NOTL x) 80 (Com8 x) -> (NOTL x) 81 82 // Lowering boolean ops 83 (AndB x y) -> (ANDL x y) 84 (OrB x y) -> (ORL x y) 85 (Not x) -> (XORLconst [1] x) 86 87 // Lowering pointer arithmetic 88 (OffPtr [off] ptr) -> (ADDLconst [off] ptr) 89 90 (Bswap32 x) -> (BSWAPL x) 91 92 (Sqrt x) -> (SQRTSD x) 93 94 // Lowering extension 95 (SignExt8to16 x) -> (MOVBLSX x) 96 (SignExt8to32 x) -> (MOVBLSX x) 97 (SignExt16to32 x) -> (MOVWLSX x) 98 99 (ZeroExt8to16 x) -> (MOVBLZX x) 100 (ZeroExt8to32 x) -> (MOVBLZX x) 101 (ZeroExt16to32 x) -> (MOVWLZX x) 102 103 (Signmask x) -> (SARLconst x [31]) 104 (Zeromask <t> x) -> (XORLconst [-1] (SBBLcarrymask <t> (CMPLconst x [1]))) 105 (Slicemask <t> x) -> (XORLconst [-1] (SARLconst <t> (SUBLconst <t> x [1]) [31])) 106 107 // Lowering truncation 108 // Because we ignore high parts of registers, truncates are just copies. 109 (Trunc16to8 x) -> x 110 (Trunc32to8 x) -> x 111 (Trunc32to16 x) -> x 112 113 // Lowering float <-> int 114 (Cvt32to32F x) -> (CVTSL2SS x) 115 (Cvt32to64F x) -> (CVTSL2SD x) 116 117 (Cvt32Fto32 x) -> (CVTTSS2SL x) 118 (Cvt64Fto32 x) -> (CVTTSD2SL x) 119 120 (Cvt32Fto64F x) -> (CVTSS2SD x) 121 (Cvt64Fto32F x) -> (CVTSD2SS x) 122 123 // Lowering shifts 124 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. 125 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) 126 (Lsh32x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 127 (Lsh32x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 128 (Lsh32x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 129 130 (Lsh16x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 131 (Lsh16x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 132 (Lsh16x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 133 134 (Lsh8x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 135 (Lsh8x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 136 (Lsh8x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 137 138 (Lrot32 <t> x [c]) -> (ROLLconst <t> [c&31] x) 139 (Lrot16 <t> x [c]) -> (ROLWconst <t> [c&15] x) 140 (Lrot8 <t> x [c]) -> (ROLBconst <t> [c&7] x) 141 142 (Rsh32Ux32 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 143 (Rsh32Ux16 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 144 (Rsh32Ux8 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 145 146 (Rsh16Ux32 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16]))) 147 (Rsh16Ux16 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16]))) 148 (Rsh16Ux8 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16]))) 149 150 (Rsh8Ux32 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8]))) 151 (Rsh8Ux16 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8]))) 152 (Rsh8Ux8 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8]))) 153 154 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. 155 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. 156 157 (Rsh32x32 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32]))))) 158 (Rsh32x16 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32]))))) 159 (Rsh32x8 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32]))))) 160 161 (Rsh16x32 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16]))))) 162 (Rsh16x16 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16]))))) 163 (Rsh16x8 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16]))))) 164 165 (Rsh8x32 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8]))))) 166 (Rsh8x16 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8]))))) 167 (Rsh8x8 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8]))))) 168 169 // constant shifts 170 // generic opt rewrites all constant shifts to shift by Const64 171 (Lsh32x64 x (Const64 [c])) && uint64(c) < 32 -> (SHLLconst x [c]) 172 (Rsh32x64 x (Const64 [c])) && uint64(c) < 32 -> (SARLconst x [c]) 173 (Rsh32Ux64 x (Const64 [c])) && uint64(c) < 32 -> (SHRLconst x [c]) 174 (Lsh16x64 x (Const64 [c])) && uint64(c) < 16 -> (SHLLconst x [c]) 175 (Rsh16x64 x (Const64 [c])) && uint64(c) < 16 -> (SARWconst x [c]) 176 (Rsh16Ux64 x (Const64 [c])) && uint64(c) < 16 -> (SHRWconst x [c]) 177 (Lsh8x64 x (Const64 [c])) && uint64(c) < 8 -> (SHLLconst x [c]) 178 (Rsh8x64 x (Const64 [c])) && uint64(c) < 8 -> (SARBconst x [c]) 179 (Rsh8Ux64 x (Const64 [c])) && uint64(c) < 8 -> (SHRBconst x [c]) 180 181 // large constant shifts 182 (Lsh32x64 _ (Const64 [c])) && uint64(c) >= 32 -> (Const32 [0]) 183 (Rsh32Ux64 _ (Const64 [c])) && uint64(c) >= 32 -> (Const32 [0]) 184 (Lsh16x64 _ (Const64 [c])) && uint64(c) >= 16 -> (Const16 [0]) 185 (Rsh16Ux64 _ (Const64 [c])) && uint64(c) >= 16 -> (Const16 [0]) 186 (Lsh8x64 _ (Const64 [c])) && uint64(c) >= 8 -> (Const8 [0]) 187 (Rsh8Ux64 _ (Const64 [c])) && uint64(c) >= 8 -> (Const8 [0]) 188 189 // large constant signed right shift, we leave the sign bit 190 (Rsh32x64 x (Const64 [c])) && uint64(c) >= 32 -> (SARLconst x [31]) 191 (Rsh16x64 x (Const64 [c])) && uint64(c) >= 16 -> (SARWconst x [15]) 192 (Rsh8x64 x (Const64 [c])) && uint64(c) >= 8 -> (SARBconst x [7]) 193 194 // Lowering comparisons 195 (Less32 x y) -> (SETL (CMPL x y)) 196 (Less16 x y) -> (SETL (CMPW x y)) 197 (Less8 x y) -> (SETL (CMPB x y)) 198 (Less32U x y) -> (SETB (CMPL x y)) 199 (Less16U x y) -> (SETB (CMPW x y)) 200 (Less8U x y) -> (SETB (CMPB x y)) 201 // Use SETGF with reversed operands to dodge NaN case 202 (Less64F x y) -> (SETGF (UCOMISD y x)) 203 (Less32F x y) -> (SETGF (UCOMISS y x)) 204 205 (Leq32 x y) -> (SETLE (CMPL x y)) 206 (Leq16 x y) -> (SETLE (CMPW x y)) 207 (Leq8 x y) -> (SETLE (CMPB x y)) 208 (Leq32U x y) -> (SETBE (CMPL x y)) 209 (Leq16U x y) -> (SETBE (CMPW x y)) 210 (Leq8U x y) -> (SETBE (CMPB x y)) 211 // Use SETGEF with reversed operands to dodge NaN case 212 (Leq64F x y) -> (SETGEF (UCOMISD y x)) 213 (Leq32F x y) -> (SETGEF (UCOMISS y x)) 214 215 (Greater32 x y) -> (SETG (CMPL x y)) 216 (Greater16 x y) -> (SETG (CMPW x y)) 217 (Greater8 x y) -> (SETG (CMPB x y)) 218 (Greater32U x y) -> (SETA (CMPL x y)) 219 (Greater16U x y) -> (SETA (CMPW x y)) 220 (Greater8U x y) -> (SETA (CMPB x y)) 221 // Note Go assembler gets UCOMISx operand order wrong, but it is right here 222 // Bug is accommodated at generation of assembly language. 223 (Greater64F x y) -> (SETGF (UCOMISD x y)) 224 (Greater32F x y) -> (SETGF (UCOMISS x y)) 225 226 (Geq32 x y) -> (SETGE (CMPL x y)) 227 (Geq16 x y) -> (SETGE (CMPW x y)) 228 (Geq8 x y) -> (SETGE (CMPB x y)) 229 (Geq32U x y) -> (SETAE (CMPL x y)) 230 (Geq16U x y) -> (SETAE (CMPW x y)) 231 (Geq8U x y) -> (SETAE (CMPB x y)) 232 // Note Go assembler gets UCOMISx operand order wrong, but it is right here 233 // Bug is accommodated at generation of assembly language. 234 (Geq64F x y) -> (SETGEF (UCOMISD x y)) 235 (Geq32F x y) -> (SETGEF (UCOMISS x y)) 236 237 (Eq32 x y) -> (SETEQ (CMPL x y)) 238 (Eq16 x y) -> (SETEQ (CMPW x y)) 239 (Eq8 x y) -> (SETEQ (CMPB x y)) 240 (EqB x y) -> (SETEQ (CMPB x y)) 241 (EqPtr x y) -> (SETEQ (CMPL x y)) 242 (Eq64F x y) -> (SETEQF (UCOMISD x y)) 243 (Eq32F x y) -> (SETEQF (UCOMISS x y)) 244 245 (Neq32 x y) -> (SETNE (CMPL x y)) 246 (Neq16 x y) -> (SETNE (CMPW x y)) 247 (Neq8 x y) -> (SETNE (CMPB x y)) 248 (NeqB x y) -> (SETNE (CMPB x y)) 249 (NeqPtr x y) -> (SETNE (CMPL x y)) 250 (Neq64F x y) -> (SETNEF (UCOMISD x y)) 251 (Neq32F x y) -> (SETNEF (UCOMISS x y)) 252 253 // Lowering loads 254 (Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) -> (MOVLload ptr mem) 255 (Load <t> ptr mem) && is16BitInt(t) -> (MOVWload ptr mem) 256 (Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) -> (MOVBload ptr mem) 257 (Load <t> ptr mem) && is32BitFloat(t) -> (MOVSSload ptr mem) 258 (Load <t> ptr mem) && is64BitFloat(t) -> (MOVSDload ptr mem) 259 260 // Lowering stores 261 // These more-specific FP versions of Store pattern should come first. 262 (Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem) 263 (Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem) 264 265 (Store [4] ptr val mem) -> (MOVLstore ptr val mem) 266 (Store [2] ptr val mem) -> (MOVWstore ptr val mem) 267 (Store [1] ptr val mem) -> (MOVBstore ptr val mem) 268 269 // Lowering moves 270 (Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem 271 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBload src mem) mem) 272 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstore dst (MOVWload src mem) mem) 273 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstore dst (MOVLload src mem) mem) 274 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 -> 275 (MOVBstore [2] dst (MOVBload [2] src mem) 276 (MOVWstore dst (MOVWload src mem) mem)) 277 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 -> 278 (MOVBstore [4] dst (MOVBload [4] src mem) 279 (MOVLstore dst (MOVLload src mem) mem)) 280 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 -> 281 (MOVWstore [4] dst (MOVWload [4] src mem) 282 (MOVLstore dst (MOVLload src mem) mem)) 283 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 -> 284 (MOVLstore [3] dst (MOVLload [3] src mem) 285 (MOVLstore dst (MOVLload src mem) mem)) 286 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 -> 287 (MOVLstore [4] dst (MOVLload [4] src mem) 288 (MOVLstore dst (MOVLload src mem) mem)) 289 290 // Adjust moves to be a multiple of 4 bytes. 291 (Move [s] dst src mem) 292 && SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size()%4 != 0 -> 293 (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%4] 294 (ADDLconst <dst.Type> dst [SizeAndAlign(s).Size()%4]) 295 (ADDLconst <src.Type> src [SizeAndAlign(s).Size()%4]) 296 (MOVLstore dst (MOVLload src mem) mem)) 297 298 // Medium copying uses a duff device. 299 (Move [s] dst src mem) 300 && SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() <= 4*128 && SizeAndAlign(s).Size()%4 == 0 301 && !config.noDuffDevice -> 302 (DUFFCOPY [10*(128-SizeAndAlign(s).Size()/4)] dst src mem) 303 // 10 and 128 are magic constants. 10 is the number of bytes to encode: 304 // MOVL (SI), CX 305 // ADDL $4, SI 306 // MOVL CX, (DI) 307 // ADDL $4, DI 308 // and 128 is the number of such blocks. See src/runtime/duff_386.s:duffcopy. 309 310 // Large copying uses REP MOVSL. 311 (Move [s] dst src mem) && (SizeAndAlign(s).Size() > 4*128 || config.noDuffDevice) && SizeAndAlign(s).Size()%4 == 0 -> 312 (REPMOVSL dst src (MOVLconst [SizeAndAlign(s).Size()/4]) mem) 313 314 // Lowering Zero instructions 315 (Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem 316 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem) 317 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstoreconst [0] destptr mem) 318 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstoreconst [0] destptr mem) 319 320 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 -> 321 (MOVBstoreconst [makeValAndOff(0,2)] destptr 322 (MOVWstoreconst [0] destptr mem)) 323 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 5 -> 324 (MOVBstoreconst [makeValAndOff(0,4)] destptr 325 (MOVLstoreconst [0] destptr mem)) 326 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 6 -> 327 (MOVWstoreconst [makeValAndOff(0,4)] destptr 328 (MOVLstoreconst [0] destptr mem)) 329 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 7 -> 330 (MOVLstoreconst [makeValAndOff(0,3)] destptr 331 (MOVLstoreconst [0] destptr mem)) 332 333 // Strip off any fractional word zeroing. 334 (Zero [s] destptr mem) && SizeAndAlign(s).Size()%4 != 0 && SizeAndAlign(s).Size() > 4 -> 335 (Zero [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%4] (ADDLconst destptr [SizeAndAlign(s).Size()%4]) 336 (MOVLstoreconst [0] destptr mem)) 337 338 // Zero small numbers of words directly. 339 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 -> 340 (MOVLstoreconst [makeValAndOff(0,4)] destptr 341 (MOVLstoreconst [0] destptr mem)) 342 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 12 -> 343 (MOVLstoreconst [makeValAndOff(0,8)] destptr 344 (MOVLstoreconst [makeValAndOff(0,4)] destptr 345 (MOVLstoreconst [0] destptr mem))) 346 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 -> 347 (MOVLstoreconst [makeValAndOff(0,12)] destptr 348 (MOVLstoreconst [makeValAndOff(0,8)] destptr 349 (MOVLstoreconst [makeValAndOff(0,4)] destptr 350 (MOVLstoreconst [0] destptr mem)))) 351 352 // Medium zeroing uses a duff device. 353 (Zero [s] destptr mem) 354 && SizeAndAlign(s).Size() > 16 355 && SizeAndAlign(s).Size() <= 4*128 356 && SizeAndAlign(s).Size()%4 == 0 357 && !config.noDuffDevice -> 358 (DUFFZERO [1*(128-SizeAndAlign(s).Size()/4)] destptr (MOVLconst [0]) mem) 359 // 1 and 128 are magic constants. 1 is the number of bytes to encode STOSL. 360 // 128 is the number of STOSL instructions in duffzero. 361 // See src/runtime/duff_386.s:duffzero. 362 363 // Large zeroing uses REP STOSQ. 364 (Zero [s] destptr mem) 365 && (SizeAndAlign(s).Size() > 4*128 || (config.noDuffDevice && SizeAndAlign(s).Size() > 16)) 366 && SizeAndAlign(s).Size()%4 == 0 -> 367 (REPSTOSL destptr (MOVLconst [SizeAndAlign(s).Size()/4]) (MOVLconst [0]) mem) 368 369 // Lowering constants 370 (Const8 [val]) -> (MOVLconst [val]) 371 (Const16 [val]) -> (MOVLconst [val]) 372 (Const32 [val]) -> (MOVLconst [val]) 373 (Const32F [val]) -> (MOVSSconst [val]) 374 (Const64F [val]) -> (MOVSDconst [val]) 375 (ConstNil) -> (MOVLconst [0]) 376 (ConstBool [b]) -> (MOVLconst [b]) 377 378 // Lowering calls 379 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 380 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 381 (DeferCall [argwid] mem) -> (CALLdefer [argwid] mem) 382 (GoCall [argwid] mem) -> (CALLgo [argwid] mem) 383 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 384 385 // Miscellaneous 386 (Convert <t> x mem) -> (MOVLconvert <t> x mem) 387 (IsNonNil p) -> (SETNE (TESTL p p)) 388 (IsInBounds idx len) -> (SETB (CMPL idx len)) 389 (IsSliceInBounds idx len) -> (SETBE (CMPL idx len)) 390 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 391 (GetG mem) -> (LoweredGetG mem) 392 (GetClosurePtr) -> (LoweredGetClosurePtr) 393 (Addr {sym} base) -> (LEAL {sym} base) 394 395 // block rewrites 396 (If (SETL cmp) yes no) -> (LT cmp yes no) 397 (If (SETLE cmp) yes no) -> (LE cmp yes no) 398 (If (SETG cmp) yes no) -> (GT cmp yes no) 399 (If (SETGE cmp) yes no) -> (GE cmp yes no) 400 (If (SETEQ cmp) yes no) -> (EQ cmp yes no) 401 (If (SETNE cmp) yes no) -> (NE cmp yes no) 402 (If (SETB cmp) yes no) -> (ULT cmp yes no) 403 (If (SETBE cmp) yes no) -> (ULE cmp yes no) 404 (If (SETA cmp) yes no) -> (UGT cmp yes no) 405 (If (SETAE cmp) yes no) -> (UGE cmp yes no) 406 407 // Special case for floating point - LF/LEF not generated 408 (If (SETGF cmp) yes no) -> (UGT cmp yes no) 409 (If (SETGEF cmp) yes no) -> (UGE cmp yes no) 410 (If (SETEQF cmp) yes no) -> (EQF cmp yes no) 411 (If (SETNEF cmp) yes no) -> (NEF cmp yes no) 412 413 (If cond yes no) -> (NE (TESTB cond cond) yes no) 414 415 // *************************** 416 // Above: lowering rules 417 // Below: optimizations 418 // *************************** 419 // TODO: Should the optimizations be a separate pass? 420 421 // Fold boolean tests into blocks 422 (NE (TESTB (SETL cmp) (SETL cmp)) yes no) -> (LT cmp yes no) 423 (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) -> (LE cmp yes no) 424 (NE (TESTB (SETG cmp) (SETG cmp)) yes no) -> (GT cmp yes no) 425 (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) -> (GE cmp yes no) 426 (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) -> (EQ cmp yes no) 427 (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) -> (NE cmp yes no) 428 (NE (TESTB (SETB cmp) (SETB cmp)) yes no) -> (ULT cmp yes no) 429 (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) -> (ULE cmp yes no) 430 (NE (TESTB (SETA cmp) (SETA cmp)) yes no) -> (UGT cmp yes no) 431 (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) -> (UGE cmp yes no) 432 433 // Special case for floating point - LF/LEF not generated 434 (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) -> (UGT cmp yes no) 435 (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) -> (UGE cmp yes no) 436 (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) -> (EQF cmp yes no) 437 (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) -> (NEF cmp yes no) 438 439 // fold constants into instructions 440 (ADDL x (MOVLconst [c])) -> (ADDLconst [c] x) 441 (ADDL (MOVLconst [c]) x) -> (ADDLconst [c] x) 442 (ADDLcarry x (MOVLconst [c])) -> (ADDLconstcarry [c] x) 443 (ADDLcarry (MOVLconst [c]) x) -> (ADDLconstcarry [c] x) 444 (ADCL x (MOVLconst [c]) f) -> (ADCLconst [c] x f) 445 (ADCL (MOVLconst [c]) x f) -> (ADCLconst [c] x f) 446 447 (SUBL x (MOVLconst [c])) -> (SUBLconst x [c]) 448 (SUBL (MOVLconst [c]) x) -> (NEGL (SUBLconst <v.Type> x [c])) 449 (SUBLcarry x (MOVLconst [c])) -> (SUBLconstcarry [c] x) 450 (SBBL x (MOVLconst [c]) f) -> (SBBLconst [c] x f) 451 452 (MULL x (MOVLconst [c])) -> (MULLconst [c] x) 453 (MULL (MOVLconst [c]) x) -> (MULLconst [c] x) 454 455 (ANDL x (MOVLconst [c])) -> (ANDLconst [c] x) 456 (ANDL (MOVLconst [c]) x) -> (ANDLconst [c] x) 457 458 (ANDLconst [c] (ANDLconst [d] x)) -> (ANDLconst [c & d] x) 459 460 (XORLconst [c] (XORLconst [d] x)) -> (XORLconst [c ^ d] x) 461 462 (MULLconst [c] (MULLconst [d] x)) -> (MULLconst [int64(int32(c * d))] x) 463 464 (ORL x (MOVLconst [c])) -> (ORLconst [c] x) 465 (ORL (MOVLconst [c]) x) -> (ORLconst [c] x) 466 467 (XORL x (MOVLconst [c])) -> (XORLconst [c] x) 468 (XORL (MOVLconst [c]) x) -> (XORLconst [c] x) 469 470 (SHLL x (MOVLconst [c])) -> (SHLLconst [c&31] x) 471 (SHLL x (MOVLconst [c])) -> (SHLLconst [c&31] x) 472 473 (SHRL x (MOVLconst [c])) -> (SHRLconst [c&31] x) 474 (SHRL x (MOVLconst [c])) -> (SHRLconst [c&31] x) 475 476 (SHRW x (MOVLconst [c])) -> (SHRWconst [c&31] x) 477 (SHRW x (MOVLconst [c])) -> (SHRWconst [c&31] x) 478 479 (SHRB x (MOVLconst [c])) -> (SHRBconst [c&31] x) 480 (SHRB x (MOVLconst [c])) -> (SHRBconst [c&31] x) 481 482 (SARL x (MOVLconst [c])) -> (SARLconst [c&31] x) 483 (SARL x (MOVLconst [c])) -> (SARLconst [c&31] x) 484 485 (SARW x (MOVLconst [c])) -> (SARWconst [c&31] x) 486 (SARW x (MOVLconst [c])) -> (SARWconst [c&31] x) 487 488 (SARB x (MOVLconst [c])) -> (SARBconst [c&31] x) 489 (SARB x (MOVLconst [c])) -> (SARBconst [c&31] x) 490 491 (SARL x (ANDLconst [31] y)) -> (SARL x y) 492 493 (SHLL x (ANDLconst [31] y)) -> (SHLL x y) 494 495 (SHRL x (ANDLconst [31] y)) -> (SHRL x y) 496 497 (ROLLconst [c] (ROLLconst [d] x)) -> (ROLLconst [(c+d)&31] x) 498 (ROLWconst [c] (ROLWconst [d] x)) -> (ROLWconst [(c+d)&15] x) 499 (ROLBconst [c] (ROLBconst [d] x)) -> (ROLBconst [(c+d)& 7] x) 500 501 (ROLLconst [0] x) -> x 502 (ROLWconst [0] x) -> x 503 (ROLBconst [0] x) -> x 504 505 // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits) 506 // because the x86 instructions are defined to use all 5 bits of the shift even 507 // for the small shifts. I don't think we'll ever generate a weird shift (e.g. 508 // (SHRW x (MOVLconst [24])), but just in case. 509 510 (CMPL x (MOVLconst [c])) -> (CMPLconst x [c]) 511 (CMPL (MOVLconst [c]) x) -> (InvertFlags (CMPLconst x [c])) 512 (CMPW x (MOVLconst [c])) -> (CMPWconst x [int64(int16(c))]) 513 (CMPW (MOVLconst [c]) x) -> (InvertFlags (CMPWconst x [int64(int16(c))])) 514 (CMPB x (MOVLconst [c])) -> (CMPBconst x [int64(int8(c))]) 515 (CMPB (MOVLconst [c]) x) -> (InvertFlags (CMPBconst x [int64(int8(c))])) 516 517 // strength reduction 518 // Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf: 519 // 1 - addq, shlq, leaq, negq 520 // 3 - imulq 521 // This limits the rewrites to two instructions. 522 // TODO: 27, 81 523 (MULLconst [-1] x) -> (NEGL x) 524 (MULLconst [0] _) -> (MOVLconst [0]) 525 (MULLconst [1] x) -> x 526 (MULLconst [3] x) -> (LEAL2 x x) 527 (MULLconst [5] x) -> (LEAL4 x x) 528 (MULLconst [7] x) -> (LEAL8 (NEGL <v.Type> x) x) 529 (MULLconst [9] x) -> (LEAL8 x x) 530 (MULLconst [11] x) -> (LEAL2 x (LEAL4 <v.Type> x x)) 531 (MULLconst [13] x) -> (LEAL4 x (LEAL2 <v.Type> x x)) 532 (MULLconst [21] x) -> (LEAL4 x (LEAL4 <v.Type> x x)) 533 (MULLconst [25] x) -> (LEAL8 x (LEAL2 <v.Type> x x)) 534 (MULLconst [37] x) -> (LEAL4 x (LEAL8 <v.Type> x x)) 535 (MULLconst [41] x) -> (LEAL8 x (LEAL4 <v.Type> x x)) 536 (MULLconst [73] x) -> (LEAL8 x (LEAL8 <v.Type> x x)) 537 538 (MULLconst [c] x) && isPowerOfTwo(c) -> (SHLLconst [log2(c)] x) 539 (MULLconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUBL (SHLLconst <v.Type> [log2(c+1)] x) x) 540 (MULLconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (LEAL1 (SHLLconst <v.Type> [log2(c-1)] x) x) 541 (MULLconst [c] x) && isPowerOfTwo(c-2) && c >= 34 -> (LEAL2 (SHLLconst <v.Type> [log2(c-2)] x) x) 542 (MULLconst [c] x) && isPowerOfTwo(c-4) && c >= 68 -> (LEAL4 (SHLLconst <v.Type> [log2(c-4)] x) x) 543 (MULLconst [c] x) && isPowerOfTwo(c-8) && c >= 136 -> (LEAL8 (SHLLconst <v.Type> [log2(c-8)] x) x) 544 (MULLconst [c] x) && c%3 == 0 && isPowerOfTwo(c/3)-> (SHLLconst [log2(c/3)] (LEAL2 <v.Type> x x)) 545 (MULLconst [c] x) && c%5 == 0 && isPowerOfTwo(c/5)-> (SHLLconst [log2(c/5)] (LEAL4 <v.Type> x x)) 546 (MULLconst [c] x) && c%9 == 0 && isPowerOfTwo(c/9)-> (SHLLconst [log2(c/9)] (LEAL8 <v.Type> x x)) 547 548 // combine add/shift into LEAL 549 (ADDL x (SHLLconst [3] y)) -> (LEAL8 x y) 550 (ADDL x (SHLLconst [2] y)) -> (LEAL4 x y) 551 (ADDL x (SHLLconst [1] y)) -> (LEAL2 x y) 552 (ADDL x (ADDL y y)) -> (LEAL2 x y) 553 (ADDL x (ADDL x y)) -> (LEAL2 y x) 554 (ADDL x (ADDL y x)) -> (LEAL2 y x) 555 556 // combine ADDL/ADDLconst into LEAL1 557 (ADDLconst [c] (ADDL x y)) -> (LEAL1 [c] x y) 558 (ADDL (ADDLconst [c] x) y) -> (LEAL1 [c] x y) 559 (ADDL x (ADDLconst [c] y)) -> (LEAL1 [c] x y) 560 561 // fold ADDL into LEAL 562 (ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x) 563 (LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x) 564 (LEAL [c] {s} (ADDL x y)) && x.Op != OpSB && y.Op != OpSB -> (LEAL1 [c] {s} x y) 565 (ADDL x (LEAL [c] {s} y)) && x.Op != OpSB && y.Op != OpSB -> (LEAL1 [c] {s} x y) 566 (ADDL (LEAL [c] {s} x) y) && x.Op != OpSB && y.Op != OpSB -> (LEAL1 [c] {s} x y) 567 568 // fold ADDLconst into LEALx 569 (ADDLconst [c] (LEAL1 [d] {s} x y)) && is32Bit(c+d) -> (LEAL1 [c+d] {s} x y) 570 (ADDLconst [c] (LEAL2 [d] {s} x y)) && is32Bit(c+d) -> (LEAL2 [c+d] {s} x y) 571 (ADDLconst [c] (LEAL4 [d] {s} x y)) && is32Bit(c+d) -> (LEAL4 [c+d] {s} x y) 572 (ADDLconst [c] (LEAL8 [d] {s} x y)) && is32Bit(c+d) -> (LEAL8 [c+d] {s} x y) 573 (LEAL1 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL1 [c+d] {s} x y) 574 (LEAL1 [c] {s} x (ADDLconst [d] y)) && is32Bit(c+d) && y.Op != OpSB -> (LEAL1 [c+d] {s} x y) 575 (LEAL2 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL2 [c+d] {s} x y) 576 (LEAL2 [c] {s} x (ADDLconst [d] y)) && is32Bit(c+2*d) && y.Op != OpSB -> (LEAL2 [c+2*d] {s} x y) 577 (LEAL4 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL4 [c+d] {s} x y) 578 (LEAL4 [c] {s} x (ADDLconst [d] y)) && is32Bit(c+4*d) && y.Op != OpSB -> (LEAL4 [c+4*d] {s} x y) 579 (LEAL8 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL8 [c+d] {s} x y) 580 (LEAL8 [c] {s} x (ADDLconst [d] y)) && is32Bit(c+8*d) && y.Op != OpSB -> (LEAL8 [c+8*d] {s} x y) 581 582 // fold shifts into LEALx 583 (LEAL1 [c] {s} x (SHLLconst [1] y)) -> (LEAL2 [c] {s} x y) 584 (LEAL1 [c] {s} (SHLLconst [1] x) y) -> (LEAL2 [c] {s} y x) 585 (LEAL1 [c] {s} x (SHLLconst [2] y)) -> (LEAL4 [c] {s} x y) 586 (LEAL1 [c] {s} (SHLLconst [2] x) y) -> (LEAL4 [c] {s} y x) 587 (LEAL1 [c] {s} x (SHLLconst [3] y)) -> (LEAL8 [c] {s} x y) 588 (LEAL1 [c] {s} (SHLLconst [3] x) y) -> (LEAL8 [c] {s} y x) 589 590 (LEAL2 [c] {s} x (SHLLconst [1] y)) -> (LEAL4 [c] {s} x y) 591 (LEAL2 [c] {s} x (SHLLconst [2] y)) -> (LEAL8 [c] {s} x y) 592 (LEAL4 [c] {s} x (SHLLconst [1] y)) -> (LEAL8 [c] {s} x y) 593 594 // reverse ordering of compare instruction 595 (SETL (InvertFlags x)) -> (SETG x) 596 (SETG (InvertFlags x)) -> (SETL x) 597 (SETB (InvertFlags x)) -> (SETA x) 598 (SETA (InvertFlags x)) -> (SETB x) 599 (SETLE (InvertFlags x)) -> (SETGE x) 600 (SETGE (InvertFlags x)) -> (SETLE x) 601 (SETBE (InvertFlags x)) -> (SETAE x) 602 (SETAE (InvertFlags x)) -> (SETBE x) 603 (SETEQ (InvertFlags x)) -> (SETEQ x) 604 (SETNE (InvertFlags x)) -> (SETNE x) 605 606 // sign extended loads 607 // Note: The combined instruction must end up in the same block 608 // as the original load. If not, we end up making a value with 609 // memory type live in two different blocks, which can lead to 610 // multiple memory values alive simultaneously. 611 // Make sure we don't combine these ops if the load has another use. 612 // This prevents a single load from being split into multiple loads 613 // which then might return different values. See test/atomicload.go. 614 (MOVBLSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBLSXload <v.Type> [off] {sym} ptr mem) 615 (MOVBLZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 616 (MOVWLSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWLSXload <v.Type> [off] {sym} ptr mem) 617 (MOVWLZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 618 619 (MOVBLZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem) 620 (MOVWLZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx1 <v.Type> [off] {sym} ptr idx mem) 621 (MOVWLZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem) 622 623 // replace load from same location as preceding store with copy 624 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 625 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 626 (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 627 628 // Fold extensions and ANDs together. 629 (MOVBLZX (ANDLconst [c] x)) -> (ANDLconst [c & 0xff] x) 630 (MOVWLZX (ANDLconst [c] x)) -> (ANDLconst [c & 0xffff] x) 631 (MOVBLSX (ANDLconst [c] x)) && c & 0x80 == 0 -> (ANDLconst [c & 0x7f] x) 632 (MOVWLSX (ANDLconst [c] x)) && c & 0x8000 == 0 -> (ANDLconst [c & 0x7fff] x) 633 634 // Don't extend before storing 635 (MOVWstore [off] {sym} ptr (MOVWLSX x) mem) -> (MOVWstore [off] {sym} ptr x mem) 636 (MOVBstore [off] {sym} ptr (MOVBLSX x) mem) -> (MOVBstore [off] {sym} ptr x mem) 637 (MOVWstore [off] {sym} ptr (MOVWLZX x) mem) -> (MOVWstore [off] {sym} ptr x mem) 638 (MOVBstore [off] {sym} ptr (MOVBLZX x) mem) -> (MOVBstore [off] {sym} ptr x mem) 639 640 // fold constants into memory operations 641 // Note that this is not always a good idea because if not all the uses of 642 // the ADDQconst get eliminated, we still have to compute the ADDQconst and we now 643 // have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one. 644 // Nevertheless, let's do it! 645 (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVLload [off1+off2] {sym} ptr mem) 646 (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 647 (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 648 (MOVSSload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVSSload [off1+off2] {sym} ptr mem) 649 (MOVSDload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVSDload [off1+off2] {sym} ptr mem) 650 651 (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVLstore [off1+off2] {sym} ptr val mem) 652 (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 653 (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 654 (MOVSSstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVSSstore [off1+off2] {sym} ptr val mem) 655 (MOVSDstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVSDstore [off1+off2] {sym} ptr val mem) 656 657 // Fold constants into stores. 658 (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> 659 (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) 660 (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> 661 (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) 662 (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> 663 (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) 664 665 // Fold address offsets into constant stores. 666 (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 667 (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 668 (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 669 (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 670 (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 671 (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 672 673 // We need to fold LEAQ into the MOVx ops so that the live variable analysis knows 674 // what variables are being read/written by the ops. 675 // Note: we turn off this merging for operations on globals when building 676 // position-independent code (when Flag_shared is set). 677 // PIC needs a spare register to load the PC into. Having the LEAL be 678 // a separate instruction gives us that register. Having the LEAL be 679 // a separate instruction also allows it to be CSEd (which is good because 680 // it compiles to a thunk call). 681 (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 682 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 683 (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) 684 (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 685 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 686 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) 687 (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 688 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 689 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) 690 (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 691 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 692 (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) 693 (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 694 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 695 (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 696 697 (MOVBLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 698 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 699 (MOVBLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) 700 (MOVWLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 701 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 702 (MOVWLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) 703 704 (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 705 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 706 (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 707 (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 708 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 709 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 710 (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 711 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 712 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 713 (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 714 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 715 (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 716 (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) 717 && (base.Op != OpSB || !config.ctxt.Flag_shared) -> 718 (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 719 720 (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) 721 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) -> 722 (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 723 (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) 724 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) -> 725 (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 726 (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) 727 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) -> 728 (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 729 730 // generating indexed loads and stores 731 (MOVBload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 732 (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 733 (MOVWload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 734 (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 735 (MOVWload [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 736 (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 737 (MOVLload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 738 (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 739 (MOVLload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 740 (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 741 (MOVSSload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 742 (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 743 (MOVSSload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 744 (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 745 (MOVSDload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 746 (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 747 (MOVSDload [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 748 (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 749 750 (MOVBstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 751 (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 752 (MOVWstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 753 (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 754 (MOVWstore [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 755 (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 756 (MOVLstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 757 (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 758 (MOVLstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 759 (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 760 (MOVSSstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 761 (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 762 (MOVSSstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 763 (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 764 (MOVSDstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 765 (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 766 (MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 767 (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 768 769 (MOVBload [off] {sym} (ADDL ptr idx) mem) && ptr.Op != OpSB -> (MOVBloadidx1 [off] {sym} ptr idx mem) 770 (MOVWload [off] {sym} (ADDL ptr idx) mem) && ptr.Op != OpSB -> (MOVWloadidx1 [off] {sym} ptr idx mem) 771 (MOVLload [off] {sym} (ADDL ptr idx) mem) && ptr.Op != OpSB -> (MOVLloadidx1 [off] {sym} ptr idx mem) 772 (MOVSSload [off] {sym} (ADDL ptr idx) mem) && ptr.Op != OpSB -> (MOVSSloadidx1 [off] {sym} ptr idx mem) 773 (MOVSDload [off] {sym} (ADDL ptr idx) mem) && ptr.Op != OpSB -> (MOVSDloadidx1 [off] {sym} ptr idx mem) 774 (MOVBstore [off] {sym} (ADDL ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx1 [off] {sym} ptr idx val mem) 775 (MOVWstore [off] {sym} (ADDL ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx1 [off] {sym} ptr idx val mem) 776 (MOVLstore [off] {sym} (ADDL ptr idx) val mem) && ptr.Op != OpSB -> (MOVLstoreidx1 [off] {sym} ptr idx val mem) 777 (MOVSSstore [off] {sym} (ADDL ptr idx) val mem) && ptr.Op != OpSB -> (MOVSSstoreidx1 [off] {sym} ptr idx val mem) 778 (MOVSDstore [off] {sym} (ADDL ptr idx) val mem) && ptr.Op != OpSB -> (MOVSDstoreidx1 [off] {sym} ptr idx val mem) 779 780 (MOVBstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 781 (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 782 (MOVWstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 783 (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 784 (MOVWstoreconst [x] {sym1} (LEAL2 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 785 (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 786 (MOVLstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 787 (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 788 (MOVLstoreconst [x] {sym1} (LEAL4 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 789 (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 790 791 (MOVBstoreconst [x] {sym} (ADDL ptr idx) mem) -> (MOVBstoreconstidx1 [x] {sym} ptr idx mem) 792 (MOVWstoreconst [x] {sym} (ADDL ptr idx) mem) -> (MOVWstoreconstidx1 [x] {sym} ptr idx mem) 793 (MOVLstoreconst [x] {sym} (ADDL ptr idx) mem) -> (MOVLstoreconstidx1 [x] {sym} ptr idx mem) 794 795 // combine SHLL into indexed loads and stores 796 (MOVWloadidx1 [c] {sym} ptr (SHLLconst [1] idx) mem) -> (MOVWloadidx2 [c] {sym} ptr idx mem) 797 (MOVLloadidx1 [c] {sym} ptr (SHLLconst [2] idx) mem) -> (MOVLloadidx4 [c] {sym} ptr idx mem) 798 (MOVWstoreidx1 [c] {sym} ptr (SHLLconst [1] idx) val mem) -> (MOVWstoreidx2 [c] {sym} ptr idx val mem) 799 (MOVLstoreidx1 [c] {sym} ptr (SHLLconst [2] idx) val mem) -> (MOVLstoreidx4 [c] {sym} ptr idx val mem) 800 (MOVWstoreconstidx1 [c] {sym} ptr (SHLLconst [1] idx) mem) -> (MOVWstoreconstidx2 [c] {sym} ptr idx mem) 801 (MOVLstoreconstidx1 [c] {sym} ptr (SHLLconst [2] idx) mem) -> (MOVLstoreconstidx4 [c] {sym} ptr idx mem) 802 803 // combine ADDL into indexed loads and stores 804 (MOVBloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVBloadidx1 [c+d] {sym} ptr idx mem) 805 (MOVWloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVWloadidx1 [c+d] {sym} ptr idx mem) 806 (MOVWloadidx2 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVWloadidx2 [c+d] {sym} ptr idx mem) 807 (MOVLloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVLloadidx1 [c+d] {sym} ptr idx mem) 808 (MOVLloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVLloadidx4 [c+d] {sym} ptr idx mem) 809 (MOVSSloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVSSloadidx1 [c+d] {sym} ptr idx mem) 810 (MOVSSloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVSSloadidx4 [c+d] {sym} ptr idx mem) 811 (MOVSDloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVSDloadidx1 [c+d] {sym} ptr idx mem) 812 (MOVSDloadidx8 [c] {sym} (ADDLconst [d] ptr) idx mem) -> (MOVSDloadidx8 [c+d] {sym} ptr idx mem) 813 814 (MOVBstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) 815 (MOVWstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) 816 (MOVWstoreidx2 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) 817 (MOVLstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) 818 (MOVLstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) 819 (MOVSSstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) 820 (MOVSSstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) 821 (MOVSDstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) 822 (MOVSDstoreidx8 [c] {sym} (ADDLconst [d] ptr) idx val mem) -> (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) 823 824 (MOVBloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVBloadidx1 [c+d] {sym} ptr idx mem) 825 (MOVWloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVWloadidx1 [c+d] {sym} ptr idx mem) 826 (MOVWloadidx2 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) 827 (MOVLloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVLloadidx1 [c+d] {sym} ptr idx mem) 828 (MOVLloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) 829 (MOVSSloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVSSloadidx1 [c+d] {sym} ptr idx mem) 830 (MOVSSloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) 831 (MOVSDloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVSDloadidx1 [c+d] {sym} ptr idx mem) 832 (MOVSDloadidx8 [c] {sym} ptr (ADDLconst [d] idx) mem) -> (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) 833 834 (MOVBstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) 835 (MOVWstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) 836 (MOVWstoreidx2 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) 837 (MOVLstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) 838 (MOVLstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) 839 (MOVSSstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) 840 (MOVSSstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) 841 (MOVSDstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) 842 (MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) 843 844 (MOVBstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) -> 845 (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 846 (MOVWstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) -> 847 (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 848 (MOVWstoreconstidx2 [x] {sym} (ADDLconst [c] ptr) idx mem) -> 849 (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) 850 (MOVLstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) -> 851 (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 852 (MOVLstoreconstidx4 [x] {sym} (ADDLconst [c] ptr) idx mem) -> 853 (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) 854 855 (MOVBstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) -> 856 (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 857 (MOVWstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) -> 858 (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 859 (MOVWstoreconstidx2 [x] {sym} ptr (ADDLconst [c] idx) mem) -> 860 (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) 861 (MOVLstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) -> 862 (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 863 (MOVLstoreconstidx4 [x] {sym} ptr (ADDLconst [c] idx) mem) -> 864 (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) 865 866 // fold LEALs together 867 (LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 868 (LEAL [off1+off2] {mergeSym(sym1,sym2)} x) 869 870 // LEAL into LEAL1 871 (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 872 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) 873 (LEAL1 [off1] {sym1} x (LEAL [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB -> 874 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) 875 876 // LEAL1 into LEAL 877 (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 878 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) 879 880 // LEAL into LEAL[248] 881 (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 882 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) 883 (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 884 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) 885 (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 886 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) 887 888 // LEAL[248] into LEAL 889 (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 890 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) 891 (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 892 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) 893 (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 894 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) 895 896 // Absorb InvertFlags into branches. 897 (LT (InvertFlags cmp) yes no) -> (GT cmp yes no) 898 (GT (InvertFlags cmp) yes no) -> (LT cmp yes no) 899 (LE (InvertFlags cmp) yes no) -> (GE cmp yes no) 900 (GE (InvertFlags cmp) yes no) -> (LE cmp yes no) 901 (ULT (InvertFlags cmp) yes no) -> (UGT cmp yes no) 902 (UGT (InvertFlags cmp) yes no) -> (ULT cmp yes no) 903 (ULE (InvertFlags cmp) yes no) -> (UGE cmp yes no) 904 (UGE (InvertFlags cmp) yes no) -> (ULE cmp yes no) 905 (EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) 906 (NE (InvertFlags cmp) yes no) -> (NE cmp yes no) 907 908 // Constant comparisons. 909 (CMPLconst (MOVLconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 910 (CMPLconst (MOVLconst [x]) [y]) && int32(x)<int32(y) && uint32(x)<uint32(y) -> (FlagLT_ULT) 911 (CMPLconst (MOVLconst [x]) [y]) && int32(x)<int32(y) && uint32(x)>uint32(y) -> (FlagLT_UGT) 912 (CMPLconst (MOVLconst [x]) [y]) && int32(x)>int32(y) && uint32(x)<uint32(y) -> (FlagGT_ULT) 913 (CMPLconst (MOVLconst [x]) [y]) && int32(x)>int32(y) && uint32(x)>uint32(y) -> (FlagGT_UGT) 914 (CMPWconst (MOVLconst [x]) [y]) && int16(x)==int16(y) -> (FlagEQ) 915 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<int16(y) && uint16(x)<uint16(y) -> (FlagLT_ULT) 916 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<int16(y) && uint16(x)>uint16(y) -> (FlagLT_UGT) 917 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>int16(y) && uint16(x)<uint16(y) -> (FlagGT_ULT) 918 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>int16(y) && uint16(x)>uint16(y) -> (FlagGT_UGT) 919 (CMPBconst (MOVLconst [x]) [y]) && int8(x)==int8(y) -> (FlagEQ) 920 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<int8(y) && uint8(x)<uint8(y) -> (FlagLT_ULT) 921 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<int8(y) && uint8(x)>uint8(y) -> (FlagLT_UGT) 922 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>int8(y) && uint8(x)<uint8(y) -> (FlagGT_ULT) 923 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>int8(y) && uint8(x)>uint8(y) -> (FlagGT_UGT) 924 925 // Other known comparisons. 926 (CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) -> (FlagLT_ULT) 927 (CMPLconst (ANDLconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT_ULT) 928 (CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < int16(n) -> (FlagLT_ULT) 929 (CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < int8(n) -> (FlagLT_ULT) 930 // TODO: DIVxU also. 931 932 // Absorb flag constants into SBB ops. 933 (SBBLcarrymask (FlagEQ)) -> (MOVLconst [0]) 934 (SBBLcarrymask (FlagLT_ULT)) -> (MOVLconst [-1]) 935 (SBBLcarrymask (FlagLT_UGT)) -> (MOVLconst [0]) 936 (SBBLcarrymask (FlagGT_ULT)) -> (MOVLconst [-1]) 937 (SBBLcarrymask (FlagGT_UGT)) -> (MOVLconst [0]) 938 939 // Absorb flag constants into branches. 940 (EQ (FlagEQ) yes no) -> (First nil yes no) 941 (EQ (FlagLT_ULT) yes no) -> (First nil no yes) 942 (EQ (FlagLT_UGT) yes no) -> (First nil no yes) 943 (EQ (FlagGT_ULT) yes no) -> (First nil no yes) 944 (EQ (FlagGT_UGT) yes no) -> (First nil no yes) 945 946 (NE (FlagEQ) yes no) -> (First nil no yes) 947 (NE (FlagLT_ULT) yes no) -> (First nil yes no) 948 (NE (FlagLT_UGT) yes no) -> (First nil yes no) 949 (NE (FlagGT_ULT) yes no) -> (First nil yes no) 950 (NE (FlagGT_UGT) yes no) -> (First nil yes no) 951 952 (LT (FlagEQ) yes no) -> (First nil no yes) 953 (LT (FlagLT_ULT) yes no) -> (First nil yes no) 954 (LT (FlagLT_UGT) yes no) -> (First nil yes no) 955 (LT (FlagGT_ULT) yes no) -> (First nil no yes) 956 (LT (FlagGT_UGT) yes no) -> (First nil no yes) 957 958 (LE (FlagEQ) yes no) -> (First nil yes no) 959 (LE (FlagLT_ULT) yes no) -> (First nil yes no) 960 (LE (FlagLT_UGT) yes no) -> (First nil yes no) 961 (LE (FlagGT_ULT) yes no) -> (First nil no yes) 962 (LE (FlagGT_UGT) yes no) -> (First nil no yes) 963 964 (GT (FlagEQ) yes no) -> (First nil no yes) 965 (GT (FlagLT_ULT) yes no) -> (First nil no yes) 966 (GT (FlagLT_UGT) yes no) -> (First nil no yes) 967 (GT (FlagGT_ULT) yes no) -> (First nil yes no) 968 (GT (FlagGT_UGT) yes no) -> (First nil yes no) 969 970 (GE (FlagEQ) yes no) -> (First nil yes no) 971 (GE (FlagLT_ULT) yes no) -> (First nil no yes) 972 (GE (FlagLT_UGT) yes no) -> (First nil no yes) 973 (GE (FlagGT_ULT) yes no) -> (First nil yes no) 974 (GE (FlagGT_UGT) yes no) -> (First nil yes no) 975 976 (ULT (FlagEQ) yes no) -> (First nil no yes) 977 (ULT (FlagLT_ULT) yes no) -> (First nil yes no) 978 (ULT (FlagLT_UGT) yes no) -> (First nil no yes) 979 (ULT (FlagGT_ULT) yes no) -> (First nil yes no) 980 (ULT (FlagGT_UGT) yes no) -> (First nil no yes) 981 982 (ULE (FlagEQ) yes no) -> (First nil yes no) 983 (ULE (FlagLT_ULT) yes no) -> (First nil yes no) 984 (ULE (FlagLT_UGT) yes no) -> (First nil no yes) 985 (ULE (FlagGT_ULT) yes no) -> (First nil yes no) 986 (ULE (FlagGT_UGT) yes no) -> (First nil no yes) 987 988 (UGT (FlagEQ) yes no) -> (First nil no yes) 989 (UGT (FlagLT_ULT) yes no) -> (First nil no yes) 990 (UGT (FlagLT_UGT) yes no) -> (First nil yes no) 991 (UGT (FlagGT_ULT) yes no) -> (First nil no yes) 992 (UGT (FlagGT_UGT) yes no) -> (First nil yes no) 993 994 (UGE (FlagEQ) yes no) -> (First nil yes no) 995 (UGE (FlagLT_ULT) yes no) -> (First nil no yes) 996 (UGE (FlagLT_UGT) yes no) -> (First nil yes no) 997 (UGE (FlagGT_ULT) yes no) -> (First nil no yes) 998 (UGE (FlagGT_UGT) yes no) -> (First nil yes no) 999 1000 // Absorb flag constants into SETxx ops. 1001 (SETEQ (FlagEQ)) -> (MOVLconst [1]) 1002 (SETEQ (FlagLT_ULT)) -> (MOVLconst [0]) 1003 (SETEQ (FlagLT_UGT)) -> (MOVLconst [0]) 1004 (SETEQ (FlagGT_ULT)) -> (MOVLconst [0]) 1005 (SETEQ (FlagGT_UGT)) -> (MOVLconst [0]) 1006 1007 (SETNE (FlagEQ)) -> (MOVLconst [0]) 1008 (SETNE (FlagLT_ULT)) -> (MOVLconst [1]) 1009 (SETNE (FlagLT_UGT)) -> (MOVLconst [1]) 1010 (SETNE (FlagGT_ULT)) -> (MOVLconst [1]) 1011 (SETNE (FlagGT_UGT)) -> (MOVLconst [1]) 1012 1013 (SETL (FlagEQ)) -> (MOVLconst [0]) 1014 (SETL (FlagLT_ULT)) -> (MOVLconst [1]) 1015 (SETL (FlagLT_UGT)) -> (MOVLconst [1]) 1016 (SETL (FlagGT_ULT)) -> (MOVLconst [0]) 1017 (SETL (FlagGT_UGT)) -> (MOVLconst [0]) 1018 1019 (SETLE (FlagEQ)) -> (MOVLconst [1]) 1020 (SETLE (FlagLT_ULT)) -> (MOVLconst [1]) 1021 (SETLE (FlagLT_UGT)) -> (MOVLconst [1]) 1022 (SETLE (FlagGT_ULT)) -> (MOVLconst [0]) 1023 (SETLE (FlagGT_UGT)) -> (MOVLconst [0]) 1024 1025 (SETG (FlagEQ)) -> (MOVLconst [0]) 1026 (SETG (FlagLT_ULT)) -> (MOVLconst [0]) 1027 (SETG (FlagLT_UGT)) -> (MOVLconst [0]) 1028 (SETG (FlagGT_ULT)) -> (MOVLconst [1]) 1029 (SETG (FlagGT_UGT)) -> (MOVLconst [1]) 1030 1031 (SETGE (FlagEQ)) -> (MOVLconst [1]) 1032 (SETGE (FlagLT_ULT)) -> (MOVLconst [0]) 1033 (SETGE (FlagLT_UGT)) -> (MOVLconst [0]) 1034 (SETGE (FlagGT_ULT)) -> (MOVLconst [1]) 1035 (SETGE (FlagGT_UGT)) -> (MOVLconst [1]) 1036 1037 (SETB (FlagEQ)) -> (MOVLconst [0]) 1038 (SETB (FlagLT_ULT)) -> (MOVLconst [1]) 1039 (SETB (FlagLT_UGT)) -> (MOVLconst [0]) 1040 (SETB (FlagGT_ULT)) -> (MOVLconst [1]) 1041 (SETB (FlagGT_UGT)) -> (MOVLconst [0]) 1042 1043 (SETBE (FlagEQ)) -> (MOVLconst [1]) 1044 (SETBE (FlagLT_ULT)) -> (MOVLconst [1]) 1045 (SETBE (FlagLT_UGT)) -> (MOVLconst [0]) 1046 (SETBE (FlagGT_ULT)) -> (MOVLconst [1]) 1047 (SETBE (FlagGT_UGT)) -> (MOVLconst [0]) 1048 1049 (SETA (FlagEQ)) -> (MOVLconst [0]) 1050 (SETA (FlagLT_ULT)) -> (MOVLconst [0]) 1051 (SETA (FlagLT_UGT)) -> (MOVLconst [1]) 1052 (SETA (FlagGT_ULT)) -> (MOVLconst [0]) 1053 (SETA (FlagGT_UGT)) -> (MOVLconst [1]) 1054 1055 (SETAE (FlagEQ)) -> (MOVLconst [1]) 1056 (SETAE (FlagLT_ULT)) -> (MOVLconst [0]) 1057 (SETAE (FlagLT_UGT)) -> (MOVLconst [1]) 1058 (SETAE (FlagGT_ULT)) -> (MOVLconst [0]) 1059 (SETAE (FlagGT_UGT)) -> (MOVLconst [1]) 1060 1061 // Remove redundant *const ops 1062 (ADDLconst [c] x) && int32(c)==0 -> x 1063 (SUBLconst [c] x) && int32(c) == 0 -> x 1064 (ANDLconst [c] _) && int32(c)==0 -> (MOVLconst [0]) 1065 (ANDLconst [c] x) && int32(c)==-1 -> x 1066 (ORLconst [c] x) && int32(c)==0 -> x 1067 (ORLconst [c] _) && int32(c)==-1 -> (MOVLconst [-1]) 1068 (XORLconst [c] x) && int32(c)==0 -> x 1069 // TODO: since we got rid of the W/B versions, we might miss 1070 // things like (ANDLconst [0x100] x) which were formerly 1071 // (ANDBconst [0] x). Probably doesn't happen very often. 1072 // If we cared, we might do: 1073 // (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 -> (MOVLconst [0]) 1074 1075 // Convert constant subtracts to constant adds 1076 (SUBLconst [c] x) -> (ADDLconst [int64(int32(-c))] x) 1077 1078 // generic constant folding 1079 // TODO: more of this 1080 (ADDLconst [c] (MOVLconst [d])) -> (MOVLconst [int64(int32(c+d))]) 1081 (ADDLconst [c] (ADDLconst [d] x)) -> (ADDLconst [int64(int32(c+d))] x) 1082 (SARLconst [c] (MOVLconst [d])) -> (MOVLconst [d>>uint64(c)]) 1083 (SARWconst [c] (MOVLconst [d])) -> (MOVLconst [d>>uint64(c)]) 1084 (SARBconst [c] (MOVLconst [d])) -> (MOVLconst [d>>uint64(c)]) 1085 (NEGL (MOVLconst [c])) -> (MOVLconst [int64(int32(-c))]) 1086 (MULLconst [c] (MOVLconst [d])) -> (MOVLconst [int64(int32(c*d))]) 1087 (ANDLconst [c] (MOVLconst [d])) -> (MOVLconst [c&d]) 1088 (ORLconst [c] (MOVLconst [d])) -> (MOVLconst [c|d]) 1089 (XORLconst [c] (MOVLconst [d])) -> (MOVLconst [c^d]) 1090 (NOTL (MOVLconst [c])) -> (MOVLconst [^c]) 1091 1092 // generic simplifications 1093 // TODO: more of this 1094 (ADDL x (NEGL y)) -> (SUBL x y) 1095 (SUBL x x) -> (MOVLconst [0]) 1096 (ANDL x x) -> x 1097 (ORL x x) -> x 1098 (XORL x x) -> (MOVLconst [0]) 1099 1100 // checking AND against 0. 1101 (CMPLconst (ANDL x y) [0]) -> (TESTL x y) 1102 (CMPWconst (ANDL x y) [0]) -> (TESTW x y) 1103 (CMPBconst (ANDL x y) [0]) -> (TESTB x y) 1104 (CMPLconst (ANDLconst [c] x) [0]) -> (TESTLconst [c] x) 1105 (CMPWconst (ANDLconst [c] x) [0]) -> (TESTWconst [int64(int16(c))] x) 1106 (CMPBconst (ANDLconst [c] x) [0]) -> (TESTBconst [int64(int8(c))] x) 1107 1108 // TEST %reg,%reg is shorter than CMP 1109 (CMPLconst x [0]) -> (TESTL x x) 1110 (CMPWconst x [0]) -> (TESTW x x) 1111 (CMPBconst x [0]) -> (TESTB x x) 1112 1113 // Combining byte loads into larger (unaligned) loads. 1114 // There are many ways these combinations could occur. This is 1115 // designed to match the way encoding/binary.LittleEndian does it. 1116 (ORL x0:(MOVBload [i] {s} p mem) 1117 s0:(SHLLconst [8] x1:(MOVBload [i+1] {s} p mem))) 1118 && x0.Uses == 1 1119 && x1.Uses == 1 1120 && s0.Uses == 1 1121 && mergePoint(b,x0,x1) != nil 1122 && clobber(x0) 1123 && clobber(x1) 1124 && clobber(s0) 1125 -> @mergePoint(b,x0,x1) (MOVWload [i] {s} p mem) 1126 1127 (ORL o0:(ORL 1128 x0:(MOVWload [i] {s} p mem) 1129 s0:(SHLLconst [16] x1:(MOVBload [i+2] {s} p mem))) 1130 s1:(SHLLconst [24] x2:(MOVBload [i+3] {s} p mem))) 1131 && x0.Uses == 1 1132 && x1.Uses == 1 1133 && x2.Uses == 1 1134 && s0.Uses == 1 1135 && s1.Uses == 1 1136 && o0.Uses == 1 1137 && mergePoint(b,x0,x1,x2) != nil 1138 && clobber(x0) 1139 && clobber(x1) 1140 && clobber(x2) 1141 && clobber(s0) 1142 && clobber(s1) 1143 && clobber(o0) 1144 -> @mergePoint(b,x0,x1,x2) (MOVLload [i] {s} p mem) 1145 1146 (ORL x0:(MOVBloadidx1 [i] {s} p idx mem) 1147 s0:(SHLLconst [8] x1:(MOVBloadidx1 [i+1] {s} p idx mem))) 1148 && x0.Uses == 1 1149 && x1.Uses == 1 1150 && s0.Uses == 1 1151 && mergePoint(b,x0,x1) != nil 1152 && clobber(x0) 1153 && clobber(x1) 1154 && clobber(s0) 1155 -> @mergePoint(b,x0,x1) (MOVWloadidx1 <v.Type> [i] {s} p idx mem) 1156 1157 (ORL o0:(ORL 1158 x0:(MOVWloadidx1 [i] {s} p idx mem) 1159 s0:(SHLLconst [16] x1:(MOVBloadidx1 [i+2] {s} p idx mem))) 1160 s1:(SHLLconst [24] x2:(MOVBloadidx1 [i+3] {s} p idx mem))) 1161 && x0.Uses == 1 1162 && x1.Uses == 1 1163 && x2.Uses == 1 1164 && s0.Uses == 1 1165 && s1.Uses == 1 1166 && o0.Uses == 1 1167 && mergePoint(b,x0,x1,x2) != nil 1168 && clobber(x0) 1169 && clobber(x1) 1170 && clobber(x2) 1171 && clobber(s0) 1172 && clobber(s1) 1173 && clobber(o0) 1174 -> @mergePoint(b,x0,x1,x2) (MOVLloadidx1 <v.Type> [i] {s} p idx mem) 1175 1176 // Combine constant stores into larger (unaligned) stores. 1177 (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) 1178 && x.Uses == 1 1179 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1180 && clobber(x) 1181 -> (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) 1182 (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) 1183 && x.Uses == 1 1184 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1185 && clobber(x) 1186 -> (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) 1187 1188 (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) 1189 && x.Uses == 1 1190 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1191 && clobber(x) 1192 -> (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) 1193 (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) 1194 && x.Uses == 1 1195 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1196 && clobber(x) 1197 -> (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) 1198 1199 (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) 1200 && x.Uses == 1 1201 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1202 && clobber(x) 1203 -> (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLLconst <i.Type> [1] i) mem) 1204 1205 // Combine stores into larger (unaligned) stores. 1206 (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1207 && x.Uses == 1 1208 && clobber(x) 1209 -> (MOVWstore [i-1] {s} p w mem) 1210 (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) 1211 && x.Uses == 1 1212 && clobber(x) 1213 -> (MOVWstore [i-1] {s} p w0 mem) 1214 (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) 1215 && x.Uses == 1 1216 && clobber(x) 1217 -> (MOVLstore [i-2] {s} p w mem) 1218 (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) 1219 && x.Uses == 1 1220 && clobber(x) 1221 -> (MOVLstore [i-2] {s} p w0 mem) 1222 1223 (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) 1224 && x.Uses == 1 1225 && clobber(x) 1226 -> (MOVWstoreidx1 [i-1] {s} p idx w mem) 1227 (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) 1228 && x.Uses == 1 1229 && clobber(x) 1230 -> (MOVWstoreidx1 [i-1] {s} p idx w0 mem) 1231 (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) 1232 && x.Uses == 1 1233 && clobber(x) 1234 -> (MOVLstoreidx1 [i-2] {s} p idx w mem) 1235 (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) 1236 && x.Uses == 1 1237 && clobber(x) 1238 -> (MOVLstoreidx1 [i-2] {s} p idx w0 mem) 1239 1240 (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) 1241 && x.Uses == 1 1242 && clobber(x) 1243 -> (MOVLstoreidx1 [i-2] {s} p (SHLLconst <idx.Type> [1] idx) w mem) 1244 (MOVWstoreidx2 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) 1245 && x.Uses == 1 1246 && clobber(x) 1247 -> (MOVLstoreidx1 [i-2] {s} p (SHLLconst <idx.Type> [1] idx) w0 mem) 1248 1249 // For PIC, break floating-point constant loading into two instructions so we have 1250 // a register to use for holding the address of the constant pool entry. 1251 (MOVSSconst [c]) && config.ctxt.Flag_shared -> (MOVSSconst2 (MOVSSconst1 [c])) 1252 (MOVSDconst [c]) && config.ctxt.Flag_shared -> (MOVSDconst2 (MOVSDconst1 [c])) 1253
