1 // Copyright 2015 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Lowering arithmetic 6 (Add64 x y) -> (ADDQ x y) 7 (AddPtr x y) && config.PtrSize == 8 -> (ADDQ x y) 8 (AddPtr x y) && config.PtrSize == 4 -> (ADDL x y) 9 (Add32 x y) -> (ADDL x y) 10 (Add16 x y) -> (ADDL x y) 11 (Add8 x y) -> (ADDL x y) 12 (Add32F x y) -> (ADDSS x y) 13 (Add64F x y) -> (ADDSD x y) 14 15 (Sub64 x y) -> (SUBQ x y) 16 (SubPtr x y) && config.PtrSize == 8 -> (SUBQ x y) 17 (SubPtr x y) && config.PtrSize == 4 -> (SUBL x y) 18 (Sub32 x y) -> (SUBL x y) 19 (Sub16 x y) -> (SUBL x y) 20 (Sub8 x y) -> (SUBL x y) 21 (Sub32F x y) -> (SUBSS x y) 22 (Sub64F x y) -> (SUBSD x y) 23 24 (Mul64 x y) -> (MULQ x y) 25 (Mul32 x y) -> (MULL x y) 26 (Mul16 x y) -> (MULL x y) 27 (Mul8 x y) -> (MULL x y) 28 (Mul32F x y) -> (MULSS x y) 29 (Mul64F x y) -> (MULSD x y) 30 31 (Div32F x y) -> (DIVSS x y) 32 (Div64F x y) -> (DIVSD x y) 33 34 (Div64 x y) -> (Select0 (DIVQ x y)) 35 (Div64u x y) -> (Select0 (DIVQU x y)) 36 (Div32 x y) -> (Select0 (DIVL x y)) 37 (Div32u x y) -> (Select0 (DIVLU x y)) 38 (Div16 x y) -> (Select0 (DIVW x y)) 39 (Div16u x y) -> (Select0 (DIVWU x y)) 40 (Div8 x y) -> (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) 41 (Div8u x y) -> (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) 42 43 (Hmul64 x y) -> (HMULQ x y) 44 (Hmul64u x y) -> (HMULQU x y) 45 (Hmul32 x y) -> (HMULL x y) 46 (Hmul32u x y) -> (HMULLU x y) 47 (Hmul16 x y) -> (HMULW x y) 48 (Hmul16u x y) -> (HMULWU x y) 49 (Hmul8 x y) -> (HMULB x y) 50 (Hmul8u x y) -> (HMULBU x y) 51 52 (Mul64uhilo x y) -> (MULQU2 x y) 53 (Div128u xhi xlo y) -> (DIVQU2 xhi xlo y) 54 55 (Avg64u x y) -> (AVGQU x y) 56 57 (Mod64 x y) -> (Select1 (DIVQ x y)) 58 (Mod64u x y) -> (Select1 (DIVQU x y)) 59 (Mod32 x y) -> (Select1 (DIVL x y)) 60 (Mod32u x y) -> (Select1 (DIVLU x y)) 61 (Mod16 x y) -> (Select1 (DIVW x y)) 62 (Mod16u x y) -> (Select1 (DIVWU x y)) 63 (Mod8 x y) -> (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) 64 (Mod8u x y) -> (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) 65 66 (And64 x y) -> (ANDQ x y) 67 (And32 x y) -> (ANDL x y) 68 (And16 x y) -> (ANDL x y) 69 (And8 x y) -> (ANDL x y) 70 71 (Or64 x y) -> (ORQ x y) 72 (Or32 x y) -> (ORL x y) 73 (Or16 x y) -> (ORL x y) 74 (Or8 x y) -> (ORL x y) 75 76 (Xor64 x y) -> (XORQ x y) 77 (Xor32 x y) -> (XORL x y) 78 (Xor16 x y) -> (XORL x y) 79 (Xor8 x y) -> (XORL x y) 80 81 (Neg64 x) -> (NEGQ x) 82 (Neg32 x) -> (NEGL x) 83 (Neg16 x) -> (NEGL x) 84 (Neg8 x) -> (NEGL x) 85 (Neg32F x) -> (PXOR x (MOVSSconst <config.Frontend().TypeFloat32()> [f2i(math.Copysign(0, -1))])) 86 (Neg64F x) -> (PXOR x (MOVSDconst <config.Frontend().TypeFloat64()> [f2i(math.Copysign(0, -1))])) 87 88 (Com64 x) -> (NOTQ x) 89 (Com32 x) -> (NOTL x) 90 (Com16 x) -> (NOTL x) 91 (Com8 x) -> (NOTL x) 92 93 // Lowering boolean ops 94 (AndB x y) -> (ANDL x y) 95 (OrB x y) -> (ORL x y) 96 (Not x) -> (XORLconst [1] x) 97 98 // Lowering pointer arithmetic 99 (OffPtr [off] ptr) && config.PtrSize == 8 && is32Bit(off) -> (ADDQconst [off] ptr) 100 (OffPtr [off] ptr) && config.PtrSize == 8 -> (ADDQ (MOVQconst [off]) ptr) 101 (OffPtr [off] ptr) && config.PtrSize == 4 -> (ADDLconst [off] ptr) 102 103 // Lowering other arithmetic 104 (Ctz64 <t> x) -> (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <TypeFlags> (BSFQ x))) 105 (Ctz32 <t> x) -> (CMOVLEQ (Select0 <t> (BSFL x)) (MOVLconst <t> [32]) (Select1 <TypeFlags> (BSFL x))) 106 107 (Bswap64 x) -> (BSWAPQ x) 108 (Bswap32 x) -> (BSWAPL x) 109 110 (Sqrt x) -> (SQRTSD x) 111 112 // Lowering extension 113 // Note: we always extend to 64 bits even though some ops don't need that many result bits. 114 (SignExt8to16 x) -> (MOVBQSX x) 115 (SignExt8to32 x) -> (MOVBQSX x) 116 (SignExt8to64 x) -> (MOVBQSX x) 117 (SignExt16to32 x) -> (MOVWQSX x) 118 (SignExt16to64 x) -> (MOVWQSX x) 119 (SignExt32to64 x) -> (MOVLQSX x) 120 121 (ZeroExt8to16 x) -> (MOVBQZX x) 122 (ZeroExt8to32 x) -> (MOVBQZX x) 123 (ZeroExt8to64 x) -> (MOVBQZX x) 124 (ZeroExt16to32 x) -> (MOVWQZX x) 125 (ZeroExt16to64 x) -> (MOVWQZX x) 126 (ZeroExt32to64 x) -> (MOVLQZX x) 127 128 (Slicemask <t> x) -> (XORQconst [-1] (SARQconst <t> (SUBQconst <t> x [1]) [63])) 129 130 // Lowering truncation 131 // Because we ignore high parts of registers, truncates are just copies. 132 (Trunc16to8 x) -> x 133 (Trunc32to8 x) -> x 134 (Trunc32to16 x) -> x 135 (Trunc64to8 x) -> x 136 (Trunc64to16 x) -> x 137 (Trunc64to32 x) -> x 138 139 // Lowering float <-> int 140 (Cvt32to32F x) -> (CVTSL2SS x) 141 (Cvt32to64F x) -> (CVTSL2SD x) 142 (Cvt64to32F x) -> (CVTSQ2SS x) 143 (Cvt64to64F x) -> (CVTSQ2SD x) 144 145 (Cvt32Fto32 x) -> (CVTTSS2SL x) 146 (Cvt32Fto64 x) -> (CVTTSS2SQ x) 147 (Cvt64Fto32 x) -> (CVTTSD2SL x) 148 (Cvt64Fto64 x) -> (CVTTSD2SQ x) 149 150 (Cvt32Fto64F x) -> (CVTSS2SD x) 151 (Cvt64Fto32F x) -> (CVTSD2SS x) 152 153 // Lowering shifts 154 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. 155 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) 156 (Lsh64x64 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64]))) 157 (Lsh64x32 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64]))) 158 (Lsh64x16 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64]))) 159 (Lsh64x8 <t> x y) -> (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64]))) 160 161 (Lsh32x64 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) 162 (Lsh32x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 163 (Lsh32x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 164 (Lsh32x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 165 166 (Lsh16x64 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) 167 (Lsh16x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 168 (Lsh16x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 169 (Lsh16x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 170 171 (Lsh8x64 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) 172 (Lsh8x32 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 173 (Lsh8x16 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 174 (Lsh8x8 <t> x y) -> (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 175 176 (Lrot64 <t> x [c]) -> (ROLQconst <t> [c&63] x) 177 (Lrot32 <t> x [c]) -> (ROLLconst <t> [c&31] x) 178 (Lrot16 <t> x [c]) -> (ROLWconst <t> [c&15] x) 179 (Lrot8 <t> x [c]) -> (ROLBconst <t> [c&7] x) 180 181 (Rsh64Ux64 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64]))) 182 (Rsh64Ux32 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64]))) 183 (Rsh64Ux16 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64]))) 184 (Rsh64Ux8 <t> x y) -> (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64]))) 185 186 (Rsh32Ux64 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32]))) 187 (Rsh32Ux32 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32]))) 188 (Rsh32Ux16 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32]))) 189 (Rsh32Ux8 <t> x y) -> (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32]))) 190 191 (Rsh16Ux64 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16]))) 192 (Rsh16Ux32 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16]))) 193 (Rsh16Ux16 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16]))) 194 (Rsh16Ux8 <t> x y) -> (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16]))) 195 196 (Rsh8Ux64 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8]))) 197 (Rsh8Ux32 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8]))) 198 (Rsh8Ux16 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8]))) 199 (Rsh8Ux8 <t> x y) -> (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8]))) 200 201 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. 202 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. 203 (Rsh64x64 <t> x y) -> (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64]))))) 204 (Rsh64x32 <t> x y) -> (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64]))))) 205 (Rsh64x16 <t> x y) -> (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64]))))) 206 (Rsh64x8 <t> x y) -> (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64]))))) 207 208 (Rsh32x64 <t> x y) -> (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32]))))) 209 (Rsh32x32 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32]))))) 210 (Rsh32x16 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32]))))) 211 (Rsh32x8 <t> x y) -> (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32]))))) 212 213 (Rsh16x64 <t> x y) -> (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16]))))) 214 (Rsh16x32 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16]))))) 215 (Rsh16x16 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16]))))) 216 (Rsh16x8 <t> x y) -> (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16]))))) 217 218 (Rsh8x64 <t> x y) -> (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8]))))) 219 (Rsh8x32 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8]))))) 220 (Rsh8x16 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8]))))) 221 (Rsh8x8 <t> x y) -> (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8]))))) 222 223 // Lowering comparisons 224 (Less64 x y) -> (SETL (CMPQ x y)) 225 (Less32 x y) -> (SETL (CMPL x y)) 226 (Less16 x y) -> (SETL (CMPW x y)) 227 (Less8 x y) -> (SETL (CMPB x y)) 228 (Less64U x y) -> (SETB (CMPQ x y)) 229 (Less32U x y) -> (SETB (CMPL x y)) 230 (Less16U x y) -> (SETB (CMPW x y)) 231 (Less8U x y) -> (SETB (CMPB x y)) 232 // Use SETGF with reversed operands to dodge NaN case 233 (Less64F x y) -> (SETGF (UCOMISD y x)) 234 (Less32F x y) -> (SETGF (UCOMISS y x)) 235 236 (Leq64 x y) -> (SETLE (CMPQ x y)) 237 (Leq32 x y) -> (SETLE (CMPL x y)) 238 (Leq16 x y) -> (SETLE (CMPW x y)) 239 (Leq8 x y) -> (SETLE (CMPB x y)) 240 (Leq64U x y) -> (SETBE (CMPQ x y)) 241 (Leq32U x y) -> (SETBE (CMPL x y)) 242 (Leq16U x y) -> (SETBE (CMPW x y)) 243 (Leq8U x y) -> (SETBE (CMPB x y)) 244 // Use SETGEF with reversed operands to dodge NaN case 245 (Leq64F x y) -> (SETGEF (UCOMISD y x)) 246 (Leq32F x y) -> (SETGEF (UCOMISS y x)) 247 248 (Greater64 x y) -> (SETG (CMPQ x y)) 249 (Greater32 x y) -> (SETG (CMPL x y)) 250 (Greater16 x y) -> (SETG (CMPW x y)) 251 (Greater8 x y) -> (SETG (CMPB x y)) 252 (Greater64U x y) -> (SETA (CMPQ x y)) 253 (Greater32U x y) -> (SETA (CMPL x y)) 254 (Greater16U x y) -> (SETA (CMPW x y)) 255 (Greater8U x y) -> (SETA (CMPB x y)) 256 // Note Go assembler gets UCOMISx operand order wrong, but it is right here 257 // Bug is accommodated at generation of assembly language. 258 (Greater64F x y) -> (SETGF (UCOMISD x y)) 259 (Greater32F x y) -> (SETGF (UCOMISS x y)) 260 261 (Geq64 x y) -> (SETGE (CMPQ x y)) 262 (Geq32 x y) -> (SETGE (CMPL x y)) 263 (Geq16 x y) -> (SETGE (CMPW x y)) 264 (Geq8 x y) -> (SETGE (CMPB x y)) 265 (Geq64U x y) -> (SETAE (CMPQ x y)) 266 (Geq32U x y) -> (SETAE (CMPL x y)) 267 (Geq16U x y) -> (SETAE (CMPW x y)) 268 (Geq8U x y) -> (SETAE (CMPB x y)) 269 // Note Go assembler gets UCOMISx operand order wrong, but it is right here 270 // Bug is accommodated at generation of assembly language. 271 (Geq64F x y) -> (SETGEF (UCOMISD x y)) 272 (Geq32F x y) -> (SETGEF (UCOMISS x y)) 273 274 (Eq64 x y) -> (SETEQ (CMPQ x y)) 275 (Eq32 x y) -> (SETEQ (CMPL x y)) 276 (Eq16 x y) -> (SETEQ (CMPW x y)) 277 (Eq8 x y) -> (SETEQ (CMPB x y)) 278 (EqB x y) -> (SETEQ (CMPB x y)) 279 (EqPtr x y) && config.PtrSize == 8 -> (SETEQ (CMPQ x y)) 280 (EqPtr x y) && config.PtrSize == 4 -> (SETEQ (CMPL x y)) 281 (Eq64F x y) -> (SETEQF (UCOMISD x y)) 282 (Eq32F x y) -> (SETEQF (UCOMISS x y)) 283 284 (Neq64 x y) -> (SETNE (CMPQ x y)) 285 (Neq32 x y) -> (SETNE (CMPL x y)) 286 (Neq16 x y) -> (SETNE (CMPW x y)) 287 (Neq8 x y) -> (SETNE (CMPB x y)) 288 (NeqB x y) -> (SETNE (CMPB x y)) 289 (NeqPtr x y) && config.PtrSize == 8 -> (SETNE (CMPQ x y)) 290 (NeqPtr x y) && config.PtrSize == 4 -> (SETNE (CMPL x y)) 291 (Neq64F x y) -> (SETNEF (UCOMISD x y)) 292 (Neq32F x y) -> (SETNEF (UCOMISS x y)) 293 294 (Int64Hi x) -> (SHRQconst [32] x) // needed for amd64p32 295 296 // Lowering loads 297 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t) && config.PtrSize == 8) -> (MOVQload ptr mem) 298 (Load <t> ptr mem) && (is32BitInt(t) || isPtr(t) && config.PtrSize == 4) -> (MOVLload ptr mem) 299 (Load <t> ptr mem) && is16BitInt(t) -> (MOVWload ptr mem) 300 (Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) -> (MOVBload ptr mem) 301 (Load <t> ptr mem) && is32BitFloat(t) -> (MOVSSload ptr mem) 302 (Load <t> ptr mem) && is64BitFloat(t) -> (MOVSDload ptr mem) 303 304 // Lowering stores 305 // These more-specific FP versions of Store pattern should come first. 306 (Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem) 307 (Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem) 308 309 (Store [8] ptr val mem) -> (MOVQstore ptr val mem) 310 (Store [4] ptr val mem) -> (MOVLstore ptr val mem) 311 (Store [2] ptr val mem) -> (MOVWstore ptr val mem) 312 (Store [1] ptr val mem) -> (MOVBstore ptr val mem) 313 314 // Lowering moves 315 (Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem 316 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBload src mem) mem) 317 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstore dst (MOVWload src mem) mem) 318 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstore dst (MOVLload src mem) mem) 319 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 -> (MOVQstore dst (MOVQload src mem) mem) 320 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 -> (MOVOstore dst (MOVOload src mem) mem) 321 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 -> 322 (MOVBstore [2] dst (MOVBload [2] src mem) 323 (MOVWstore dst (MOVWload src mem) mem)) 324 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 -> 325 (MOVBstore [4] dst (MOVBload [4] src mem) 326 (MOVLstore dst (MOVLload src mem) mem)) 327 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 -> 328 (MOVWstore [4] dst (MOVWload [4] src mem) 329 (MOVLstore dst (MOVLload src mem) mem)) 330 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 -> 331 (MOVLstore [3] dst (MOVLload [3] src mem) 332 (MOVLstore dst (MOVLload src mem) mem)) 333 (Move [s] dst src mem) && SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() < 16 -> 334 (MOVQstore [SizeAndAlign(s).Size()-8] dst (MOVQload [SizeAndAlign(s).Size()-8] src mem) 335 (MOVQstore dst (MOVQload src mem) mem)) 336 337 // Adjust moves to be a multiple of 16 bytes. 338 (Move [s] dst src mem) 339 && SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 <= 8 -> 340 (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%16] 341 (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()%16]) 342 (OffPtr <src.Type> src [SizeAndAlign(s).Size()%16]) 343 (MOVQstore dst (MOVQload src mem) mem)) 344 (Move [s] dst src mem) 345 && SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 > 8 -> 346 (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%16] 347 (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()%16]) 348 (OffPtr <src.Type> src [SizeAndAlign(s).Size()%16]) 349 (MOVOstore dst (MOVOload src mem) mem)) 350 351 // Medium copying uses a duff device. 352 (Move [s] dst src mem) 353 && SizeAndAlign(s).Size() >= 32 && SizeAndAlign(s).Size() <= 16*64 && SizeAndAlign(s).Size()%16 == 0 354 && !config.noDuffDevice -> 355 (DUFFCOPY [14*(64-SizeAndAlign(s).Size()/16)] dst src mem) 356 // 14 and 64 are magic constants. 14 is the number of bytes to encode: 357 // MOVUPS (SI), X0 358 // ADDQ $16, SI 359 // MOVUPS X0, (DI) 360 // ADDQ $16, DI 361 // and 64 is the number of such blocks. See src/runtime/duff_amd64.s:duffcopy. 362 363 // Large copying uses REP MOVSQ. 364 (Move [s] dst src mem) && (SizeAndAlign(s).Size() > 16*64 || config.noDuffDevice) && SizeAndAlign(s).Size()%8 == 0 -> 365 (REPMOVSQ dst src (MOVQconst [SizeAndAlign(s).Size()/8]) mem) 366 367 // Lowering Zero instructions 368 (Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem 369 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem) 370 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstoreconst [0] destptr mem) 371 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstoreconst [0] destptr mem) 372 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 -> (MOVQstoreconst [0] destptr mem) 373 374 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 -> 375 (MOVBstoreconst [makeValAndOff(0,2)] destptr 376 (MOVWstoreconst [0] destptr mem)) 377 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 5 -> 378 (MOVBstoreconst [makeValAndOff(0,4)] destptr 379 (MOVLstoreconst [0] destptr mem)) 380 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 6 -> 381 (MOVWstoreconst [makeValAndOff(0,4)] destptr 382 (MOVLstoreconst [0] destptr mem)) 383 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 7 -> 384 (MOVLstoreconst [makeValAndOff(0,3)] destptr 385 (MOVLstoreconst [0] destptr mem)) 386 387 // Strip off any fractional word zeroing. 388 (Zero [s] destptr mem) && SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8 -> 389 (Zero [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8] (OffPtr <destptr.Type> destptr [SizeAndAlign(s).Size()%8]) 390 (MOVQstoreconst [0] destptr mem)) 391 392 // Zero small numbers of words directly. 393 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 -> 394 (MOVQstoreconst [makeValAndOff(0,8)] destptr 395 (MOVQstoreconst [0] destptr mem)) 396 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 24 -> 397 (MOVQstoreconst [makeValAndOff(0,16)] destptr 398 (MOVQstoreconst [makeValAndOff(0,8)] destptr 399 (MOVQstoreconst [0] destptr mem))) 400 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 32 -> 401 (MOVQstoreconst [makeValAndOff(0,24)] destptr 402 (MOVQstoreconst [makeValAndOff(0,16)] destptr 403 (MOVQstoreconst [makeValAndOff(0,8)] destptr 404 (MOVQstoreconst [0] destptr mem)))) 405 406 // Medium zeroing uses a duff device. 407 (Zero [s] destptr mem) 408 && SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size()%16 != 0 409 && !config.noDuffDevice -> 410 (Zero [SizeAndAlign(s).Size()-8] (OffPtr <destptr.Type> [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem)) 411 (Zero [s] destptr mem) 412 && SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%16 == 0 && !config.noDuffDevice -> 413 (DUFFZERO [SizeAndAlign(s).Size()] destptr (MOVOconst [0]) mem) 414 415 // Large zeroing uses REP STOSQ. 416 (Zero [s] destptr mem) 417 && (SizeAndAlign(s).Size() > 1024 || (config.noDuffDevice && SizeAndAlign(s).Size() > 32)) 418 && SizeAndAlign(s).Size()%8 == 0 -> 419 (REPSTOSQ destptr (MOVQconst [SizeAndAlign(s).Size()/8]) (MOVQconst [0]) mem) 420 421 // Lowering constants 422 (Const8 [val]) -> (MOVLconst [val]) 423 (Const16 [val]) -> (MOVLconst [val]) 424 (Const32 [val]) -> (MOVLconst [val]) 425 (Const64 [val]) -> (MOVQconst [val]) 426 (Const32F [val]) -> (MOVSSconst [val]) 427 (Const64F [val]) -> (MOVSDconst [val]) 428 (ConstNil) && config.PtrSize == 8 -> (MOVQconst [0]) 429 (ConstNil) && config.PtrSize == 4 -> (MOVLconst [0]) 430 (ConstBool [b]) -> (MOVLconst [b]) 431 432 // Lowering calls 433 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 434 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 435 (DeferCall [argwid] mem) -> (CALLdefer [argwid] mem) 436 (GoCall [argwid] mem) -> (CALLgo [argwid] mem) 437 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 438 439 // Miscellaneous 440 (Convert <t> x mem) && config.PtrSize == 8 -> (MOVQconvert <t> x mem) 441 (Convert <t> x mem) && config.PtrSize == 4 -> (MOVLconvert <t> x mem) 442 (IsNonNil p) && config.PtrSize == 8 -> (SETNE (TESTQ p p)) 443 (IsNonNil p) && config.PtrSize == 4 -> (SETNE (TESTL p p)) 444 (IsInBounds idx len) -> (SETB (CMPQ idx len)) 445 (IsSliceInBounds idx len) -> (SETBE (CMPQ idx len)) 446 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 447 (GetG mem) -> (LoweredGetG mem) 448 (GetClosurePtr) -> (LoweredGetClosurePtr) 449 (Addr {sym} base) && config.PtrSize == 8 -> (LEAQ {sym} base) 450 (Addr {sym} base) && config.PtrSize == 4 -> (LEAL {sym} base) 451 452 // block rewrites 453 (If (SETL cmp) yes no) -> (LT cmp yes no) 454 (If (SETLE cmp) yes no) -> (LE cmp yes no) 455 (If (SETG cmp) yes no) -> (GT cmp yes no) 456 (If (SETGE cmp) yes no) -> (GE cmp yes no) 457 (If (SETEQ cmp) yes no) -> (EQ cmp yes no) 458 (If (SETNE cmp) yes no) -> (NE cmp yes no) 459 (If (SETB cmp) yes no) -> (ULT cmp yes no) 460 (If (SETBE cmp) yes no) -> (ULE cmp yes no) 461 (If (SETA cmp) yes no) -> (UGT cmp yes no) 462 (If (SETAE cmp) yes no) -> (UGE cmp yes no) 463 464 // Special case for floating point - LF/LEF not generated 465 (If (SETGF cmp) yes no) -> (UGT cmp yes no) 466 (If (SETGEF cmp) yes no) -> (UGE cmp yes no) 467 (If (SETEQF cmp) yes no) -> (EQF cmp yes no) 468 (If (SETNEF cmp) yes no) -> (NEF cmp yes no) 469 470 (If cond yes no) -> (NE (TESTB cond cond) yes no) 471 472 // Atomic loads. Other than preserving their ordering with respect to other loads, nothing special here. 473 (AtomicLoad32 ptr mem) -> (MOVLatomicload ptr mem) 474 (AtomicLoad64 ptr mem) -> (MOVQatomicload ptr mem) 475 (AtomicLoadPtr ptr mem) && config.PtrSize == 8 -> (MOVQatomicload ptr mem) 476 (AtomicLoadPtr ptr mem) && config.PtrSize == 4 -> (MOVLatomicload ptr mem) 477 478 // Atomic stores. We use XCHG to prevent the hardware reordering a subsequent load. 479 // TODO: most runtime uses of atomic stores don't need that property. Use normal stores for those? 480 (AtomicStore32 ptr val mem) -> (Select1 (XCHGL <MakeTuple(config.Frontend().TypeUInt32(),TypeMem)> val ptr mem)) 481 (AtomicStore64 ptr val mem) -> (Select1 (XCHGQ <MakeTuple(config.Frontend().TypeUInt64(),TypeMem)> val ptr mem)) 482 (AtomicStorePtrNoWB ptr val mem) && config.PtrSize == 8 -> (Select1 (XCHGQ <MakeTuple(config.Frontend().TypeBytePtr(),TypeMem)> val ptr mem)) 483 (AtomicStorePtrNoWB ptr val mem) && config.PtrSize == 4 -> (Select1 (XCHGL <MakeTuple(config.Frontend().TypeBytePtr(),TypeMem)> val ptr mem)) 484 485 // Atomic exchanges. 486 (AtomicExchange32 ptr val mem) -> (XCHGL val ptr mem) 487 (AtomicExchange64 ptr val mem) -> (XCHGQ val ptr mem) 488 489 // Atomic adds. 490 (AtomicAdd32 ptr val mem) -> (AddTupleFirst32 (XADDLlock val ptr mem) val) 491 (AtomicAdd64 ptr val mem) -> (AddTupleFirst64 (XADDQlock val ptr mem) val) 492 (Select0 <t> (AddTupleFirst32 tuple val)) -> (ADDL val (Select0 <t> tuple)) 493 (Select1 (AddTupleFirst32 tuple _ )) -> (Select1 tuple) 494 (Select0 <t> (AddTupleFirst64 tuple val)) -> (ADDQ val (Select0 <t> tuple)) 495 (Select1 (AddTupleFirst64 tuple _ )) -> (Select1 tuple) 496 497 // Atomic compare and swap. 498 (AtomicCompareAndSwap32 ptr old new_ mem) -> (CMPXCHGLlock ptr old new_ mem) 499 (AtomicCompareAndSwap64 ptr old new_ mem) -> (CMPXCHGQlock ptr old new_ mem) 500 501 // Atomic memory updates. 502 (AtomicAnd8 ptr val mem) -> (ANDBlock ptr val mem) 503 (AtomicOr8 ptr val mem) -> (ORBlock ptr val mem) 504 505 // *************************** 506 // Above: lowering rules 507 // Below: optimizations 508 // *************************** 509 // TODO: Should the optimizations be a separate pass? 510 511 // Fold boolean tests into blocks 512 (NE (TESTB (SETL cmp) (SETL cmp)) yes no) -> (LT cmp yes no) 513 (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) -> (LE cmp yes no) 514 (NE (TESTB (SETG cmp) (SETG cmp)) yes no) -> (GT cmp yes no) 515 (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) -> (GE cmp yes no) 516 (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) -> (EQ cmp yes no) 517 (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) -> (NE cmp yes no) 518 (NE (TESTB (SETB cmp) (SETB cmp)) yes no) -> (ULT cmp yes no) 519 (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) -> (ULE cmp yes no) 520 (NE (TESTB (SETA cmp) (SETA cmp)) yes no) -> (UGT cmp yes no) 521 (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) -> (UGE cmp yes no) 522 523 // Special case for floating point - LF/LEF not generated 524 (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) -> (UGT cmp yes no) 525 (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) -> (UGE cmp yes no) 526 (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) -> (EQF cmp yes no) 527 (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) -> (NEF cmp yes no) 528 529 // Disabled because it interferes with the pattern match above and makes worse code. 530 // (SETNEF x) -> (ORQ (SETNE <config.Frontend().TypeInt8()> x) (SETNAN <config.Frontend().TypeInt8()> x)) 531 // (SETEQF x) -> (ANDQ (SETEQ <config.Frontend().TypeInt8()> x) (SETORD <config.Frontend().TypeInt8()> x)) 532 533 // fold constants into instructions 534 (ADDQ x (MOVQconst [c])) && is32Bit(c) -> (ADDQconst [c] x) 535 (ADDQ (MOVQconst [c]) x) && is32Bit(c) -> (ADDQconst [c] x) 536 (ADDL x (MOVLconst [c])) -> (ADDLconst [c] x) 537 (ADDL (MOVLconst [c]) x) -> (ADDLconst [c] x) 538 539 (SUBQ x (MOVQconst [c])) && is32Bit(c) -> (SUBQconst x [c]) 540 (SUBQ (MOVQconst [c]) x) && is32Bit(c) -> (NEGQ (SUBQconst <v.Type> x [c])) 541 (SUBL x (MOVLconst [c])) -> (SUBLconst x [c]) 542 (SUBL (MOVLconst [c]) x) -> (NEGL (SUBLconst <v.Type> x [c])) 543 544 (MULQ x (MOVQconst [c])) && is32Bit(c) -> (MULQconst [c] x) 545 (MULQ (MOVQconst [c]) x) && is32Bit(c) -> (MULQconst [c] x) 546 (MULL x (MOVLconst [c])) -> (MULLconst [c] x) 547 (MULL (MOVLconst [c]) x) -> (MULLconst [c] x) 548 549 (ANDQ x (MOVQconst [c])) && is32Bit(c) -> (ANDQconst [c] x) 550 (ANDQ (MOVQconst [c]) x) && is32Bit(c) -> (ANDQconst [c] x) 551 (ANDL x (MOVLconst [c])) -> (ANDLconst [c] x) 552 (ANDL (MOVLconst [c]) x) -> (ANDLconst [c] x) 553 554 (ANDLconst [c] (ANDLconst [d] x)) -> (ANDLconst [c & d] x) 555 (ANDQconst [c] (ANDQconst [d] x)) -> (ANDQconst [c & d] x) 556 557 (XORLconst [c] (XORLconst [d] x)) -> (XORLconst [c ^ d] x) 558 (XORQconst [c] (XORQconst [d] x)) -> (XORQconst [c ^ d] x) 559 560 (MULLconst [c] (MULLconst [d] x)) -> (MULLconst [int64(int32(c * d))] x) 561 (MULQconst [c] (MULQconst [d] x)) && is32Bit(c*d) -> (MULQconst [c * d] x) 562 563 (ORQ x (MOVQconst [c])) && is32Bit(c) -> (ORQconst [c] x) 564 (ORQ (MOVQconst [c]) x) && is32Bit(c) -> (ORQconst [c] x) 565 (ORL x (MOVLconst [c])) -> (ORLconst [c] x) 566 (ORL (MOVLconst [c]) x) -> (ORLconst [c] x) 567 568 (XORQ x (MOVQconst [c])) && is32Bit(c) -> (XORQconst [c] x) 569 (XORQ (MOVQconst [c]) x) && is32Bit(c) -> (XORQconst [c] x) 570 (XORL x (MOVLconst [c])) -> (XORLconst [c] x) 571 (XORL (MOVLconst [c]) x) -> (XORLconst [c] x) 572 573 (SHLQ x (MOVQconst [c])) -> (SHLQconst [c&63] x) 574 (SHLQ x (MOVLconst [c])) -> (SHLQconst [c&63] x) 575 576 (SHLL x (MOVQconst [c])) -> (SHLLconst [c&31] x) 577 (SHLL x (MOVLconst [c])) -> (SHLLconst [c&31] x) 578 579 (SHRQ x (MOVQconst [c])) -> (SHRQconst [c&63] x) 580 (SHRQ x (MOVLconst [c])) -> (SHRQconst [c&63] x) 581 582 (SHRL x (MOVQconst [c])) -> (SHRLconst [c&31] x) 583 (SHRL x (MOVLconst [c])) -> (SHRLconst [c&31] x) 584 585 (SHRW x (MOVQconst [c])) -> (SHRWconst [c&31] x) 586 (SHRW x (MOVLconst [c])) -> (SHRWconst [c&31] x) 587 588 (SHRB x (MOVQconst [c])) -> (SHRBconst [c&31] x) 589 (SHRB x (MOVLconst [c])) -> (SHRBconst [c&31] x) 590 591 (SARQ x (MOVQconst [c])) -> (SARQconst [c&63] x) 592 (SARQ x (MOVLconst [c])) -> (SARQconst [c&63] x) 593 594 (SARL x (MOVQconst [c])) -> (SARLconst [c&31] x) 595 (SARL x (MOVLconst [c])) -> (SARLconst [c&31] x) 596 597 (SARW x (MOVQconst [c])) -> (SARWconst [c&31] x) 598 (SARW x (MOVLconst [c])) -> (SARWconst [c&31] x) 599 600 (SARB x (MOVQconst [c])) -> (SARBconst [c&31] x) 601 (SARB x (MOVLconst [c])) -> (SARBconst [c&31] x) 602 603 (SARL x (ANDLconst [31] y)) -> (SARL x y) 604 (SARQ x (ANDQconst [63] y)) -> (SARQ x y) 605 606 (SHLL x (ANDLconst [31] y)) -> (SHLL x y) 607 (SHLQ x (ANDQconst [63] y)) -> (SHLQ x y) 608 609 (SHRL x (ANDLconst [31] y)) -> (SHRL x y) 610 (SHRQ x (ANDQconst [63] y)) -> (SHRQ x y) 611 612 (ROLQconst [c] (ROLQconst [d] x)) -> (ROLQconst [(c+d)&63] x) 613 (ROLLconst [c] (ROLLconst [d] x)) -> (ROLLconst [(c+d)&31] x) 614 (ROLWconst [c] (ROLWconst [d] x)) -> (ROLWconst [(c+d)&15] x) 615 (ROLBconst [c] (ROLBconst [d] x)) -> (ROLBconst [(c+d)& 7] x) 616 617 (ROLQconst [0] x) -> x 618 (ROLLconst [0] x) -> x 619 (ROLWconst [0] x) -> x 620 (ROLBconst [0] x) -> x 621 622 // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits) 623 // because the x86 instructions are defined to use all 5 bits of the shift even 624 // for the small shifts. I don't think we'll ever generate a weird shift (e.g. 625 // (SHRW x (MOVLconst [24])), but just in case. 626 627 (CMPQ x (MOVQconst [c])) && is32Bit(c) -> (CMPQconst x [c]) 628 (CMPQ (MOVQconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPQconst x [c])) 629 (CMPL x (MOVLconst [c])) -> (CMPLconst x [c]) 630 (CMPL (MOVLconst [c]) x) -> (InvertFlags (CMPLconst x [c])) 631 (CMPW x (MOVLconst [c])) -> (CMPWconst x [int64(int16(c))]) 632 (CMPW (MOVLconst [c]) x) -> (InvertFlags (CMPWconst x [int64(int16(c))])) 633 (CMPB x (MOVLconst [c])) -> (CMPBconst x [int64(int8(c))]) 634 (CMPB (MOVLconst [c]) x) -> (InvertFlags (CMPBconst x [int64(int8(c))])) 635 636 // Using MOVZX instead of AND is cheaper. 637 (ANDLconst [0xFF] x) -> (MOVBQZX x) 638 (ANDLconst [0xFFFF] x) -> (MOVWQZX x) 639 (ANDQconst [0xFF] x) -> (MOVBQZX x) 640 (ANDQconst [0xFFFF] x) -> (MOVWQZX x) 641 (ANDQconst [0xFFFFFFFF] x) -> (MOVLQZX x) 642 643 // strength reduction 644 // Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf: 645 // 1 - addq, shlq, leaq, negq 646 // 3 - imulq 647 // This limits the rewrites to two instructions. 648 // TODO: 27, 81 649 (MULQconst [-1] x) -> (NEGQ x) 650 (MULQconst [0] _) -> (MOVQconst [0]) 651 (MULQconst [1] x) -> x 652 (MULQconst [3] x) -> (LEAQ2 x x) 653 (MULQconst [5] x) -> (LEAQ4 x x) 654 (MULQconst [7] x) -> (LEAQ8 (NEGQ <v.Type> x) x) 655 (MULQconst [9] x) -> (LEAQ8 x x) 656 (MULQconst [11] x) -> (LEAQ2 x (LEAQ4 <v.Type> x x)) 657 (MULQconst [13] x) -> (LEAQ4 x (LEAQ2 <v.Type> x x)) 658 (MULQconst [21] x) -> (LEAQ4 x (LEAQ4 <v.Type> x x)) 659 (MULQconst [25] x) -> (LEAQ8 x (LEAQ2 <v.Type> x x)) 660 (MULQconst [37] x) -> (LEAQ4 x (LEAQ8 <v.Type> x x)) 661 (MULQconst [41] x) -> (LEAQ8 x (LEAQ4 <v.Type> x x)) 662 (MULQconst [73] x) -> (LEAQ8 x (LEAQ8 <v.Type> x x)) 663 664 (MULQconst [c] x) && isPowerOfTwo(c) -> (SHLQconst [log2(c)] x) 665 (MULQconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUBQ (SHLQconst <v.Type> [log2(c+1)] x) x) 666 (MULQconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (LEAQ1 (SHLQconst <v.Type> [log2(c-1)] x) x) 667 (MULQconst [c] x) && isPowerOfTwo(c-2) && c >= 34 -> (LEAQ2 (SHLQconst <v.Type> [log2(c-2)] x) x) 668 (MULQconst [c] x) && isPowerOfTwo(c-4) && c >= 68 -> (LEAQ4 (SHLQconst <v.Type> [log2(c-4)] x) x) 669 (MULQconst [c] x) && isPowerOfTwo(c-8) && c >= 136 -> (LEAQ8 (SHLQconst <v.Type> [log2(c-8)] x) x) 670 (MULQconst [c] x) && c%3 == 0 && isPowerOfTwo(c/3)-> (SHLQconst [log2(c/3)] (LEAQ2 <v.Type> x x)) 671 (MULQconst [c] x) && c%5 == 0 && isPowerOfTwo(c/5)-> (SHLQconst [log2(c/5)] (LEAQ4 <v.Type> x x)) 672 (MULQconst [c] x) && c%9 == 0 && isPowerOfTwo(c/9)-> (SHLQconst [log2(c/9)] (LEAQ8 <v.Type> x x)) 673 674 // combine add/shift into LEAQ 675 (ADDQ x (SHLQconst [3] y)) -> (LEAQ8 x y) 676 (ADDQ x (SHLQconst [2] y)) -> (LEAQ4 x y) 677 (ADDQ x (SHLQconst [1] y)) -> (LEAQ2 x y) 678 (ADDQ x (ADDQ y y)) -> (LEAQ2 x y) 679 (ADDQ x (ADDQ x y)) -> (LEAQ2 y x) 680 (ADDQ x (ADDQ y x)) -> (LEAQ2 y x) 681 682 // combine ADDQ/ADDQconst into LEAQ1 683 (ADDQconst [c] (ADDQ x y)) -> (LEAQ1 [c] x y) 684 (ADDQ (ADDQconst [c] x) y) -> (LEAQ1 [c] x y) 685 (ADDQ x (ADDQconst [c] y)) -> (LEAQ1 [c] x y) 686 687 // fold ADDQ into LEAQ 688 (ADDQconst [c] (LEAQ [d] {s} x)) && is32Bit(c+d) -> (LEAQ [c+d] {s} x) 689 (LEAQ [c] {s} (ADDQconst [d] x)) && is32Bit(c+d) -> (LEAQ [c+d] {s} x) 690 (LEAQ [c] {s} (ADDQ x y)) && x.Op != OpSB && y.Op != OpSB -> (LEAQ1 [c] {s} x y) 691 (ADDQ x (LEAQ [c] {s} y)) && x.Op != OpSB && y.Op != OpSB -> (LEAQ1 [c] {s} x y) 692 (ADDQ (LEAQ [c] {s} x) y) && x.Op != OpSB && y.Op != OpSB -> (LEAQ1 [c] {s} x y) 693 694 // fold ADDQconst into LEAQx 695 (ADDQconst [c] (LEAQ1 [d] {s} x y)) && is32Bit(c+d) -> (LEAQ1 [c+d] {s} x y) 696 (ADDQconst [c] (LEAQ2 [d] {s} x y)) && is32Bit(c+d) -> (LEAQ2 [c+d] {s} x y) 697 (ADDQconst [c] (LEAQ4 [d] {s} x y)) && is32Bit(c+d) -> (LEAQ4 [c+d] {s} x y) 698 (ADDQconst [c] (LEAQ8 [d] {s} x y)) && is32Bit(c+d) -> (LEAQ8 [c+d] {s} x y) 699 (LEAQ1 [c] {s} (ADDQconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAQ1 [c+d] {s} x y) 700 (LEAQ1 [c] {s} x (ADDQconst [d] y)) && is32Bit(c+d) && y.Op != OpSB -> (LEAQ1 [c+d] {s} x y) 701 (LEAQ2 [c] {s} (ADDQconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAQ2 [c+d] {s} x y) 702 (LEAQ2 [c] {s} x (ADDQconst [d] y)) && is32Bit(c+2*d) && y.Op != OpSB -> (LEAQ2 [c+2*d] {s} x y) 703 (LEAQ4 [c] {s} (ADDQconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAQ4 [c+d] {s} x y) 704 (LEAQ4 [c] {s} x (ADDQconst [d] y)) && is32Bit(c+4*d) && y.Op != OpSB -> (LEAQ4 [c+4*d] {s} x y) 705 (LEAQ8 [c] {s} (ADDQconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAQ8 [c+d] {s} x y) 706 (LEAQ8 [c] {s} x (ADDQconst [d] y)) && is32Bit(c+8*d) && y.Op != OpSB -> (LEAQ8 [c+8*d] {s} x y) 707 708 // fold shifts into LEAQx 709 (LEAQ1 [c] {s} x (SHLQconst [1] y)) -> (LEAQ2 [c] {s} x y) 710 (LEAQ1 [c] {s} (SHLQconst [1] x) y) -> (LEAQ2 [c] {s} y x) 711 (LEAQ1 [c] {s} x (SHLQconst [2] y)) -> (LEAQ4 [c] {s} x y) 712 (LEAQ1 [c] {s} (SHLQconst [2] x) y) -> (LEAQ4 [c] {s} y x) 713 (LEAQ1 [c] {s} x (SHLQconst [3] y)) -> (LEAQ8 [c] {s} x y) 714 (LEAQ1 [c] {s} (SHLQconst [3] x) y) -> (LEAQ8 [c] {s} y x) 715 716 (LEAQ2 [c] {s} x (SHLQconst [1] y)) -> (LEAQ4 [c] {s} x y) 717 (LEAQ2 [c] {s} x (SHLQconst [2] y)) -> (LEAQ8 [c] {s} x y) 718 (LEAQ4 [c] {s} x (SHLQconst [1] y)) -> (LEAQ8 [c] {s} x y) 719 720 // reverse ordering of compare instruction 721 (SETL (InvertFlags x)) -> (SETG x) 722 (SETG (InvertFlags x)) -> (SETL x) 723 (SETB (InvertFlags x)) -> (SETA x) 724 (SETA (InvertFlags x)) -> (SETB x) 725 (SETLE (InvertFlags x)) -> (SETGE x) 726 (SETGE (InvertFlags x)) -> (SETLE x) 727 (SETBE (InvertFlags x)) -> (SETAE x) 728 (SETAE (InvertFlags x)) -> (SETBE x) 729 (SETEQ (InvertFlags x)) -> (SETEQ x) 730 (SETNE (InvertFlags x)) -> (SETNE x) 731 732 // sign extended loads 733 // Note: The combined instruction must end up in the same block 734 // as the original load. If not, we end up making a value with 735 // memory type live in two different blocks, which can lead to 736 // multiple memory values alive simultaneously. 737 // Make sure we don't combine these ops if the load has another use. 738 // This prevents a single load from being split into multiple loads 739 // which then might return different values. See test/atomicload.go. 740 (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem) 741 (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem) 742 (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem) 743 (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem) 744 (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 745 (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 746 (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 747 (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 748 (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem) 749 (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem) 750 (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem) 751 (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 752 (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 753 (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 754 (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem) 755 (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem) 756 (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVLload <v.Type> [off] {sym} ptr mem) 757 (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVLload <v.Type> [off] {sym} ptr mem) 758 759 (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem) 760 (MOVWQZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx1 <v.Type> [off] {sym} ptr idx mem) 761 (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem) 762 (MOVLQZX x:(MOVLloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVLloadidx1 <v.Type> [off] {sym} ptr idx mem) 763 (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVLloadidx4 <v.Type> [off] {sym} ptr idx mem) 764 765 // replace load from same location as preceding store with copy 766 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 767 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 768 (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 769 (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 770 771 // Fold extensions and ANDs together. 772 (MOVBQZX (ANDLconst [c] x)) -> (ANDLconst [c & 0xff] x) 773 (MOVWQZX (ANDLconst [c] x)) -> (ANDLconst [c & 0xffff] x) 774 (MOVLQZX (ANDLconst [c] x)) -> (ANDLconst [c] x) 775 (MOVBQSX (ANDLconst [c] x)) && c & 0x80 == 0 -> (ANDLconst [c & 0x7f] x) 776 (MOVWQSX (ANDLconst [c] x)) && c & 0x8000 == 0 -> (ANDLconst [c & 0x7fff] x) 777 (MOVLQSX (ANDLconst [c] x)) && c & 0x80000000 == 0 -> (ANDLconst [c & 0x7fffffff] x) 778 779 // Don't extend before storing 780 (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) -> (MOVLstore [off] {sym} ptr x mem) 781 (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) -> (MOVWstore [off] {sym} ptr x mem) 782 (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) -> (MOVBstore [off] {sym} ptr x mem) 783 (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) -> (MOVLstore [off] {sym} ptr x mem) 784 (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) -> (MOVWstore [off] {sym} ptr x mem) 785 (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) -> (MOVBstore [off] {sym} ptr x mem) 786 787 // fold constants into memory operations 788 // Note that this is not always a good idea because if not all the uses of 789 // the ADDQconst get eliminated, we still have to compute the ADDQconst and we now 790 // have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one. 791 // Nevertheless, let's do it! 792 (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVQload [off1+off2] {sym} ptr mem) 793 (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVLload [off1+off2] {sym} ptr mem) 794 (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 795 (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 796 (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVSSload [off1+off2] {sym} ptr mem) 797 (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVSDload [off1+off2] {sym} ptr mem) 798 (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVOload [off1+off2] {sym} ptr mem) 799 800 (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVQstore [off1+off2] {sym} ptr val mem) 801 (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVLstore [off1+off2] {sym} ptr val mem) 802 (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 803 (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 804 (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVSSstore [off1+off2] {sym} ptr val mem) 805 (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVSDstore [off1+off2] {sym} ptr val mem) 806 (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVOstore [off1+off2] {sym} ptr val mem) 807 808 // Fold constants into stores. 809 (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validValAndOff(c,off) -> 810 (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 811 (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> 812 (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) 813 (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> 814 (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) 815 (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) && validOff(off) -> 816 (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) 817 818 // Fold address offsets into constant stores. 819 (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 820 (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 821 (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 822 (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 823 (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 824 (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 825 (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 826 (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 827 828 // We need to fold LEAQ into the MOVx ops so that the live variable analysis knows 829 // what variables are being read/written by the ops. 830 (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 831 (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) 832 (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 833 (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) 834 (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 835 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) 836 (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 837 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) 838 (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 839 (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) 840 (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 841 (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 842 (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 843 (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) 844 845 (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 846 (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) 847 (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 848 (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) 849 (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 850 (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) 851 852 (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 853 (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 854 (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 855 (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 856 (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 857 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 858 (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 859 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 860 (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 861 (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 862 (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 863 (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 864 (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 865 (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 866 867 (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 868 (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 869 (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 870 (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 871 (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 872 (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 873 (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 874 (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 875 876 // generating indexed loads and stores 877 (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 878 (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 879 (MOVWload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 880 (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 881 (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 882 (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 883 (MOVLload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 884 (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 885 (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 886 (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 887 (MOVQload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 888 (MOVQloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 889 (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 890 (MOVQloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 891 (MOVSSload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 892 (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 893 (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 894 (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 895 (MOVSDload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 896 (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 897 (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 898 (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 899 900 (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 901 (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 902 (MOVWstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 903 (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 904 (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 905 (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 906 (MOVLstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 907 (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 908 (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 909 (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 910 (MOVQstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 911 (MOVQstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 912 (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 913 (MOVQstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 914 (MOVSSstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 915 (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 916 (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 917 (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 918 (MOVSDstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 919 (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 920 (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 921 (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 922 923 (MOVBload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVBloadidx1 [off] {sym} ptr idx mem) 924 (MOVWload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVWloadidx1 [off] {sym} ptr idx mem) 925 (MOVLload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVLloadidx1 [off] {sym} ptr idx mem) 926 (MOVQload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVQloadidx1 [off] {sym} ptr idx mem) 927 (MOVSSload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVSSloadidx1 [off] {sym} ptr idx mem) 928 (MOVSDload [off] {sym} (ADDQ ptr idx) mem) && ptr.Op != OpSB -> (MOVSDloadidx1 [off] {sym} ptr idx mem) 929 (MOVBstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx1 [off] {sym} ptr idx val mem) 930 (MOVWstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx1 [off] {sym} ptr idx val mem) 931 (MOVLstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVLstoreidx1 [off] {sym} ptr idx val mem) 932 (MOVQstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVQstoreidx1 [off] {sym} ptr idx val mem) 933 (MOVSSstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVSSstoreidx1 [off] {sym} ptr idx val mem) 934 (MOVSDstore [off] {sym} (ADDQ ptr idx) val mem) && ptr.Op != OpSB -> (MOVSDstoreidx1 [off] {sym} ptr idx val mem) 935 936 (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 937 (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 938 (MOVWstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 939 (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 940 (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 941 (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 942 (MOVLstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 943 (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 944 (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 945 (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 946 (MOVQstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 947 (MOVQstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 948 (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) -> 949 (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) 950 951 (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) -> (MOVBstoreconstidx1 [x] {sym} ptr idx mem) 952 (MOVWstoreconst [x] {sym} (ADDQ ptr idx) mem) -> (MOVWstoreconstidx1 [x] {sym} ptr idx mem) 953 (MOVLstoreconst [x] {sym} (ADDQ ptr idx) mem) -> (MOVLstoreconstidx1 [x] {sym} ptr idx mem) 954 (MOVQstoreconst [x] {sym} (ADDQ ptr idx) mem) -> (MOVQstoreconstidx1 [x] {sym} ptr idx mem) 955 956 // combine SHLQ into indexed loads and stores 957 (MOVWloadidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) -> (MOVWloadidx2 [c] {sym} ptr idx mem) 958 (MOVLloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) -> (MOVLloadidx4 [c] {sym} ptr idx mem) 959 (MOVQloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) -> (MOVQloadidx8 [c] {sym} ptr idx mem) 960 (MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) -> (MOVSSloadidx4 [c] {sym} ptr idx mem) 961 (MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) -> (MOVSDloadidx8 [c] {sym} ptr idx mem) 962 (MOVWstoreidx1 [c] {sym} ptr (SHLQconst [1] idx) val mem) -> (MOVWstoreidx2 [c] {sym} ptr idx val mem) 963 (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) -> (MOVLstoreidx4 [c] {sym} ptr idx val mem) 964 (MOVQstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) -> (MOVQstoreidx8 [c] {sym} ptr idx val mem) 965 (MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) -> (MOVSSstoreidx4 [c] {sym} ptr idx val mem) 966 (MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) -> (MOVSDstoreidx8 [c] {sym} ptr idx val mem) 967 (MOVWstoreconstidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) -> (MOVWstoreconstidx2 [c] {sym} ptr idx mem) 968 (MOVLstoreconstidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) -> (MOVLstoreconstidx4 [c] {sym} ptr idx mem) 969 (MOVQstoreconstidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) -> (MOVQstoreconstidx8 [c] {sym} ptr idx mem) 970 971 // combine ADDQ into indexed loads and stores 972 (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVBloadidx1 [c+d] {sym} ptr idx mem) 973 (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVWloadidx1 [c+d] {sym} ptr idx mem) 974 (MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVWloadidx2 [c+d] {sym} ptr idx mem) 975 (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVLloadidx1 [c+d] {sym} ptr idx mem) 976 (MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVLloadidx4 [c+d] {sym} ptr idx mem) 977 (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVQloadidx1 [c+d] {sym} ptr idx mem) 978 (MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVQloadidx8 [c+d] {sym} ptr idx mem) 979 (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVSSloadidx1 [c+d] {sym} ptr idx mem) 980 (MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVSSloadidx4 [c+d] {sym} ptr idx mem) 981 (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVSDloadidx1 [c+d] {sym} ptr idx mem) 982 (MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) -> (MOVSDloadidx8 [c+d] {sym} ptr idx mem) 983 984 (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) 985 (MOVWstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) 986 (MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) 987 (MOVLstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) 988 (MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) 989 (MOVQstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) 990 (MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) 991 (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) 992 (MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) 993 (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) 994 (MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) -> (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) 995 996 (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVBloadidx1 [c+d] {sym} ptr idx mem) 997 (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVWloadidx1 [c+d] {sym} ptr idx mem) 998 (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) 999 (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVLloadidx1 [c+d] {sym} ptr idx mem) 1000 (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) 1001 (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVQloadidx1 [c+d] {sym} ptr idx mem) 1002 (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) 1003 (MOVSSloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVSSloadidx1 [c+d] {sym} ptr idx mem) 1004 (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) 1005 (MOVSDloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVSDloadidx1 [c+d] {sym} ptr idx mem) 1006 (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) -> (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) 1007 1008 (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) 1009 (MOVWstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) 1010 (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) 1011 (MOVLstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) 1012 (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) 1013 (MOVQstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) 1014 (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) 1015 (MOVSSstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) 1016 (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) 1017 (MOVSDstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) 1018 (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) -> (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) 1019 1020 (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1021 (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1022 (MOVWstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1023 (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1024 (MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1025 (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1026 (MOVLstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1027 (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1028 (MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1029 (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1030 (MOVQstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1031 (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1032 (MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) -> 1033 (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1034 1035 (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1036 (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1037 (MOVWstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1038 (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1039 (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1040 (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) 1041 (MOVLstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1042 (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1043 (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1044 (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) 1045 (MOVQstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1046 (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) 1047 (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) -> 1048 (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) 1049 1050 // fold LEAQs together 1051 (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1052 (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) 1053 1054 // LEAQ into LEAQ1 1055 (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 1056 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) 1057 (LEAQ1 [off1] {sym1} x (LEAQ [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB -> 1058 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) 1059 1060 // LEAQ1 into LEAQ 1061 (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1062 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) 1063 1064 // LEAQ into LEAQ[248] 1065 (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 1066 (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) 1067 (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 1068 (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) 1069 (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 1070 (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) 1071 1072 // LEAQ[248] into LEAQ 1073 (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1074 (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) 1075 (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1076 (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) 1077 (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1078 (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) 1079 1080 // Absorb InvertFlags into branches. 1081 (LT (InvertFlags cmp) yes no) -> (GT cmp yes no) 1082 (GT (InvertFlags cmp) yes no) -> (LT cmp yes no) 1083 (LE (InvertFlags cmp) yes no) -> (GE cmp yes no) 1084 (GE (InvertFlags cmp) yes no) -> (LE cmp yes no) 1085 (ULT (InvertFlags cmp) yes no) -> (UGT cmp yes no) 1086 (UGT (InvertFlags cmp) yes no) -> (ULT cmp yes no) 1087 (ULE (InvertFlags cmp) yes no) -> (UGE cmp yes no) 1088 (UGE (InvertFlags cmp) yes no) -> (ULE cmp yes no) 1089 (EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) 1090 (NE (InvertFlags cmp) yes no) -> (NE cmp yes no) 1091 1092 // Constant comparisons. 1093 (CMPQconst (MOVQconst [x]) [y]) && x==y -> (FlagEQ) 1094 (CMPQconst (MOVQconst [x]) [y]) && x<y && uint64(x)<uint64(y) -> (FlagLT_ULT) 1095 (CMPQconst (MOVQconst [x]) [y]) && x<y && uint64(x)>uint64(y) -> (FlagLT_UGT) 1096 (CMPQconst (MOVQconst [x]) [y]) && x>y && uint64(x)<uint64(y) -> (FlagGT_ULT) 1097 (CMPQconst (MOVQconst [x]) [y]) && x>y && uint64(x)>uint64(y) -> (FlagGT_UGT) 1098 (CMPLconst (MOVLconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 1099 (CMPLconst (MOVLconst [x]) [y]) && int32(x)<int32(y) && uint32(x)<uint32(y) -> (FlagLT_ULT) 1100 (CMPLconst (MOVLconst [x]) [y]) && int32(x)<int32(y) && uint32(x)>uint32(y) -> (FlagLT_UGT) 1101 (CMPLconst (MOVLconst [x]) [y]) && int32(x)>int32(y) && uint32(x)<uint32(y) -> (FlagGT_ULT) 1102 (CMPLconst (MOVLconst [x]) [y]) && int32(x)>int32(y) && uint32(x)>uint32(y) -> (FlagGT_UGT) 1103 (CMPWconst (MOVLconst [x]) [y]) && int16(x)==int16(y) -> (FlagEQ) 1104 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<int16(y) && uint16(x)<uint16(y) -> (FlagLT_ULT) 1105 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<int16(y) && uint16(x)>uint16(y) -> (FlagLT_UGT) 1106 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>int16(y) && uint16(x)<uint16(y) -> (FlagGT_ULT) 1107 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>int16(y) && uint16(x)>uint16(y) -> (FlagGT_UGT) 1108 (CMPBconst (MOVLconst [x]) [y]) && int8(x)==int8(y) -> (FlagEQ) 1109 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<int8(y) && uint8(x)<uint8(y) -> (FlagLT_ULT) 1110 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<int8(y) && uint8(x)>uint8(y) -> (FlagLT_UGT) 1111 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>int8(y) && uint8(x)<uint8(y) -> (FlagGT_ULT) 1112 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>int8(y) && uint8(x)>uint8(y) -> (FlagGT_UGT) 1113 1114 // Other known comparisons. 1115 (CMPQconst (MOVBQZX _) [c]) && 0xFF < c -> (FlagLT_ULT) 1116 (CMPQconst (MOVWQZX _) [c]) && 0xFFFF < c -> (FlagLT_ULT) 1117 (CMPQconst (MOVLQZX _) [c]) && 0xFFFFFFFF < c -> (FlagLT_ULT) 1118 (CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) -> (FlagLT_ULT) 1119 (CMPQconst (SHRQconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) -> (FlagLT_ULT) 1120 (CMPQconst (ANDQconst _ [m]) [n]) && 0 <= m && m < n -> (FlagLT_ULT) 1121 (CMPLconst (ANDLconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT_ULT) 1122 (CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < int16(n) -> (FlagLT_ULT) 1123 (CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < int8(n) -> (FlagLT_ULT) 1124 // TODO: DIVxU also. 1125 1126 // Absorb flag constants into SBB ops. 1127 (SBBQcarrymask (FlagEQ)) -> (MOVQconst [0]) 1128 (SBBQcarrymask (FlagLT_ULT)) -> (MOVQconst [-1]) 1129 (SBBQcarrymask (FlagLT_UGT)) -> (MOVQconst [0]) 1130 (SBBQcarrymask (FlagGT_ULT)) -> (MOVQconst [-1]) 1131 (SBBQcarrymask (FlagGT_UGT)) -> (MOVQconst [0]) 1132 (SBBLcarrymask (FlagEQ)) -> (MOVLconst [0]) 1133 (SBBLcarrymask (FlagLT_ULT)) -> (MOVLconst [-1]) 1134 (SBBLcarrymask (FlagLT_UGT)) -> (MOVLconst [0]) 1135 (SBBLcarrymask (FlagGT_ULT)) -> (MOVLconst [-1]) 1136 (SBBLcarrymask (FlagGT_UGT)) -> (MOVLconst [0]) 1137 1138 // Absorb flag constants into branches. 1139 (EQ (FlagEQ) yes no) -> (First nil yes no) 1140 (EQ (FlagLT_ULT) yes no) -> (First nil no yes) 1141 (EQ (FlagLT_UGT) yes no) -> (First nil no yes) 1142 (EQ (FlagGT_ULT) yes no) -> (First nil no yes) 1143 (EQ (FlagGT_UGT) yes no) -> (First nil no yes) 1144 1145 (NE (FlagEQ) yes no) -> (First nil no yes) 1146 (NE (FlagLT_ULT) yes no) -> (First nil yes no) 1147 (NE (FlagLT_UGT) yes no) -> (First nil yes no) 1148 (NE (FlagGT_ULT) yes no) -> (First nil yes no) 1149 (NE (FlagGT_UGT) yes no) -> (First nil yes no) 1150 1151 (LT (FlagEQ) yes no) -> (First nil no yes) 1152 (LT (FlagLT_ULT) yes no) -> (First nil yes no) 1153 (LT (FlagLT_UGT) yes no) -> (First nil yes no) 1154 (LT (FlagGT_ULT) yes no) -> (First nil no yes) 1155 (LT (FlagGT_UGT) yes no) -> (First nil no yes) 1156 1157 (LE (FlagEQ) yes no) -> (First nil yes no) 1158 (LE (FlagLT_ULT) yes no) -> (First nil yes no) 1159 (LE (FlagLT_UGT) yes no) -> (First nil yes no) 1160 (LE (FlagGT_ULT) yes no) -> (First nil no yes) 1161 (LE (FlagGT_UGT) yes no) -> (First nil no yes) 1162 1163 (GT (FlagEQ) yes no) -> (First nil no yes) 1164 (GT (FlagLT_ULT) yes no) -> (First nil no yes) 1165 (GT (FlagLT_UGT) yes no) -> (First nil no yes) 1166 (GT (FlagGT_ULT) yes no) -> (First nil yes no) 1167 (GT (FlagGT_UGT) yes no) -> (First nil yes no) 1168 1169 (GE (FlagEQ) yes no) -> (First nil yes no) 1170 (GE (FlagLT_ULT) yes no) -> (First nil no yes) 1171 (GE (FlagLT_UGT) yes no) -> (First nil no yes) 1172 (GE (FlagGT_ULT) yes no) -> (First nil yes no) 1173 (GE (FlagGT_UGT) yes no) -> (First nil yes no) 1174 1175 (ULT (FlagEQ) yes no) -> (First nil no yes) 1176 (ULT (FlagLT_ULT) yes no) -> (First nil yes no) 1177 (ULT (FlagLT_UGT) yes no) -> (First nil no yes) 1178 (ULT (FlagGT_ULT) yes no) -> (First nil yes no) 1179 (ULT (FlagGT_UGT) yes no) -> (First nil no yes) 1180 1181 (ULE (FlagEQ) yes no) -> (First nil yes no) 1182 (ULE (FlagLT_ULT) yes no) -> (First nil yes no) 1183 (ULE (FlagLT_UGT) yes no) -> (First nil no yes) 1184 (ULE (FlagGT_ULT) yes no) -> (First nil yes no) 1185 (ULE (FlagGT_UGT) yes no) -> (First nil no yes) 1186 1187 (UGT (FlagEQ) yes no) -> (First nil no yes) 1188 (UGT (FlagLT_ULT) yes no) -> (First nil no yes) 1189 (UGT (FlagLT_UGT) yes no) -> (First nil yes no) 1190 (UGT (FlagGT_ULT) yes no) -> (First nil no yes) 1191 (UGT (FlagGT_UGT) yes no) -> (First nil yes no) 1192 1193 (UGE (FlagEQ) yes no) -> (First nil yes no) 1194 (UGE (FlagLT_ULT) yes no) -> (First nil no yes) 1195 (UGE (FlagLT_UGT) yes no) -> (First nil yes no) 1196 (UGE (FlagGT_ULT) yes no) -> (First nil no yes) 1197 (UGE (FlagGT_UGT) yes no) -> (First nil yes no) 1198 1199 // Absorb flag constants into SETxx ops. 1200 (SETEQ (FlagEQ)) -> (MOVLconst [1]) 1201 (SETEQ (FlagLT_ULT)) -> (MOVLconst [0]) 1202 (SETEQ (FlagLT_UGT)) -> (MOVLconst [0]) 1203 (SETEQ (FlagGT_ULT)) -> (MOVLconst [0]) 1204 (SETEQ (FlagGT_UGT)) -> (MOVLconst [0]) 1205 1206 (SETNE (FlagEQ)) -> (MOVLconst [0]) 1207 (SETNE (FlagLT_ULT)) -> (MOVLconst [1]) 1208 (SETNE (FlagLT_UGT)) -> (MOVLconst [1]) 1209 (SETNE (FlagGT_ULT)) -> (MOVLconst [1]) 1210 (SETNE (FlagGT_UGT)) -> (MOVLconst [1]) 1211 1212 (SETL (FlagEQ)) -> (MOVLconst [0]) 1213 (SETL (FlagLT_ULT)) -> (MOVLconst [1]) 1214 (SETL (FlagLT_UGT)) -> (MOVLconst [1]) 1215 (SETL (FlagGT_ULT)) -> (MOVLconst [0]) 1216 (SETL (FlagGT_UGT)) -> (MOVLconst [0]) 1217 1218 (SETLE (FlagEQ)) -> (MOVLconst [1]) 1219 (SETLE (FlagLT_ULT)) -> (MOVLconst [1]) 1220 (SETLE (FlagLT_UGT)) -> (MOVLconst [1]) 1221 (SETLE (FlagGT_ULT)) -> (MOVLconst [0]) 1222 (SETLE (FlagGT_UGT)) -> (MOVLconst [0]) 1223 1224 (SETG (FlagEQ)) -> (MOVLconst [0]) 1225 (SETG (FlagLT_ULT)) -> (MOVLconst [0]) 1226 (SETG (FlagLT_UGT)) -> (MOVLconst [0]) 1227 (SETG (FlagGT_ULT)) -> (MOVLconst [1]) 1228 (SETG (FlagGT_UGT)) -> (MOVLconst [1]) 1229 1230 (SETGE (FlagEQ)) -> (MOVLconst [1]) 1231 (SETGE (FlagLT_ULT)) -> (MOVLconst [0]) 1232 (SETGE (FlagLT_UGT)) -> (MOVLconst [0]) 1233 (SETGE (FlagGT_ULT)) -> (MOVLconst [1]) 1234 (SETGE (FlagGT_UGT)) -> (MOVLconst [1]) 1235 1236 (SETB (FlagEQ)) -> (MOVLconst [0]) 1237 (SETB (FlagLT_ULT)) -> (MOVLconst [1]) 1238 (SETB (FlagLT_UGT)) -> (MOVLconst [0]) 1239 (SETB (FlagGT_ULT)) -> (MOVLconst [1]) 1240 (SETB (FlagGT_UGT)) -> (MOVLconst [0]) 1241 1242 (SETBE (FlagEQ)) -> (MOVLconst [1]) 1243 (SETBE (FlagLT_ULT)) -> (MOVLconst [1]) 1244 (SETBE (FlagLT_UGT)) -> (MOVLconst [0]) 1245 (SETBE (FlagGT_ULT)) -> (MOVLconst [1]) 1246 (SETBE (FlagGT_UGT)) -> (MOVLconst [0]) 1247 1248 (SETA (FlagEQ)) -> (MOVLconst [0]) 1249 (SETA (FlagLT_ULT)) -> (MOVLconst [0]) 1250 (SETA (FlagLT_UGT)) -> (MOVLconst [1]) 1251 (SETA (FlagGT_ULT)) -> (MOVLconst [0]) 1252 (SETA (FlagGT_UGT)) -> (MOVLconst [1]) 1253 1254 (SETAE (FlagEQ)) -> (MOVLconst [1]) 1255 (SETAE (FlagLT_ULT)) -> (MOVLconst [0]) 1256 (SETAE (FlagLT_UGT)) -> (MOVLconst [1]) 1257 (SETAE (FlagGT_ULT)) -> (MOVLconst [0]) 1258 (SETAE (FlagGT_UGT)) -> (MOVLconst [1]) 1259 1260 // Remove redundant *const ops 1261 (ADDQconst [0] x) -> x 1262 (ADDLconst [c] x) && int32(c)==0 -> x 1263 (SUBQconst [0] x) -> x 1264 (SUBLconst [c] x) && int32(c) == 0 -> x 1265 (ANDQconst [0] _) -> (MOVQconst [0]) 1266 (ANDLconst [c] _) && int32(c)==0 -> (MOVLconst [0]) 1267 (ANDQconst [-1] x) -> x 1268 (ANDLconst [c] x) && int32(c)==-1 -> x 1269 (ORQconst [0] x) -> x 1270 (ORLconst [c] x) && int32(c)==0 -> x 1271 (ORQconst [-1] _) -> (MOVQconst [-1]) 1272 (ORLconst [c] _) && int32(c)==-1 -> (MOVLconst [-1]) 1273 (XORQconst [0] x) -> x 1274 (XORLconst [c] x) && int32(c)==0 -> x 1275 // TODO: since we got rid of the W/B versions, we might miss 1276 // things like (ANDLconst [0x100] x) which were formerly 1277 // (ANDBconst [0] x). Probably doesn't happen very often. 1278 // If we cared, we might do: 1279 // (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 -> (MOVLconst [0]) 1280 1281 // Convert constant subtracts to constant adds 1282 (SUBQconst [c] x) && c != -(1<<31) -> (ADDQconst [-c] x) 1283 (SUBLconst [c] x) -> (ADDLconst [int64(int32(-c))] x) 1284 1285 // generic constant folding 1286 // TODO: more of this 1287 (ADDQconst [c] (MOVQconst [d])) -> (MOVQconst [c+d]) 1288 (ADDLconst [c] (MOVLconst [d])) -> (MOVLconst [int64(int32(c+d))]) 1289 (ADDQconst [c] (ADDQconst [d] x)) && is32Bit(c+d) -> (ADDQconst [c+d] x) 1290 (ADDLconst [c] (ADDLconst [d] x)) -> (ADDLconst [int64(int32(c+d))] x) 1291 (SUBQconst (MOVQconst [d]) [c]) -> (MOVQconst [d-c]) 1292 (SUBQconst (SUBQconst x [d]) [c]) && is32Bit(-c-d) -> (ADDQconst [-c-d] x) 1293 (SARQconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) 1294 (SARLconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) 1295 (SARWconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) 1296 (SARBconst [c] (MOVQconst [d])) -> (MOVQconst [d>>uint64(c)]) 1297 (NEGQ (MOVQconst [c])) -> (MOVQconst [-c]) 1298 (NEGL (MOVLconst [c])) -> (MOVLconst [int64(int32(-c))]) 1299 (MULQconst [c] (MOVQconst [d])) -> (MOVQconst [c*d]) 1300 (MULLconst [c] (MOVLconst [d])) -> (MOVLconst [int64(int32(c*d))]) 1301 (ANDQconst [c] (MOVQconst [d])) -> (MOVQconst [c&d]) 1302 (ANDLconst [c] (MOVLconst [d])) -> (MOVLconst [c&d]) 1303 (ORQconst [c] (MOVQconst [d])) -> (MOVQconst [c|d]) 1304 (ORLconst [c] (MOVLconst [d])) -> (MOVLconst [c|d]) 1305 (XORQconst [c] (MOVQconst [d])) -> (MOVQconst [c^d]) 1306 (XORLconst [c] (MOVLconst [d])) -> (MOVLconst [c^d]) 1307 (NOTQ (MOVQconst [c])) -> (MOVQconst [^c]) 1308 (NOTL (MOVLconst [c])) -> (MOVLconst [^c]) 1309 1310 // generic simplifications 1311 // TODO: more of this 1312 (ADDQ x (NEGQ y)) -> (SUBQ x y) 1313 (ADDL x (NEGL y)) -> (SUBL x y) 1314 (SUBQ x x) -> (MOVQconst [0]) 1315 (SUBL x x) -> (MOVLconst [0]) 1316 (ANDQ x x) -> x 1317 (ANDL x x) -> x 1318 (ORQ x x) -> x 1319 (ORL x x) -> x 1320 (XORQ x x) -> (MOVQconst [0]) 1321 (XORL x x) -> (MOVLconst [0]) 1322 1323 // checking AND against 0. 1324 (CMPQconst (ANDQ x y) [0]) -> (TESTQ x y) 1325 (CMPLconst (ANDL x y) [0]) -> (TESTL x y) 1326 (CMPWconst (ANDL x y) [0]) -> (TESTW x y) 1327 (CMPBconst (ANDL x y) [0]) -> (TESTB x y) 1328 (CMPQconst (ANDQconst [c] x) [0]) -> (TESTQconst [c] x) 1329 (CMPLconst (ANDLconst [c] x) [0]) -> (TESTLconst [c] x) 1330 (CMPWconst (ANDLconst [c] x) [0]) -> (TESTWconst [int64(int16(c))] x) 1331 (CMPBconst (ANDLconst [c] x) [0]) -> (TESTBconst [int64(int8(c))] x) 1332 1333 // TEST %reg,%reg is shorter than CMP 1334 (CMPQconst x [0]) -> (TESTQ x x) 1335 (CMPLconst x [0]) -> (TESTL x x) 1336 (CMPWconst x [0]) -> (TESTW x x) 1337 (CMPBconst x [0]) -> (TESTB x x) 1338 1339 // Combining byte loads into larger (unaligned) loads. 1340 // There are many ways these combinations could occur. This is 1341 // designed to match the way encoding/binary.LittleEndian does it. 1342 (ORL x0:(MOVBload [i] {s} p mem) 1343 s0:(SHLLconst [8] x1:(MOVBload [i+1] {s} p mem))) 1344 && x0.Uses == 1 1345 && x1.Uses == 1 1346 && s0.Uses == 1 1347 && mergePoint(b,x0,x1) != nil 1348 && clobber(x0) 1349 && clobber(x1) 1350 && clobber(s0) 1351 -> @mergePoint(b,x0,x1) (MOVWload [i] {s} p mem) 1352 1353 (ORL o0:(ORL 1354 x0:(MOVWload [i] {s} p mem) 1355 s0:(SHLLconst [16] x1:(MOVBload [i+2] {s} p mem))) 1356 s1:(SHLLconst [24] x2:(MOVBload [i+3] {s} p mem))) 1357 && x0.Uses == 1 1358 && x1.Uses == 1 1359 && x2.Uses == 1 1360 && s0.Uses == 1 1361 && s1.Uses == 1 1362 && o0.Uses == 1 1363 && mergePoint(b,x0,x1,x2) != nil 1364 && clobber(x0) 1365 && clobber(x1) 1366 && clobber(x2) 1367 && clobber(s0) 1368 && clobber(s1) 1369 && clobber(o0) 1370 -> @mergePoint(b,x0,x1,x2) (MOVLload [i] {s} p mem) 1371 1372 (ORQ o0:(ORQ o1:(ORQ o2:(ORQ o3:(ORQ o4:(ORQ o5:(ORQ 1373 x0:(MOVBload [i] {s} p mem) 1374 s0:(SHLQconst [8] x1:(MOVBload [i+1] {s} p mem))) 1375 s1:(SHLQconst [16] x2:(MOVBload [i+2] {s} p mem))) 1376 s2:(SHLQconst [24] x3:(MOVBload [i+3] {s} p mem))) 1377 s3:(SHLQconst [32] x4:(MOVBload [i+4] {s} p mem))) 1378 s4:(SHLQconst [40] x5:(MOVBload [i+5] {s} p mem))) 1379 s5:(SHLQconst [48] x6:(MOVBload [i+6] {s} p mem))) 1380 s6:(SHLQconst [56] x7:(MOVBload [i+7] {s} p mem))) 1381 && x0.Uses == 1 1382 && x1.Uses == 1 1383 && x2.Uses == 1 1384 && x3.Uses == 1 1385 && x4.Uses == 1 1386 && x5.Uses == 1 1387 && x6.Uses == 1 1388 && x7.Uses == 1 1389 && s0.Uses == 1 1390 && s1.Uses == 1 1391 && s2.Uses == 1 1392 && s3.Uses == 1 1393 && s4.Uses == 1 1394 && s5.Uses == 1 1395 && s6.Uses == 1 1396 && o0.Uses == 1 1397 && o1.Uses == 1 1398 && o2.Uses == 1 1399 && o3.Uses == 1 1400 && o4.Uses == 1 1401 && o5.Uses == 1 1402 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1403 && clobber(x0) 1404 && clobber(x1) 1405 && clobber(x2) 1406 && clobber(x3) 1407 && clobber(x4) 1408 && clobber(x5) 1409 && clobber(x6) 1410 && clobber(x7) 1411 && clobber(s0) 1412 && clobber(s1) 1413 && clobber(s2) 1414 && clobber(s3) 1415 && clobber(s4) 1416 && clobber(s5) 1417 && clobber(s6) 1418 && clobber(o0) 1419 && clobber(o1) 1420 && clobber(o2) 1421 && clobber(o3) 1422 && clobber(o4) 1423 && clobber(o5) 1424 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVQload [i] {s} p mem) 1425 1426 (ORL x0:(MOVBloadidx1 [i] {s} p idx mem) 1427 s0:(SHLLconst [8] x1:(MOVBloadidx1 [i+1] {s} p idx mem))) 1428 && x0.Uses == 1 1429 && x1.Uses == 1 1430 && s0.Uses == 1 1431 && mergePoint(b,x0,x1) != nil 1432 && clobber(x0) 1433 && clobber(x1) 1434 && clobber(s0) 1435 -> @mergePoint(b,x0,x1) (MOVWloadidx1 <v.Type> [i] {s} p idx mem) 1436 1437 (ORL o0:(ORL 1438 x0:(MOVWloadidx1 [i] {s} p idx mem) 1439 s0:(SHLLconst [16] x1:(MOVBloadidx1 [i+2] {s} p idx mem))) 1440 s1:(SHLLconst [24] x2:(MOVBloadidx1 [i+3] {s} p idx mem))) 1441 && x0.Uses == 1 1442 && x1.Uses == 1 1443 && x2.Uses == 1 1444 && s0.Uses == 1 1445 && s1.Uses == 1 1446 && o0.Uses == 1 1447 && mergePoint(b,x0,x1,x2) != nil 1448 && clobber(x0) 1449 && clobber(x1) 1450 && clobber(x2) 1451 && clobber(s0) 1452 && clobber(s1) 1453 && clobber(o0) 1454 -> @mergePoint(b,x0,x1,x2) (MOVLloadidx1 <v.Type> [i] {s} p idx mem) 1455 1456 (ORQ o0:(ORQ o1:(ORQ o2:(ORQ o3:(ORQ o4:(ORQ o5:(ORQ 1457 x0:(MOVBloadidx1 [i] {s} p idx mem) 1458 s0:(SHLQconst [8] x1:(MOVBloadidx1 [i+1] {s} p idx mem))) 1459 s1:(SHLQconst [16] x2:(MOVBloadidx1 [i+2] {s} p idx mem))) 1460 s2:(SHLQconst [24] x3:(MOVBloadidx1 [i+3] {s} p idx mem))) 1461 s3:(SHLQconst [32] x4:(MOVBloadidx1 [i+4] {s} p idx mem))) 1462 s4:(SHLQconst [40] x5:(MOVBloadidx1 [i+5] {s} p idx mem))) 1463 s5:(SHLQconst [48] x6:(MOVBloadidx1 [i+6] {s} p idx mem))) 1464 s6:(SHLQconst [56] x7:(MOVBloadidx1 [i+7] {s} p idx mem))) 1465 && x0.Uses == 1 1466 && x1.Uses == 1 1467 && x2.Uses == 1 1468 && x3.Uses == 1 1469 && x4.Uses == 1 1470 && x5.Uses == 1 1471 && x6.Uses == 1 1472 && x7.Uses == 1 1473 && s0.Uses == 1 1474 && s1.Uses == 1 1475 && s2.Uses == 1 1476 && s3.Uses == 1 1477 && s4.Uses == 1 1478 && s5.Uses == 1 1479 && s6.Uses == 1 1480 && o0.Uses == 1 1481 && o1.Uses == 1 1482 && o2.Uses == 1 1483 && o3.Uses == 1 1484 && o4.Uses == 1 1485 && o5.Uses == 1 1486 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1487 && clobber(x0) 1488 && clobber(x1) 1489 && clobber(x2) 1490 && clobber(x3) 1491 && clobber(x4) 1492 && clobber(x5) 1493 && clobber(x6) 1494 && clobber(x7) 1495 && clobber(s0) 1496 && clobber(s1) 1497 && clobber(s2) 1498 && clobber(s3) 1499 && clobber(s4) 1500 && clobber(s5) 1501 && clobber(s6) 1502 && clobber(o0) 1503 && clobber(o1) 1504 && clobber(o2) 1505 && clobber(o3) 1506 && clobber(o4) 1507 && clobber(o5) 1508 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVQloadidx1 <v.Type> [i] {s} p idx mem) 1509 1510 // Combine byte loads + shifts into larger (unaligned) loads + bswap 1511 (ORL o1:(ORL o0:(ORL 1512 x0:(MOVBload [i] {s} p mem) 1513 s0:(SHLLconst [8] x1:(MOVBload [i-1] {s} p mem))) 1514 s1:(SHLLconst [16] x2:(MOVBload [i-2] {s} p mem))) 1515 s2:(SHLLconst [24] x3:(MOVBload [i-3] {s} p mem))) 1516 && x0.Uses == 1 1517 && x1.Uses == 1 1518 && x2.Uses == 1 1519 && x3.Uses == 1 1520 && s0.Uses == 1 1521 && s1.Uses == 1 1522 && s2.Uses == 1 1523 && o0.Uses == 1 1524 && o1.Uses == 1 1525 && mergePoint(b,x0,x1,x2,x3) != nil 1526 && clobber(x0) 1527 && clobber(x1) 1528 && clobber(x2) 1529 && clobber(x3) 1530 && clobber(s0) 1531 && clobber(s1) 1532 && clobber(s2) 1533 && clobber(o0) 1534 && clobber(o1) 1535 -> @mergePoint(b,x0,x1,x2,x3) (BSWAPL <v.Type> (MOVLload [i-3] {s} p mem)) 1536 1537 (ORL o1:(ORL o0:(ORL 1538 x0:(MOVBloadidx1 [i] {s} p idx mem) 1539 s0:(SHLLconst [8] x1:(MOVBloadidx1 [i-1] {s} p idx mem))) 1540 s1:(SHLLconst [16] x2:(MOVBloadidx1 [i-2] {s} p idx mem))) 1541 s2:(SHLLconst [24] x3:(MOVBloadidx1 [i-3] {s} p idx mem))) 1542 && x0.Uses == 1 1543 && x1.Uses == 1 1544 && x2.Uses == 1 1545 && x3.Uses == 1 1546 && s0.Uses == 1 1547 && s1.Uses == 1 1548 && s2.Uses == 1 1549 && o0.Uses == 1 1550 && o1.Uses == 1 1551 && mergePoint(b,x0,x1,x2,x3) != nil 1552 && clobber(x0) 1553 && clobber(x1) 1554 && clobber(x2) 1555 && clobber(x3) 1556 && clobber(s0) 1557 && clobber(s1) 1558 && clobber(s2) 1559 && clobber(o0) 1560 && clobber(o1) 1561 -> @mergePoint(b,x0,x1,x2,x3) (BSWAPL <v.Type> (MOVLloadidx1 <v.Type> [i-3] {s} p idx mem)) 1562 1563 (ORQ o5:(ORQ o4:(ORQ o3:(ORQ o2:(ORQ o1:(ORQ o0:(ORQ 1564 x0:(MOVBload [i] {s} p mem) 1565 s0:(SHLQconst [8] x1:(MOVBload [i-1] {s} p mem))) 1566 s1:(SHLQconst [16] x2:(MOVBload [i-2] {s} p mem))) 1567 s2:(SHLQconst [24] x3:(MOVBload [i-3] {s} p mem))) 1568 s3:(SHLQconst [32] x4:(MOVBload [i-4] {s} p mem))) 1569 s4:(SHLQconst [40] x5:(MOVBload [i-5] {s} p mem))) 1570 s5:(SHLQconst [48] x6:(MOVBload [i-6] {s} p mem))) 1571 s6:(SHLQconst [56] x7:(MOVBload [i-7] {s} p mem))) 1572 && x0.Uses == 1 1573 && x1.Uses == 1 1574 && x2.Uses == 1 1575 && x3.Uses == 1 1576 && x4.Uses == 1 1577 && x5.Uses == 1 1578 && x6.Uses == 1 1579 && x7.Uses == 1 1580 && s0.Uses == 1 1581 && s1.Uses == 1 1582 && s2.Uses == 1 1583 && s3.Uses == 1 1584 && s4.Uses == 1 1585 && s5.Uses == 1 1586 && s6.Uses == 1 1587 && o0.Uses == 1 1588 && o1.Uses == 1 1589 && o2.Uses == 1 1590 && o3.Uses == 1 1591 && o4.Uses == 1 1592 && o5.Uses == 1 1593 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1594 && clobber(x0) 1595 && clobber(x1) 1596 && clobber(x2) 1597 && clobber(x3) 1598 && clobber(x4) 1599 && clobber(x5) 1600 && clobber(x6) 1601 && clobber(x7) 1602 && clobber(s0) 1603 && clobber(s1) 1604 && clobber(s2) 1605 && clobber(s3) 1606 && clobber(s4) 1607 && clobber(s5) 1608 && clobber(s6) 1609 && clobber(o0) 1610 && clobber(o1) 1611 && clobber(o2) 1612 && clobber(o3) 1613 && clobber(o4) 1614 && clobber(o5) 1615 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (BSWAPQ <v.Type> (MOVQload [i-7] {s} p mem)) 1616 1617 (ORQ o5:(ORQ o4:(ORQ o3:(ORQ o2:(ORQ o1:(ORQ o0:(ORQ 1618 x0:(MOVBloadidx1 [i] {s} p idx mem) 1619 s0:(SHLQconst [8] x1:(MOVBloadidx1 [i-1] {s} p idx mem))) 1620 s1:(SHLQconst [16] x2:(MOVBloadidx1 [i-2] {s} p idx mem))) 1621 s2:(SHLQconst [24] x3:(MOVBloadidx1 [i-3] {s} p idx mem))) 1622 s3:(SHLQconst [32] x4:(MOVBloadidx1 [i-4] {s} p idx mem))) 1623 s4:(SHLQconst [40] x5:(MOVBloadidx1 [i-5] {s} p idx mem))) 1624 s5:(SHLQconst [48] x6:(MOVBloadidx1 [i-6] {s} p idx mem))) 1625 s6:(SHLQconst [56] x7:(MOVBloadidx1 [i-7] {s} p idx mem))) 1626 && x0.Uses == 1 1627 && x1.Uses == 1 1628 && x2.Uses == 1 1629 && x3.Uses == 1 1630 && x4.Uses == 1 1631 && x5.Uses == 1 1632 && x6.Uses == 1 1633 && x7.Uses == 1 1634 && s0.Uses == 1 1635 && s1.Uses == 1 1636 && s2.Uses == 1 1637 && s3.Uses == 1 1638 && s4.Uses == 1 1639 && s5.Uses == 1 1640 && s6.Uses == 1 1641 && o0.Uses == 1 1642 && o1.Uses == 1 1643 && o2.Uses == 1 1644 && o3.Uses == 1 1645 && o4.Uses == 1 1646 && o5.Uses == 1 1647 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1648 && clobber(x0) 1649 && clobber(x1) 1650 && clobber(x2) 1651 && clobber(x3) 1652 && clobber(x4) 1653 && clobber(x5) 1654 && clobber(x6) 1655 && clobber(x7) 1656 && clobber(s0) 1657 && clobber(s1) 1658 && clobber(s2) 1659 && clobber(s3) 1660 && clobber(s4) 1661 && clobber(s5) 1662 && clobber(s6) 1663 && clobber(o0) 1664 && clobber(o1) 1665 && clobber(o2) 1666 && clobber(o3) 1667 && clobber(o4) 1668 && clobber(o5) 1669 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (BSWAPQ <v.Type> (MOVQloadidx1 <v.Type> [i-7] {s} p idx mem)) 1670 1671 // Combine stores + shifts into bswap and larger (unaligned) stores 1672 (MOVBstore [i] {s} p w 1673 x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) 1674 x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) 1675 x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) 1676 && x0.Uses == 1 1677 && x1.Uses == 1 1678 && x2.Uses == 1 1679 && clobber(x0) 1680 && clobber(x1) 1681 && clobber(x2) 1682 -> (MOVLstore [i-3] {s} p (BSWAPL <w.Type> w) mem) 1683 1684 (MOVBstore [i] {s} p w 1685 x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) 1686 x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) 1687 x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) 1688 x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) 1689 x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) 1690 x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) 1691 x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) 1692 && x0.Uses == 1 1693 && x1.Uses == 1 1694 && x2.Uses == 1 1695 && x3.Uses == 1 1696 && x4.Uses == 1 1697 && x5.Uses == 1 1698 && x6.Uses == 1 1699 && clobber(x0) 1700 && clobber(x1) 1701 && clobber(x2) 1702 && clobber(x3) 1703 && clobber(x4) 1704 && clobber(x5) 1705 && clobber(x6) 1706 -> (MOVQstore [i-7] {s} p (BSWAPQ <w.Type> w) mem) 1707 1708 // Combine constant stores into larger (unaligned) stores. 1709 (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) 1710 && x.Uses == 1 1711 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1712 && clobber(x) 1713 -> (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) 1714 (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) 1715 && x.Uses == 1 1716 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1717 && clobber(x) 1718 -> (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) 1719 (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) 1720 && x.Uses == 1 1721 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() 1722 && clobber(x) 1723 -> (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) 1724 1725 (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) 1726 && x.Uses == 1 1727 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1728 && clobber(x) 1729 -> (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) 1730 (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) 1731 && x.Uses == 1 1732 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1733 && clobber(x) 1734 -> (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) 1735 (MOVLstoreconstidx1 [c] {s} p i x:(MOVLstoreconstidx1 [a] {s} p i mem)) 1736 && x.Uses == 1 1737 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() 1738 && clobber(x) 1739 -> (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p i (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) 1740 1741 (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) 1742 && x.Uses == 1 1743 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1744 && clobber(x) 1745 -> (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLQconst <i.Type> [1] i) mem) 1746 (MOVLstoreconstidx4 [c] {s} p i x:(MOVLstoreconstidx4 [a] {s} p i mem)) 1747 && x.Uses == 1 1748 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() 1749 && clobber(x) 1750 -> (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p (SHLQconst <i.Type> [2] i) (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) 1751 1752 // Combine stores into larger (unaligned) stores. 1753 (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1754 && x.Uses == 1 1755 && clobber(x) 1756 -> (MOVWstore [i-1] {s} p w mem) 1757 (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) 1758 && x.Uses == 1 1759 && clobber(x) 1760 -> (MOVWstore [i-1] {s} p w0 mem) 1761 (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) 1762 && x.Uses == 1 1763 && clobber(x) 1764 -> (MOVLstore [i-2] {s} p w mem) 1765 (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) 1766 && x.Uses == 1 1767 && clobber(x) 1768 -> (MOVLstore [i-2] {s} p w0 mem) 1769 (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) 1770 && x.Uses == 1 1771 && clobber(x) 1772 -> (MOVQstore [i-4] {s} p w mem) 1773 (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) 1774 && x.Uses == 1 1775 && clobber(x) 1776 -> (MOVQstore [i-4] {s} p w0 mem) 1777 1778 (MOVBstoreidx1 [i] {s} p idx (SHRQconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) 1779 && x.Uses == 1 1780 && clobber(x) 1781 -> (MOVWstoreidx1 [i-1] {s} p idx w mem) 1782 (MOVBstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRQconst [j-8] w) mem)) 1783 && x.Uses == 1 1784 && clobber(x) 1785 -> (MOVWstoreidx1 [i-1] {s} p idx w0 mem) 1786 (MOVWstoreidx1 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) 1787 && x.Uses == 1 1788 && clobber(x) 1789 -> (MOVLstoreidx1 [i-2] {s} p idx w mem) 1790 (MOVWstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) 1791 && x.Uses == 1 1792 && clobber(x) 1793 -> (MOVLstoreidx1 [i-2] {s} p idx w0 mem) 1794 (MOVLstoreidx1 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx1 [i-4] {s} p idx w mem)) 1795 && x.Uses == 1 1796 && clobber(x) 1797 -> (MOVQstoreidx1 [i-4] {s} p idx w mem) 1798 (MOVLstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx1 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) 1799 && x.Uses == 1 1800 && clobber(x) 1801 -> (MOVQstoreidx1 [i-4] {s} p idx w0 mem) 1802 1803 (MOVWstoreidx2 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) 1804 && x.Uses == 1 1805 && clobber(x) 1806 -> (MOVLstoreidx1 [i-2] {s} p (SHLQconst <idx.Type> [1] idx) w mem) 1807 (MOVWstoreidx2 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) 1808 && x.Uses == 1 1809 && clobber(x) 1810 -> (MOVLstoreidx1 [i-2] {s} p (SHLQconst <idx.Type> [1] idx) w0 mem) 1811 (MOVLstoreidx4 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx4 [i-4] {s} p idx w mem)) 1812 && x.Uses == 1 1813 && clobber(x) 1814 -> (MOVQstoreidx1 [i-4] {s} p (SHLQconst <idx.Type> [2] idx) w mem) 1815 (MOVLstoreidx4 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx4 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) 1816 && x.Uses == 1 1817 && clobber(x) 1818 -> (MOVQstoreidx1 [i-4] {s} p (SHLQconst <idx.Type> [2] idx) w0 mem) 1819 1820 // amd64p32 rules 1821 // same as the rules above, but with 32 instead of 64 bit pointer arithmetic. 1822 // LEAQ,ADDQ -> LEAL,ADDL 1823 (ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x) 1824 (LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x) 1825 1826 (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> 1827 (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) 1828 (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> 1829 (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) 1830 (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> 1831 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) 1832 (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) && canMergeSym(sym1, sym2) -> 1833 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) 1834 1835 (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> 1836 (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 1837 (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> 1838 (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 1839 (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> 1840 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 1841 (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && canMergeSym(sym1, sym2) -> 1842 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 1843 1844 (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 1845 (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 1846 (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 1847 (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 1848 (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 1849 (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 1850 (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 1851 (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 1852 1853 (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVQload [off1+off2] {sym} ptr mem) 1854 (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVLload [off1+off2] {sym} ptr mem) 1855 (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 1856 (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 1857 (MOVQstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVQstore [off1+off2] {sym} ptr val mem) 1858 (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVLstore [off1+off2] {sym} ptr val mem) 1859 (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 1860 (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 1861 (MOVQstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 1862 (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 1863 (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 1864 (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 1865 (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 1866 (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 1867 (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 1868 (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 1869 1870 // Merge ADDQconst and LEAQ into atomic loads. 1871 (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> 1872 (MOVQatomicload [off1+off2] {sym} ptr mem) 1873 (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> 1874 (MOVLatomicload [off1+off2] {sym} ptr mem) 1875 (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1876 (MOVQatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 1877 (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 1878 (MOVLatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 1879 1880 // Merge ADDQconst and LEAQ into atomic stores. 1881 (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> 1882 (XCHGQ [off1+off2] {sym} val ptr mem) 1883 (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB -> 1884 (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) 1885 (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> 1886 (XCHGL [off1+off2] {sym} val ptr mem) 1887 (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB -> 1888 (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) 1889 1890 // Merge ADDQconst into atomic adds. 1891 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions. 1892 (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> 1893 (XADDQlock [off1+off2] {sym} val ptr mem) 1894 (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) -> 1895 (XADDLlock [off1+off2] {sym} val ptr mem) 1896 1897 // Merge ADDQconst into atomic compare and swaps. 1898 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions. 1899 (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(off1+off2) -> 1900 (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) 1901 (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(off1+off2) -> 1902 (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) 1903
