1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/s390x" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386ULT 26 Block386ULE 27 Block386UGT 28 Block386UGE 29 Block386EQF 30 Block386NEF 31 Block386ORD 32 Block386NAN 33 34 BlockAMD64EQ 35 BlockAMD64NE 36 BlockAMD64LT 37 BlockAMD64LE 38 BlockAMD64GT 39 BlockAMD64GE 40 BlockAMD64ULT 41 BlockAMD64ULE 42 BlockAMD64UGT 43 BlockAMD64UGE 44 BlockAMD64EQF 45 BlockAMD64NEF 46 BlockAMD64ORD 47 BlockAMD64NAN 48 49 BlockARMEQ 50 BlockARMNE 51 BlockARMLT 52 BlockARMLE 53 BlockARMGT 54 BlockARMGE 55 BlockARMULT 56 BlockARMULE 57 BlockARMUGT 58 BlockARMUGE 59 60 BlockARM64EQ 61 BlockARM64NE 62 BlockARM64LT 63 BlockARM64LE 64 BlockARM64GT 65 BlockARM64GE 66 BlockARM64ULT 67 BlockARM64ULE 68 BlockARM64UGT 69 BlockARM64UGE 70 BlockARM64Z 71 BlockARM64NZ 72 BlockARM64ZW 73 BlockARM64NZW 74 75 BlockMIPSEQ 76 BlockMIPSNE 77 BlockMIPSLTZ 78 BlockMIPSLEZ 79 BlockMIPSGTZ 80 BlockMIPSGEZ 81 BlockMIPSFPT 82 BlockMIPSFPF 83 84 BlockMIPS64EQ 85 BlockMIPS64NE 86 BlockMIPS64LTZ 87 BlockMIPS64LEZ 88 BlockMIPS64GTZ 89 BlockMIPS64GEZ 90 BlockMIPS64FPT 91 BlockMIPS64FPF 92 93 BlockPPC64EQ 94 BlockPPC64NE 95 BlockPPC64LT 96 BlockPPC64LE 97 BlockPPC64GT 98 BlockPPC64GE 99 BlockPPC64FLT 100 BlockPPC64FLE 101 BlockPPC64FGT 102 BlockPPC64FGE 103 104 BlockS390XEQ 105 BlockS390XNE 106 BlockS390XLT 107 BlockS390XLE 108 BlockS390XGT 109 BlockS390XGE 110 BlockS390XGTF 111 BlockS390XGEF 112 113 BlockPlain 114 BlockIf 115 BlockDefer 116 BlockRet 117 BlockRetJmp 118 BlockExit 119 BlockFirst 120 ) 121 122 var blockString = [...]string{ 123 BlockInvalid: "BlockInvalid", 124 125 Block386EQ: "EQ", 126 Block386NE: "NE", 127 Block386LT: "LT", 128 Block386LE: "LE", 129 Block386GT: "GT", 130 Block386GE: "GE", 131 Block386ULT: "ULT", 132 Block386ULE: "ULE", 133 Block386UGT: "UGT", 134 Block386UGE: "UGE", 135 Block386EQF: "EQF", 136 Block386NEF: "NEF", 137 Block386ORD: "ORD", 138 Block386NAN: "NAN", 139 140 BlockAMD64EQ: "EQ", 141 BlockAMD64NE: "NE", 142 BlockAMD64LT: "LT", 143 BlockAMD64LE: "LE", 144 BlockAMD64GT: "GT", 145 BlockAMD64GE: "GE", 146 BlockAMD64ULT: "ULT", 147 BlockAMD64ULE: "ULE", 148 BlockAMD64UGT: "UGT", 149 BlockAMD64UGE: "UGE", 150 BlockAMD64EQF: "EQF", 151 BlockAMD64NEF: "NEF", 152 BlockAMD64ORD: "ORD", 153 BlockAMD64NAN: "NAN", 154 155 BlockARMEQ: "EQ", 156 BlockARMNE: "NE", 157 BlockARMLT: "LT", 158 BlockARMLE: "LE", 159 BlockARMGT: "GT", 160 BlockARMGE: "GE", 161 BlockARMULT: "ULT", 162 BlockARMULE: "ULE", 163 BlockARMUGT: "UGT", 164 BlockARMUGE: "UGE", 165 166 BlockARM64EQ: "EQ", 167 BlockARM64NE: "NE", 168 BlockARM64LT: "LT", 169 BlockARM64LE: "LE", 170 BlockARM64GT: "GT", 171 BlockARM64GE: "GE", 172 BlockARM64ULT: "ULT", 173 BlockARM64ULE: "ULE", 174 BlockARM64UGT: "UGT", 175 BlockARM64UGE: "UGE", 176 BlockARM64Z: "Z", 177 BlockARM64NZ: "NZ", 178 BlockARM64ZW: "ZW", 179 BlockARM64NZW: "NZW", 180 181 BlockMIPSEQ: "EQ", 182 BlockMIPSNE: "NE", 183 BlockMIPSLTZ: "LTZ", 184 BlockMIPSLEZ: "LEZ", 185 BlockMIPSGTZ: "GTZ", 186 BlockMIPSGEZ: "GEZ", 187 BlockMIPSFPT: "FPT", 188 BlockMIPSFPF: "FPF", 189 190 BlockMIPS64EQ: "EQ", 191 BlockMIPS64NE: "NE", 192 BlockMIPS64LTZ: "LTZ", 193 BlockMIPS64LEZ: "LEZ", 194 BlockMIPS64GTZ: "GTZ", 195 BlockMIPS64GEZ: "GEZ", 196 BlockMIPS64FPT: "FPT", 197 BlockMIPS64FPF: "FPF", 198 199 BlockPPC64EQ: "EQ", 200 BlockPPC64NE: "NE", 201 BlockPPC64LT: "LT", 202 BlockPPC64LE: "LE", 203 BlockPPC64GT: "GT", 204 BlockPPC64GE: "GE", 205 BlockPPC64FLT: "FLT", 206 BlockPPC64FLE: "FLE", 207 BlockPPC64FGT: "FGT", 208 BlockPPC64FGE: "FGE", 209 210 BlockS390XEQ: "EQ", 211 BlockS390XNE: "NE", 212 BlockS390XLT: "LT", 213 BlockS390XLE: "LE", 214 BlockS390XGT: "GT", 215 BlockS390XGE: "GE", 216 BlockS390XGTF: "GTF", 217 BlockS390XGEF: "GEF", 218 219 BlockPlain: "Plain", 220 BlockIf: "If", 221 BlockDefer: "Defer", 222 BlockRet: "Ret", 223 BlockRetJmp: "RetJmp", 224 BlockExit: "Exit", 225 BlockFirst: "First", 226 } 227 228 func (k BlockKind) String() string { return blockString[k] } 229 230 const ( 231 OpInvalid Op = iota 232 233 Op386ADDSS 234 Op386ADDSD 235 Op386SUBSS 236 Op386SUBSD 237 Op386MULSS 238 Op386MULSD 239 Op386DIVSS 240 Op386DIVSD 241 Op386MOVSSload 242 Op386MOVSDload 243 Op386MOVSSconst 244 Op386MOVSDconst 245 Op386MOVSSloadidx1 246 Op386MOVSSloadidx4 247 Op386MOVSDloadidx1 248 Op386MOVSDloadidx8 249 Op386MOVSSstore 250 Op386MOVSDstore 251 Op386MOVSSstoreidx1 252 Op386MOVSSstoreidx4 253 Op386MOVSDstoreidx1 254 Op386MOVSDstoreidx8 255 Op386ADDL 256 Op386ADDLconst 257 Op386ADDLcarry 258 Op386ADDLconstcarry 259 Op386ADCL 260 Op386ADCLconst 261 Op386SUBL 262 Op386SUBLconst 263 Op386SUBLcarry 264 Op386SUBLconstcarry 265 Op386SBBL 266 Op386SBBLconst 267 Op386MULL 268 Op386MULLconst 269 Op386HMULL 270 Op386HMULLU 271 Op386HMULW 272 Op386HMULB 273 Op386HMULWU 274 Op386HMULBU 275 Op386MULLQU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLdefer 394 Op386CALLgo 395 Op386CALLinter 396 Op386DUFFCOPY 397 Op386REPMOVSL 398 Op386InvertFlags 399 Op386LoweredGetG 400 Op386LoweredGetClosurePtr 401 Op386LoweredNilCheck 402 Op386MOVLconvert 403 Op386FlagEQ 404 Op386FlagLT_ULT 405 Op386FlagLT_UGT 406 Op386FlagGT_UGT 407 Op386FlagGT_ULT 408 Op386FCHS 409 Op386MOVSSconst1 410 Op386MOVSDconst1 411 Op386MOVSSconst2 412 Op386MOVSDconst2 413 414 OpAMD64ADDSS 415 OpAMD64ADDSD 416 OpAMD64SUBSS 417 OpAMD64SUBSD 418 OpAMD64MULSS 419 OpAMD64MULSD 420 OpAMD64DIVSS 421 OpAMD64DIVSD 422 OpAMD64MOVSSload 423 OpAMD64MOVSDload 424 OpAMD64MOVSSconst 425 OpAMD64MOVSDconst 426 OpAMD64MOVSSloadidx1 427 OpAMD64MOVSSloadidx4 428 OpAMD64MOVSDloadidx1 429 OpAMD64MOVSDloadidx8 430 OpAMD64MOVSSstore 431 OpAMD64MOVSDstore 432 OpAMD64MOVSSstoreidx1 433 OpAMD64MOVSSstoreidx4 434 OpAMD64MOVSDstoreidx1 435 OpAMD64MOVSDstoreidx8 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULW 451 OpAMD64HMULB 452 OpAMD64HMULQU 453 OpAMD64HMULLU 454 OpAMD64HMULWU 455 OpAMD64HMULBU 456 OpAMD64AVGQU 457 OpAMD64DIVQ 458 OpAMD64DIVL 459 OpAMD64DIVW 460 OpAMD64DIVQU 461 OpAMD64DIVLU 462 OpAMD64DIVWU 463 OpAMD64MULQU2 464 OpAMD64DIVQU2 465 OpAMD64ANDQ 466 OpAMD64ANDL 467 OpAMD64ANDQconst 468 OpAMD64ANDLconst 469 OpAMD64ORQ 470 OpAMD64ORL 471 OpAMD64ORQconst 472 OpAMD64ORLconst 473 OpAMD64XORQ 474 OpAMD64XORL 475 OpAMD64XORQconst 476 OpAMD64XORLconst 477 OpAMD64CMPQ 478 OpAMD64CMPL 479 OpAMD64CMPW 480 OpAMD64CMPB 481 OpAMD64CMPQconst 482 OpAMD64CMPLconst 483 OpAMD64CMPWconst 484 OpAMD64CMPBconst 485 OpAMD64UCOMISS 486 OpAMD64UCOMISD 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQconst 516 OpAMD64ROLLconst 517 OpAMD64ROLWconst 518 OpAMD64ROLBconst 519 OpAMD64NEGQ 520 OpAMD64NEGL 521 OpAMD64NOTQ 522 OpAMD64NOTL 523 OpAMD64BSFQ 524 OpAMD64BSFL 525 OpAMD64CMOVQEQ 526 OpAMD64CMOVLEQ 527 OpAMD64BSWAPQ 528 OpAMD64BSWAPL 529 OpAMD64SQRTSD 530 OpAMD64SBBQcarrymask 531 OpAMD64SBBLcarrymask 532 OpAMD64SETEQ 533 OpAMD64SETNE 534 OpAMD64SETL 535 OpAMD64SETLE 536 OpAMD64SETG 537 OpAMD64SETGE 538 OpAMD64SETB 539 OpAMD64SETBE 540 OpAMD64SETA 541 OpAMD64SETAE 542 OpAMD64SETEQF 543 OpAMD64SETNEF 544 OpAMD64SETORD 545 OpAMD64SETNAN 546 OpAMD64SETGF 547 OpAMD64SETGEF 548 OpAMD64MOVBQSX 549 OpAMD64MOVBQZX 550 OpAMD64MOVWQSX 551 OpAMD64MOVWQZX 552 OpAMD64MOVLQSX 553 OpAMD64MOVLQZX 554 OpAMD64MOVLconst 555 OpAMD64MOVQconst 556 OpAMD64CVTTSD2SL 557 OpAMD64CVTTSD2SQ 558 OpAMD64CVTTSS2SL 559 OpAMD64CVTTSS2SQ 560 OpAMD64CVTSL2SS 561 OpAMD64CVTSL2SD 562 OpAMD64CVTSQ2SS 563 OpAMD64CVTSQ2SD 564 OpAMD64CVTSD2SS 565 OpAMD64CVTSS2SD 566 OpAMD64PXOR 567 OpAMD64LEAQ 568 OpAMD64LEAQ1 569 OpAMD64LEAQ2 570 OpAMD64LEAQ4 571 OpAMD64LEAQ8 572 OpAMD64LEAL 573 OpAMD64MOVBload 574 OpAMD64MOVBQSXload 575 OpAMD64MOVWload 576 OpAMD64MOVWQSXload 577 OpAMD64MOVLload 578 OpAMD64MOVLQSXload 579 OpAMD64MOVQload 580 OpAMD64MOVBstore 581 OpAMD64MOVWstore 582 OpAMD64MOVLstore 583 OpAMD64MOVQstore 584 OpAMD64MOVOload 585 OpAMD64MOVOstore 586 OpAMD64MOVBloadidx1 587 OpAMD64MOVWloadidx1 588 OpAMD64MOVWloadidx2 589 OpAMD64MOVLloadidx1 590 OpAMD64MOVLloadidx4 591 OpAMD64MOVQloadidx1 592 OpAMD64MOVQloadidx8 593 OpAMD64MOVBstoreidx1 594 OpAMD64MOVWstoreidx1 595 OpAMD64MOVWstoreidx2 596 OpAMD64MOVLstoreidx1 597 OpAMD64MOVLstoreidx4 598 OpAMD64MOVQstoreidx1 599 OpAMD64MOVQstoreidx8 600 OpAMD64MOVBstoreconst 601 OpAMD64MOVWstoreconst 602 OpAMD64MOVLstoreconst 603 OpAMD64MOVQstoreconst 604 OpAMD64MOVBstoreconstidx1 605 OpAMD64MOVWstoreconstidx1 606 OpAMD64MOVWstoreconstidx2 607 OpAMD64MOVLstoreconstidx1 608 OpAMD64MOVLstoreconstidx4 609 OpAMD64MOVQstoreconstidx1 610 OpAMD64MOVQstoreconstidx8 611 OpAMD64DUFFZERO 612 OpAMD64MOVOconst 613 OpAMD64REPSTOSQ 614 OpAMD64CALLstatic 615 OpAMD64CALLclosure 616 OpAMD64CALLdefer 617 OpAMD64CALLgo 618 OpAMD64CALLinter 619 OpAMD64DUFFCOPY 620 OpAMD64REPMOVSQ 621 OpAMD64InvertFlags 622 OpAMD64LoweredGetG 623 OpAMD64LoweredGetClosurePtr 624 OpAMD64LoweredNilCheck 625 OpAMD64MOVQconvert 626 OpAMD64MOVLconvert 627 OpAMD64FlagEQ 628 OpAMD64FlagLT_ULT 629 OpAMD64FlagLT_UGT 630 OpAMD64FlagGT_UGT 631 OpAMD64FlagGT_ULT 632 OpAMD64MOVLatomicload 633 OpAMD64MOVQatomicload 634 OpAMD64XCHGL 635 OpAMD64XCHGQ 636 OpAMD64XADDLlock 637 OpAMD64XADDQlock 638 OpAMD64AddTupleFirst32 639 OpAMD64AddTupleFirst64 640 OpAMD64CMPXCHGLlock 641 OpAMD64CMPXCHGQlock 642 OpAMD64ANDBlock 643 OpAMD64ORBlock 644 645 OpARMADD 646 OpARMADDconst 647 OpARMSUB 648 OpARMSUBconst 649 OpARMRSB 650 OpARMRSBconst 651 OpARMMUL 652 OpARMHMUL 653 OpARMHMULU 654 OpARMUDIVrtcall 655 OpARMADDS 656 OpARMADDSconst 657 OpARMADC 658 OpARMADCconst 659 OpARMSUBS 660 OpARMSUBSconst 661 OpARMRSBSconst 662 OpARMSBC 663 OpARMSBCconst 664 OpARMRSCconst 665 OpARMMULLU 666 OpARMMULA 667 OpARMADDF 668 OpARMADDD 669 OpARMSUBF 670 OpARMSUBD 671 OpARMMULF 672 OpARMMULD 673 OpARMDIVF 674 OpARMDIVD 675 OpARMAND 676 OpARMANDconst 677 OpARMOR 678 OpARMORconst 679 OpARMXOR 680 OpARMXORconst 681 OpARMBIC 682 OpARMBICconst 683 OpARMMVN 684 OpARMNEGF 685 OpARMNEGD 686 OpARMSQRTD 687 OpARMCLZ 688 OpARMSLL 689 OpARMSLLconst 690 OpARMSRL 691 OpARMSRLconst 692 OpARMSRA 693 OpARMSRAconst 694 OpARMSRRconst 695 OpARMADDshiftLL 696 OpARMADDshiftRL 697 OpARMADDshiftRA 698 OpARMSUBshiftLL 699 OpARMSUBshiftRL 700 OpARMSUBshiftRA 701 OpARMRSBshiftLL 702 OpARMRSBshiftRL 703 OpARMRSBshiftRA 704 OpARMANDshiftLL 705 OpARMANDshiftRL 706 OpARMANDshiftRA 707 OpARMORshiftLL 708 OpARMORshiftRL 709 OpARMORshiftRA 710 OpARMXORshiftLL 711 OpARMXORshiftRL 712 OpARMXORshiftRA 713 OpARMXORshiftRR 714 OpARMBICshiftLL 715 OpARMBICshiftRL 716 OpARMBICshiftRA 717 OpARMMVNshiftLL 718 OpARMMVNshiftRL 719 OpARMMVNshiftRA 720 OpARMADCshiftLL 721 OpARMADCshiftRL 722 OpARMADCshiftRA 723 OpARMSBCshiftLL 724 OpARMSBCshiftRL 725 OpARMSBCshiftRA 726 OpARMRSCshiftLL 727 OpARMRSCshiftRL 728 OpARMRSCshiftRA 729 OpARMADDSshiftLL 730 OpARMADDSshiftRL 731 OpARMADDSshiftRA 732 OpARMSUBSshiftLL 733 OpARMSUBSshiftRL 734 OpARMSUBSshiftRA 735 OpARMRSBSshiftLL 736 OpARMRSBSshiftRL 737 OpARMRSBSshiftRA 738 OpARMADDshiftLLreg 739 OpARMADDshiftRLreg 740 OpARMADDshiftRAreg 741 OpARMSUBshiftLLreg 742 OpARMSUBshiftRLreg 743 OpARMSUBshiftRAreg 744 OpARMRSBshiftLLreg 745 OpARMRSBshiftRLreg 746 OpARMRSBshiftRAreg 747 OpARMANDshiftLLreg 748 OpARMANDshiftRLreg 749 OpARMANDshiftRAreg 750 OpARMORshiftLLreg 751 OpARMORshiftRLreg 752 OpARMORshiftRAreg 753 OpARMXORshiftLLreg 754 OpARMXORshiftRLreg 755 OpARMXORshiftRAreg 756 OpARMBICshiftLLreg 757 OpARMBICshiftRLreg 758 OpARMBICshiftRAreg 759 OpARMMVNshiftLLreg 760 OpARMMVNshiftRLreg 761 OpARMMVNshiftRAreg 762 OpARMADCshiftLLreg 763 OpARMADCshiftRLreg 764 OpARMADCshiftRAreg 765 OpARMSBCshiftLLreg 766 OpARMSBCshiftRLreg 767 OpARMSBCshiftRAreg 768 OpARMRSCshiftLLreg 769 OpARMRSCshiftRLreg 770 OpARMRSCshiftRAreg 771 OpARMADDSshiftLLreg 772 OpARMADDSshiftRLreg 773 OpARMADDSshiftRAreg 774 OpARMSUBSshiftLLreg 775 OpARMSUBSshiftRLreg 776 OpARMSUBSshiftRAreg 777 OpARMRSBSshiftLLreg 778 OpARMRSBSshiftRLreg 779 OpARMRSBSshiftRAreg 780 OpARMCMP 781 OpARMCMPconst 782 OpARMCMN 783 OpARMCMNconst 784 OpARMTST 785 OpARMTSTconst 786 OpARMTEQ 787 OpARMTEQconst 788 OpARMCMPF 789 OpARMCMPD 790 OpARMCMPshiftLL 791 OpARMCMPshiftRL 792 OpARMCMPshiftRA 793 OpARMCMPshiftLLreg 794 OpARMCMPshiftRLreg 795 OpARMCMPshiftRAreg 796 OpARMCMPF0 797 OpARMCMPD0 798 OpARMMOVWconst 799 OpARMMOVFconst 800 OpARMMOVDconst 801 OpARMMOVWaddr 802 OpARMMOVBload 803 OpARMMOVBUload 804 OpARMMOVHload 805 OpARMMOVHUload 806 OpARMMOVWload 807 OpARMMOVFload 808 OpARMMOVDload 809 OpARMMOVBstore 810 OpARMMOVHstore 811 OpARMMOVWstore 812 OpARMMOVFstore 813 OpARMMOVDstore 814 OpARMMOVWloadidx 815 OpARMMOVWloadshiftLL 816 OpARMMOVWloadshiftRL 817 OpARMMOVWloadshiftRA 818 OpARMMOVWstoreidx 819 OpARMMOVWstoreshiftLL 820 OpARMMOVWstoreshiftRL 821 OpARMMOVWstoreshiftRA 822 OpARMMOVBreg 823 OpARMMOVBUreg 824 OpARMMOVHreg 825 OpARMMOVHUreg 826 OpARMMOVWreg 827 OpARMMOVWnop 828 OpARMMOVWF 829 OpARMMOVWD 830 OpARMMOVWUF 831 OpARMMOVWUD 832 OpARMMOVFW 833 OpARMMOVDW 834 OpARMMOVFWU 835 OpARMMOVDWU 836 OpARMMOVFD 837 OpARMMOVDF 838 OpARMCMOVWHSconst 839 OpARMCMOVWLSconst 840 OpARMSRAcond 841 OpARMCALLstatic 842 OpARMCALLclosure 843 OpARMCALLdefer 844 OpARMCALLgo 845 OpARMCALLinter 846 OpARMLoweredNilCheck 847 OpARMEqual 848 OpARMNotEqual 849 OpARMLessThan 850 OpARMLessEqual 851 OpARMGreaterThan 852 OpARMGreaterEqual 853 OpARMLessThanU 854 OpARMLessEqualU 855 OpARMGreaterThanU 856 OpARMGreaterEqualU 857 OpARMDUFFZERO 858 OpARMDUFFCOPY 859 OpARMLoweredZero 860 OpARMLoweredMove 861 OpARMLoweredGetClosurePtr 862 OpARMMOVWconvert 863 OpARMFlagEQ 864 OpARMFlagLT_ULT 865 OpARMFlagLT_UGT 866 OpARMFlagGT_UGT 867 OpARMFlagGT_ULT 868 OpARMInvertFlags 869 870 OpARM64ADD 871 OpARM64ADDconst 872 OpARM64SUB 873 OpARM64SUBconst 874 OpARM64MUL 875 OpARM64MULW 876 OpARM64MULH 877 OpARM64UMULH 878 OpARM64MULL 879 OpARM64UMULL 880 OpARM64DIV 881 OpARM64UDIV 882 OpARM64DIVW 883 OpARM64UDIVW 884 OpARM64MOD 885 OpARM64UMOD 886 OpARM64MODW 887 OpARM64UMODW 888 OpARM64FADDS 889 OpARM64FADDD 890 OpARM64FSUBS 891 OpARM64FSUBD 892 OpARM64FMULS 893 OpARM64FMULD 894 OpARM64FDIVS 895 OpARM64FDIVD 896 OpARM64AND 897 OpARM64ANDconst 898 OpARM64OR 899 OpARM64ORconst 900 OpARM64XOR 901 OpARM64XORconst 902 OpARM64BIC 903 OpARM64BICconst 904 OpARM64MVN 905 OpARM64NEG 906 OpARM64FNEGS 907 OpARM64FNEGD 908 OpARM64FSQRTD 909 OpARM64REV 910 OpARM64REVW 911 OpARM64REV16W 912 OpARM64RBIT 913 OpARM64RBITW 914 OpARM64CLZ 915 OpARM64CLZW 916 OpARM64SLL 917 OpARM64SLLconst 918 OpARM64SRL 919 OpARM64SRLconst 920 OpARM64SRA 921 OpARM64SRAconst 922 OpARM64RORconst 923 OpARM64RORWconst 924 OpARM64CMP 925 OpARM64CMPconst 926 OpARM64CMPW 927 OpARM64CMPWconst 928 OpARM64CMN 929 OpARM64CMNconst 930 OpARM64CMNW 931 OpARM64CMNWconst 932 OpARM64FCMPS 933 OpARM64FCMPD 934 OpARM64ADDshiftLL 935 OpARM64ADDshiftRL 936 OpARM64ADDshiftRA 937 OpARM64SUBshiftLL 938 OpARM64SUBshiftRL 939 OpARM64SUBshiftRA 940 OpARM64ANDshiftLL 941 OpARM64ANDshiftRL 942 OpARM64ANDshiftRA 943 OpARM64ORshiftLL 944 OpARM64ORshiftRL 945 OpARM64ORshiftRA 946 OpARM64XORshiftLL 947 OpARM64XORshiftRL 948 OpARM64XORshiftRA 949 OpARM64BICshiftLL 950 OpARM64BICshiftRL 951 OpARM64BICshiftRA 952 OpARM64CMPshiftLL 953 OpARM64CMPshiftRL 954 OpARM64CMPshiftRA 955 OpARM64MOVDconst 956 OpARM64FMOVSconst 957 OpARM64FMOVDconst 958 OpARM64MOVDaddr 959 OpARM64MOVBload 960 OpARM64MOVBUload 961 OpARM64MOVHload 962 OpARM64MOVHUload 963 OpARM64MOVWload 964 OpARM64MOVWUload 965 OpARM64MOVDload 966 OpARM64FMOVSload 967 OpARM64FMOVDload 968 OpARM64MOVBstore 969 OpARM64MOVHstore 970 OpARM64MOVWstore 971 OpARM64MOVDstore 972 OpARM64FMOVSstore 973 OpARM64FMOVDstore 974 OpARM64MOVBstorezero 975 OpARM64MOVHstorezero 976 OpARM64MOVWstorezero 977 OpARM64MOVDstorezero 978 OpARM64MOVBreg 979 OpARM64MOVBUreg 980 OpARM64MOVHreg 981 OpARM64MOVHUreg 982 OpARM64MOVWreg 983 OpARM64MOVWUreg 984 OpARM64MOVDreg 985 OpARM64MOVDnop 986 OpARM64SCVTFWS 987 OpARM64SCVTFWD 988 OpARM64UCVTFWS 989 OpARM64UCVTFWD 990 OpARM64SCVTFS 991 OpARM64SCVTFD 992 OpARM64UCVTFS 993 OpARM64UCVTFD 994 OpARM64FCVTZSSW 995 OpARM64FCVTZSDW 996 OpARM64FCVTZUSW 997 OpARM64FCVTZUDW 998 OpARM64FCVTZSS 999 OpARM64FCVTZSD 1000 OpARM64FCVTZUS 1001 OpARM64FCVTZUD 1002 OpARM64FCVTSD 1003 OpARM64FCVTDS 1004 OpARM64CSELULT 1005 OpARM64CSELULT0 1006 OpARM64CALLstatic 1007 OpARM64CALLclosure 1008 OpARM64CALLdefer 1009 OpARM64CALLgo 1010 OpARM64CALLinter 1011 OpARM64LoweredNilCheck 1012 OpARM64Equal 1013 OpARM64NotEqual 1014 OpARM64LessThan 1015 OpARM64LessEqual 1016 OpARM64GreaterThan 1017 OpARM64GreaterEqual 1018 OpARM64LessThanU 1019 OpARM64LessEqualU 1020 OpARM64GreaterThanU 1021 OpARM64GreaterEqualU 1022 OpARM64DUFFZERO 1023 OpARM64LoweredZero 1024 OpARM64DUFFCOPY 1025 OpARM64LoweredMove 1026 OpARM64LoweredGetClosurePtr 1027 OpARM64MOVDconvert 1028 OpARM64FlagEQ 1029 OpARM64FlagLT_ULT 1030 OpARM64FlagLT_UGT 1031 OpARM64FlagGT_UGT 1032 OpARM64FlagGT_ULT 1033 OpARM64InvertFlags 1034 OpARM64LDAR 1035 OpARM64LDARW 1036 OpARM64STLR 1037 OpARM64STLRW 1038 OpARM64LoweredAtomicExchange64 1039 OpARM64LoweredAtomicExchange32 1040 OpARM64LoweredAtomicAdd64 1041 OpARM64LoweredAtomicAdd32 1042 OpARM64LoweredAtomicCas64 1043 OpARM64LoweredAtomicCas32 1044 OpARM64LoweredAtomicAnd8 1045 OpARM64LoweredAtomicOr8 1046 1047 OpMIPSADD 1048 OpMIPSADDconst 1049 OpMIPSSUB 1050 OpMIPSSUBconst 1051 OpMIPSMUL 1052 OpMIPSMULT 1053 OpMIPSMULTU 1054 OpMIPSDIV 1055 OpMIPSDIVU 1056 OpMIPSADDF 1057 OpMIPSADDD 1058 OpMIPSSUBF 1059 OpMIPSSUBD 1060 OpMIPSMULF 1061 OpMIPSMULD 1062 OpMIPSDIVF 1063 OpMIPSDIVD 1064 OpMIPSAND 1065 OpMIPSANDconst 1066 OpMIPSOR 1067 OpMIPSORconst 1068 OpMIPSXOR 1069 OpMIPSXORconst 1070 OpMIPSNOR 1071 OpMIPSNORconst 1072 OpMIPSNEG 1073 OpMIPSNEGF 1074 OpMIPSNEGD 1075 OpMIPSSQRTD 1076 OpMIPSSLL 1077 OpMIPSSLLconst 1078 OpMIPSSRL 1079 OpMIPSSRLconst 1080 OpMIPSSRA 1081 OpMIPSSRAconst 1082 OpMIPSCLZ 1083 OpMIPSSGT 1084 OpMIPSSGTconst 1085 OpMIPSSGTzero 1086 OpMIPSSGTU 1087 OpMIPSSGTUconst 1088 OpMIPSSGTUzero 1089 OpMIPSCMPEQF 1090 OpMIPSCMPEQD 1091 OpMIPSCMPGEF 1092 OpMIPSCMPGED 1093 OpMIPSCMPGTF 1094 OpMIPSCMPGTD 1095 OpMIPSMOVWconst 1096 OpMIPSMOVFconst 1097 OpMIPSMOVDconst 1098 OpMIPSMOVWaddr 1099 OpMIPSMOVBload 1100 OpMIPSMOVBUload 1101 OpMIPSMOVHload 1102 OpMIPSMOVHUload 1103 OpMIPSMOVWload 1104 OpMIPSMOVFload 1105 OpMIPSMOVDload 1106 OpMIPSMOVBstore 1107 OpMIPSMOVHstore 1108 OpMIPSMOVWstore 1109 OpMIPSMOVFstore 1110 OpMIPSMOVDstore 1111 OpMIPSMOVBstorezero 1112 OpMIPSMOVHstorezero 1113 OpMIPSMOVWstorezero 1114 OpMIPSMOVBreg 1115 OpMIPSMOVBUreg 1116 OpMIPSMOVHreg 1117 OpMIPSMOVHUreg 1118 OpMIPSMOVWreg 1119 OpMIPSMOVWnop 1120 OpMIPSCMOVZ 1121 OpMIPSCMOVZzero 1122 OpMIPSMOVWF 1123 OpMIPSMOVWD 1124 OpMIPSTRUNCFW 1125 OpMIPSTRUNCDW 1126 OpMIPSMOVFD 1127 OpMIPSMOVDF 1128 OpMIPSCALLstatic 1129 OpMIPSCALLclosure 1130 OpMIPSCALLdefer 1131 OpMIPSCALLgo 1132 OpMIPSCALLinter 1133 OpMIPSLoweredAtomicLoad 1134 OpMIPSLoweredAtomicStore 1135 OpMIPSLoweredAtomicStorezero 1136 OpMIPSLoweredAtomicExchange 1137 OpMIPSLoweredAtomicAdd 1138 OpMIPSLoweredAtomicAddconst 1139 OpMIPSLoweredAtomicCas 1140 OpMIPSLoweredAtomicAnd 1141 OpMIPSLoweredAtomicOr 1142 OpMIPSLoweredZero 1143 OpMIPSLoweredMove 1144 OpMIPSLoweredNilCheck 1145 OpMIPSFPFlagTrue 1146 OpMIPSFPFlagFalse 1147 OpMIPSLoweredGetClosurePtr 1148 OpMIPSMOVWconvert 1149 1150 OpMIPS64ADDV 1151 OpMIPS64ADDVconst 1152 OpMIPS64SUBV 1153 OpMIPS64SUBVconst 1154 OpMIPS64MULV 1155 OpMIPS64MULVU 1156 OpMIPS64DIVV 1157 OpMIPS64DIVVU 1158 OpMIPS64ADDF 1159 OpMIPS64ADDD 1160 OpMIPS64SUBF 1161 OpMIPS64SUBD 1162 OpMIPS64MULF 1163 OpMIPS64MULD 1164 OpMIPS64DIVF 1165 OpMIPS64DIVD 1166 OpMIPS64AND 1167 OpMIPS64ANDconst 1168 OpMIPS64OR 1169 OpMIPS64ORconst 1170 OpMIPS64XOR 1171 OpMIPS64XORconst 1172 OpMIPS64NOR 1173 OpMIPS64NORconst 1174 OpMIPS64NEGV 1175 OpMIPS64NEGF 1176 OpMIPS64NEGD 1177 OpMIPS64SLLV 1178 OpMIPS64SLLVconst 1179 OpMIPS64SRLV 1180 OpMIPS64SRLVconst 1181 OpMIPS64SRAV 1182 OpMIPS64SRAVconst 1183 OpMIPS64SGT 1184 OpMIPS64SGTconst 1185 OpMIPS64SGTU 1186 OpMIPS64SGTUconst 1187 OpMIPS64CMPEQF 1188 OpMIPS64CMPEQD 1189 OpMIPS64CMPGEF 1190 OpMIPS64CMPGED 1191 OpMIPS64CMPGTF 1192 OpMIPS64CMPGTD 1193 OpMIPS64MOVVconst 1194 OpMIPS64MOVFconst 1195 OpMIPS64MOVDconst 1196 OpMIPS64MOVVaddr 1197 OpMIPS64MOVBload 1198 OpMIPS64MOVBUload 1199 OpMIPS64MOVHload 1200 OpMIPS64MOVHUload 1201 OpMIPS64MOVWload 1202 OpMIPS64MOVWUload 1203 OpMIPS64MOVVload 1204 OpMIPS64MOVFload 1205 OpMIPS64MOVDload 1206 OpMIPS64MOVBstore 1207 OpMIPS64MOVHstore 1208 OpMIPS64MOVWstore 1209 OpMIPS64MOVVstore 1210 OpMIPS64MOVFstore 1211 OpMIPS64MOVDstore 1212 OpMIPS64MOVBstorezero 1213 OpMIPS64MOVHstorezero 1214 OpMIPS64MOVWstorezero 1215 OpMIPS64MOVVstorezero 1216 OpMIPS64MOVBreg 1217 OpMIPS64MOVBUreg 1218 OpMIPS64MOVHreg 1219 OpMIPS64MOVHUreg 1220 OpMIPS64MOVWreg 1221 OpMIPS64MOVWUreg 1222 OpMIPS64MOVVreg 1223 OpMIPS64MOVVnop 1224 OpMIPS64MOVWF 1225 OpMIPS64MOVWD 1226 OpMIPS64MOVVF 1227 OpMIPS64MOVVD 1228 OpMIPS64TRUNCFW 1229 OpMIPS64TRUNCDW 1230 OpMIPS64TRUNCFV 1231 OpMIPS64TRUNCDV 1232 OpMIPS64MOVFD 1233 OpMIPS64MOVDF 1234 OpMIPS64CALLstatic 1235 OpMIPS64CALLclosure 1236 OpMIPS64CALLdefer 1237 OpMIPS64CALLgo 1238 OpMIPS64CALLinter 1239 OpMIPS64DUFFZERO 1240 OpMIPS64LoweredZero 1241 OpMIPS64LoweredMove 1242 OpMIPS64LoweredNilCheck 1243 OpMIPS64FPFlagTrue 1244 OpMIPS64FPFlagFalse 1245 OpMIPS64LoweredGetClosurePtr 1246 OpMIPS64MOVVconvert 1247 1248 OpPPC64ADD 1249 OpPPC64ADDconst 1250 OpPPC64FADD 1251 OpPPC64FADDS 1252 OpPPC64SUB 1253 OpPPC64FSUB 1254 OpPPC64FSUBS 1255 OpPPC64MULLD 1256 OpPPC64MULLW 1257 OpPPC64MULHD 1258 OpPPC64MULHW 1259 OpPPC64MULHDU 1260 OpPPC64MULHWU 1261 OpPPC64FMUL 1262 OpPPC64FMULS 1263 OpPPC64SRAD 1264 OpPPC64SRAW 1265 OpPPC64SRD 1266 OpPPC64SRW 1267 OpPPC64SLD 1268 OpPPC64SLW 1269 OpPPC64ADDconstForCarry 1270 OpPPC64MaskIfNotCarry 1271 OpPPC64SRADconst 1272 OpPPC64SRAWconst 1273 OpPPC64SRDconst 1274 OpPPC64SRWconst 1275 OpPPC64SLDconst 1276 OpPPC64SLWconst 1277 OpPPC64FDIV 1278 OpPPC64FDIVS 1279 OpPPC64DIVD 1280 OpPPC64DIVW 1281 OpPPC64DIVDU 1282 OpPPC64DIVWU 1283 OpPPC64FCTIDZ 1284 OpPPC64FCTIWZ 1285 OpPPC64FCFID 1286 OpPPC64FRSP 1287 OpPPC64Xf2i64 1288 OpPPC64Xi2f64 1289 OpPPC64AND 1290 OpPPC64ANDN 1291 OpPPC64OR 1292 OpPPC64ORN 1293 OpPPC64XOR 1294 OpPPC64EQV 1295 OpPPC64NEG 1296 OpPPC64FNEG 1297 OpPPC64FSQRT 1298 OpPPC64FSQRTS 1299 OpPPC64ORconst 1300 OpPPC64XORconst 1301 OpPPC64ANDconst 1302 OpPPC64ANDCCconst 1303 OpPPC64MOVBreg 1304 OpPPC64MOVBZreg 1305 OpPPC64MOVHreg 1306 OpPPC64MOVHZreg 1307 OpPPC64MOVWreg 1308 OpPPC64MOVWZreg 1309 OpPPC64MOVBZload 1310 OpPPC64MOVHload 1311 OpPPC64MOVHZload 1312 OpPPC64MOVWload 1313 OpPPC64MOVWZload 1314 OpPPC64MOVDload 1315 OpPPC64FMOVDload 1316 OpPPC64FMOVSload 1317 OpPPC64MOVBstore 1318 OpPPC64MOVHstore 1319 OpPPC64MOVWstore 1320 OpPPC64MOVDstore 1321 OpPPC64FMOVDstore 1322 OpPPC64FMOVSstore 1323 OpPPC64MOVBstorezero 1324 OpPPC64MOVHstorezero 1325 OpPPC64MOVWstorezero 1326 OpPPC64MOVDstorezero 1327 OpPPC64MOVDaddr 1328 OpPPC64MOVDconst 1329 OpPPC64FMOVDconst 1330 OpPPC64FMOVSconst 1331 OpPPC64FCMPU 1332 OpPPC64CMP 1333 OpPPC64CMPU 1334 OpPPC64CMPW 1335 OpPPC64CMPWU 1336 OpPPC64CMPconst 1337 OpPPC64CMPUconst 1338 OpPPC64CMPWconst 1339 OpPPC64CMPWUconst 1340 OpPPC64Equal 1341 OpPPC64NotEqual 1342 OpPPC64LessThan 1343 OpPPC64FLessThan 1344 OpPPC64LessEqual 1345 OpPPC64FLessEqual 1346 OpPPC64GreaterThan 1347 OpPPC64FGreaterThan 1348 OpPPC64GreaterEqual 1349 OpPPC64FGreaterEqual 1350 OpPPC64LoweredGetClosurePtr 1351 OpPPC64LoweredNilCheck 1352 OpPPC64MOVDconvert 1353 OpPPC64CALLstatic 1354 OpPPC64CALLclosure 1355 OpPPC64CALLdefer 1356 OpPPC64CALLgo 1357 OpPPC64CALLinter 1358 OpPPC64LoweredZero 1359 OpPPC64LoweredMove 1360 OpPPC64InvertFlags 1361 OpPPC64FlagEQ 1362 OpPPC64FlagLT 1363 OpPPC64FlagGT 1364 1365 OpS390XFADDS 1366 OpS390XFADD 1367 OpS390XFSUBS 1368 OpS390XFSUB 1369 OpS390XFMULS 1370 OpS390XFMUL 1371 OpS390XFDIVS 1372 OpS390XFDIV 1373 OpS390XFNEGS 1374 OpS390XFNEG 1375 OpS390XFMOVSload 1376 OpS390XFMOVDload 1377 OpS390XFMOVSconst 1378 OpS390XFMOVDconst 1379 OpS390XFMOVSloadidx 1380 OpS390XFMOVDloadidx 1381 OpS390XFMOVSstore 1382 OpS390XFMOVDstore 1383 OpS390XFMOVSstoreidx 1384 OpS390XFMOVDstoreidx 1385 OpS390XADD 1386 OpS390XADDW 1387 OpS390XADDconst 1388 OpS390XADDWconst 1389 OpS390XADDload 1390 OpS390XADDWload 1391 OpS390XSUB 1392 OpS390XSUBW 1393 OpS390XSUBconst 1394 OpS390XSUBWconst 1395 OpS390XSUBload 1396 OpS390XSUBWload 1397 OpS390XMULLD 1398 OpS390XMULLW 1399 OpS390XMULLDconst 1400 OpS390XMULLWconst 1401 OpS390XMULLDload 1402 OpS390XMULLWload 1403 OpS390XMULHD 1404 OpS390XMULHDU 1405 OpS390XDIVD 1406 OpS390XDIVW 1407 OpS390XDIVDU 1408 OpS390XDIVWU 1409 OpS390XMODD 1410 OpS390XMODW 1411 OpS390XMODDU 1412 OpS390XMODWU 1413 OpS390XAND 1414 OpS390XANDW 1415 OpS390XANDconst 1416 OpS390XANDWconst 1417 OpS390XANDload 1418 OpS390XANDWload 1419 OpS390XOR 1420 OpS390XORW 1421 OpS390XORconst 1422 OpS390XORWconst 1423 OpS390XORload 1424 OpS390XORWload 1425 OpS390XXOR 1426 OpS390XXORW 1427 OpS390XXORconst 1428 OpS390XXORWconst 1429 OpS390XXORload 1430 OpS390XXORWload 1431 OpS390XCMP 1432 OpS390XCMPW 1433 OpS390XCMPU 1434 OpS390XCMPWU 1435 OpS390XCMPconst 1436 OpS390XCMPWconst 1437 OpS390XCMPUconst 1438 OpS390XCMPWUconst 1439 OpS390XFCMPS 1440 OpS390XFCMP 1441 OpS390XSLD 1442 OpS390XSLW 1443 OpS390XSLDconst 1444 OpS390XSLWconst 1445 OpS390XSRD 1446 OpS390XSRW 1447 OpS390XSRDconst 1448 OpS390XSRWconst 1449 OpS390XSRAD 1450 OpS390XSRAW 1451 OpS390XSRADconst 1452 OpS390XSRAWconst 1453 OpS390XRLLGconst 1454 OpS390XRLLconst 1455 OpS390XNEG 1456 OpS390XNEGW 1457 OpS390XNOT 1458 OpS390XNOTW 1459 OpS390XFSQRT 1460 OpS390XSUBEcarrymask 1461 OpS390XSUBEWcarrymask 1462 OpS390XMOVDEQ 1463 OpS390XMOVDNE 1464 OpS390XMOVDLT 1465 OpS390XMOVDLE 1466 OpS390XMOVDGT 1467 OpS390XMOVDGE 1468 OpS390XMOVDGTnoinv 1469 OpS390XMOVDGEnoinv 1470 OpS390XMOVBreg 1471 OpS390XMOVBZreg 1472 OpS390XMOVHreg 1473 OpS390XMOVHZreg 1474 OpS390XMOVWreg 1475 OpS390XMOVWZreg 1476 OpS390XMOVDreg 1477 OpS390XMOVDnop 1478 OpS390XMOVDconst 1479 OpS390XCFDBRA 1480 OpS390XCGDBRA 1481 OpS390XCFEBRA 1482 OpS390XCGEBRA 1483 OpS390XCEFBRA 1484 OpS390XCDFBRA 1485 OpS390XCEGBRA 1486 OpS390XCDGBRA 1487 OpS390XLEDBR 1488 OpS390XLDEBR 1489 OpS390XMOVDaddr 1490 OpS390XMOVDaddridx 1491 OpS390XMOVBZload 1492 OpS390XMOVBload 1493 OpS390XMOVHZload 1494 OpS390XMOVHload 1495 OpS390XMOVWZload 1496 OpS390XMOVWload 1497 OpS390XMOVDload 1498 OpS390XMOVWBR 1499 OpS390XMOVDBR 1500 OpS390XMOVHBRload 1501 OpS390XMOVWBRload 1502 OpS390XMOVDBRload 1503 OpS390XMOVBstore 1504 OpS390XMOVHstore 1505 OpS390XMOVWstore 1506 OpS390XMOVDstore 1507 OpS390XMOVHBRstore 1508 OpS390XMOVWBRstore 1509 OpS390XMOVDBRstore 1510 OpS390XMVC 1511 OpS390XMOVBZloadidx 1512 OpS390XMOVHZloadidx 1513 OpS390XMOVWZloadidx 1514 OpS390XMOVDloadidx 1515 OpS390XMOVHBRloadidx 1516 OpS390XMOVWBRloadidx 1517 OpS390XMOVDBRloadidx 1518 OpS390XMOVBstoreidx 1519 OpS390XMOVHstoreidx 1520 OpS390XMOVWstoreidx 1521 OpS390XMOVDstoreidx 1522 OpS390XMOVHBRstoreidx 1523 OpS390XMOVWBRstoreidx 1524 OpS390XMOVDBRstoreidx 1525 OpS390XMOVBstoreconst 1526 OpS390XMOVHstoreconst 1527 OpS390XMOVWstoreconst 1528 OpS390XMOVDstoreconst 1529 OpS390XCLEAR 1530 OpS390XCALLstatic 1531 OpS390XCALLclosure 1532 OpS390XCALLdefer 1533 OpS390XCALLgo 1534 OpS390XCALLinter 1535 OpS390XInvertFlags 1536 OpS390XLoweredGetG 1537 OpS390XLoweredGetClosurePtr 1538 OpS390XLoweredNilCheck 1539 OpS390XMOVDconvert 1540 OpS390XFlagEQ 1541 OpS390XFlagLT 1542 OpS390XFlagGT 1543 OpS390XMOVWZatomicload 1544 OpS390XMOVDatomicload 1545 OpS390XMOVWatomicstore 1546 OpS390XMOVDatomicstore 1547 OpS390XLAA 1548 OpS390XLAAG 1549 OpS390XAddTupleFirst32 1550 OpS390XAddTupleFirst64 1551 OpS390XLoweredAtomicCas32 1552 OpS390XLoweredAtomicCas64 1553 OpS390XLoweredAtomicExchange32 1554 OpS390XLoweredAtomicExchange64 1555 OpS390XFLOGR 1556 OpS390XSTMG2 1557 OpS390XSTMG3 1558 OpS390XSTMG4 1559 OpS390XSTM2 1560 OpS390XSTM3 1561 OpS390XSTM4 1562 OpS390XLoweredMove 1563 OpS390XLoweredZero 1564 1565 OpAdd8 1566 OpAdd16 1567 OpAdd32 1568 OpAdd64 1569 OpAddPtr 1570 OpAdd32F 1571 OpAdd64F 1572 OpSub8 1573 OpSub16 1574 OpSub32 1575 OpSub64 1576 OpSubPtr 1577 OpSub32F 1578 OpSub64F 1579 OpMul8 1580 OpMul16 1581 OpMul32 1582 OpMul64 1583 OpMul32F 1584 OpMul64F 1585 OpDiv32F 1586 OpDiv64F 1587 OpHmul8 1588 OpHmul8u 1589 OpHmul16 1590 OpHmul16u 1591 OpHmul32 1592 OpHmul32u 1593 OpHmul64 1594 OpHmul64u 1595 OpMul32uhilo 1596 OpMul64uhilo 1597 OpAvg64u 1598 OpDiv8 1599 OpDiv8u 1600 OpDiv16 1601 OpDiv16u 1602 OpDiv32 1603 OpDiv32u 1604 OpDiv64 1605 OpDiv64u 1606 OpDiv128u 1607 OpMod8 1608 OpMod8u 1609 OpMod16 1610 OpMod16u 1611 OpMod32 1612 OpMod32u 1613 OpMod64 1614 OpMod64u 1615 OpAnd8 1616 OpAnd16 1617 OpAnd32 1618 OpAnd64 1619 OpOr8 1620 OpOr16 1621 OpOr32 1622 OpOr64 1623 OpXor8 1624 OpXor16 1625 OpXor32 1626 OpXor64 1627 OpLsh8x8 1628 OpLsh8x16 1629 OpLsh8x32 1630 OpLsh8x64 1631 OpLsh16x8 1632 OpLsh16x16 1633 OpLsh16x32 1634 OpLsh16x64 1635 OpLsh32x8 1636 OpLsh32x16 1637 OpLsh32x32 1638 OpLsh32x64 1639 OpLsh64x8 1640 OpLsh64x16 1641 OpLsh64x32 1642 OpLsh64x64 1643 OpRsh8x8 1644 OpRsh8x16 1645 OpRsh8x32 1646 OpRsh8x64 1647 OpRsh16x8 1648 OpRsh16x16 1649 OpRsh16x32 1650 OpRsh16x64 1651 OpRsh32x8 1652 OpRsh32x16 1653 OpRsh32x32 1654 OpRsh32x64 1655 OpRsh64x8 1656 OpRsh64x16 1657 OpRsh64x32 1658 OpRsh64x64 1659 OpRsh8Ux8 1660 OpRsh8Ux16 1661 OpRsh8Ux32 1662 OpRsh8Ux64 1663 OpRsh16Ux8 1664 OpRsh16Ux16 1665 OpRsh16Ux32 1666 OpRsh16Ux64 1667 OpRsh32Ux8 1668 OpRsh32Ux16 1669 OpRsh32Ux32 1670 OpRsh32Ux64 1671 OpRsh64Ux8 1672 OpRsh64Ux16 1673 OpRsh64Ux32 1674 OpRsh64Ux64 1675 OpLrot8 1676 OpLrot16 1677 OpLrot32 1678 OpLrot64 1679 OpEq8 1680 OpEq16 1681 OpEq32 1682 OpEq64 1683 OpEqPtr 1684 OpEqInter 1685 OpEqSlice 1686 OpEq32F 1687 OpEq64F 1688 OpNeq8 1689 OpNeq16 1690 OpNeq32 1691 OpNeq64 1692 OpNeqPtr 1693 OpNeqInter 1694 OpNeqSlice 1695 OpNeq32F 1696 OpNeq64F 1697 OpLess8 1698 OpLess8U 1699 OpLess16 1700 OpLess16U 1701 OpLess32 1702 OpLess32U 1703 OpLess64 1704 OpLess64U 1705 OpLess32F 1706 OpLess64F 1707 OpLeq8 1708 OpLeq8U 1709 OpLeq16 1710 OpLeq16U 1711 OpLeq32 1712 OpLeq32U 1713 OpLeq64 1714 OpLeq64U 1715 OpLeq32F 1716 OpLeq64F 1717 OpGreater8 1718 OpGreater8U 1719 OpGreater16 1720 OpGreater16U 1721 OpGreater32 1722 OpGreater32U 1723 OpGreater64 1724 OpGreater64U 1725 OpGreater32F 1726 OpGreater64F 1727 OpGeq8 1728 OpGeq8U 1729 OpGeq16 1730 OpGeq16U 1731 OpGeq32 1732 OpGeq32U 1733 OpGeq64 1734 OpGeq64U 1735 OpGeq32F 1736 OpGeq64F 1737 OpAndB 1738 OpOrB 1739 OpEqB 1740 OpNeqB 1741 OpNot 1742 OpNeg8 1743 OpNeg16 1744 OpNeg32 1745 OpNeg64 1746 OpNeg32F 1747 OpNeg64F 1748 OpCom8 1749 OpCom16 1750 OpCom32 1751 OpCom64 1752 OpCtz32 1753 OpCtz64 1754 OpBswap32 1755 OpBswap64 1756 OpSqrt 1757 OpPhi 1758 OpCopy 1759 OpConvert 1760 OpConstBool 1761 OpConstString 1762 OpConstNil 1763 OpConst8 1764 OpConst16 1765 OpConst32 1766 OpConst64 1767 OpConst32F 1768 OpConst64F 1769 OpConstInterface 1770 OpConstSlice 1771 OpInitMem 1772 OpArg 1773 OpAddr 1774 OpSP 1775 OpSB 1776 OpFunc 1777 OpLoad 1778 OpStore 1779 OpMove 1780 OpZero 1781 OpStoreWB 1782 OpMoveWB 1783 OpMoveWBVolatile 1784 OpZeroWB 1785 OpClosureCall 1786 OpStaticCall 1787 OpDeferCall 1788 OpGoCall 1789 OpInterCall 1790 OpSignExt8to16 1791 OpSignExt8to32 1792 OpSignExt8to64 1793 OpSignExt16to32 1794 OpSignExt16to64 1795 OpSignExt32to64 1796 OpZeroExt8to16 1797 OpZeroExt8to32 1798 OpZeroExt8to64 1799 OpZeroExt16to32 1800 OpZeroExt16to64 1801 OpZeroExt32to64 1802 OpTrunc16to8 1803 OpTrunc32to8 1804 OpTrunc32to16 1805 OpTrunc64to8 1806 OpTrunc64to16 1807 OpTrunc64to32 1808 OpCvt32to32F 1809 OpCvt32to64F 1810 OpCvt64to32F 1811 OpCvt64to64F 1812 OpCvt32Fto32 1813 OpCvt32Fto64 1814 OpCvt64Fto32 1815 OpCvt64Fto64 1816 OpCvt32Fto64F 1817 OpCvt64Fto32F 1818 OpIsNonNil 1819 OpIsInBounds 1820 OpIsSliceInBounds 1821 OpNilCheck 1822 OpGetG 1823 OpGetClosurePtr 1824 OpPtrIndex 1825 OpOffPtr 1826 OpSliceMake 1827 OpSlicePtr 1828 OpSliceLen 1829 OpSliceCap 1830 OpComplexMake 1831 OpComplexReal 1832 OpComplexImag 1833 OpStringMake 1834 OpStringPtr 1835 OpStringLen 1836 OpIMake 1837 OpITab 1838 OpIData 1839 OpStructMake0 1840 OpStructMake1 1841 OpStructMake2 1842 OpStructMake3 1843 OpStructMake4 1844 OpStructSelect 1845 OpArrayMake0 1846 OpArrayMake1 1847 OpArraySelect 1848 OpStoreReg 1849 OpLoadReg 1850 OpFwdRef 1851 OpUnknown 1852 OpVarDef 1853 OpVarKill 1854 OpVarLive 1855 OpKeepAlive 1856 OpInt64Make 1857 OpInt64Hi 1858 OpInt64Lo 1859 OpAdd32carry 1860 OpAdd32withcarry 1861 OpSub32carry 1862 OpSub32withcarry 1863 OpSignmask 1864 OpZeromask 1865 OpSlicemask 1866 OpCvt32Uto32F 1867 OpCvt32Uto64F 1868 OpCvt32Fto32U 1869 OpCvt64Fto32U 1870 OpCvt64Uto32F 1871 OpCvt64Uto64F 1872 OpCvt32Fto64U 1873 OpCvt64Fto64U 1874 OpSelect0 1875 OpSelect1 1876 OpAtomicLoad32 1877 OpAtomicLoad64 1878 OpAtomicLoadPtr 1879 OpAtomicStore32 1880 OpAtomicStore64 1881 OpAtomicStorePtrNoWB 1882 OpAtomicExchange32 1883 OpAtomicExchange64 1884 OpAtomicAdd32 1885 OpAtomicAdd64 1886 OpAtomicCompareAndSwap32 1887 OpAtomicCompareAndSwap64 1888 OpAtomicAnd8 1889 OpAtomicOr8 1890 ) 1891 1892 var opcodeTable = [...]opInfo{ 1893 {name: "OpInvalid"}, 1894 1895 { 1896 name: "ADDSS", 1897 argLen: 2, 1898 commutative: true, 1899 resultInArg0: true, 1900 usesScratch: true, 1901 asm: x86.AADDSS, 1902 reg: regInfo{ 1903 inputs: []inputInfo{ 1904 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1905 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1906 }, 1907 outputs: []outputInfo{ 1908 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1909 }, 1910 }, 1911 }, 1912 { 1913 name: "ADDSD", 1914 argLen: 2, 1915 commutative: true, 1916 resultInArg0: true, 1917 asm: x86.AADDSD, 1918 reg: regInfo{ 1919 inputs: []inputInfo{ 1920 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1921 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1922 }, 1923 outputs: []outputInfo{ 1924 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1925 }, 1926 }, 1927 }, 1928 { 1929 name: "SUBSS", 1930 argLen: 2, 1931 resultInArg0: true, 1932 usesScratch: true, 1933 asm: x86.ASUBSS, 1934 reg: regInfo{ 1935 inputs: []inputInfo{ 1936 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1937 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1938 }, 1939 outputs: []outputInfo{ 1940 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1941 }, 1942 }, 1943 }, 1944 { 1945 name: "SUBSD", 1946 argLen: 2, 1947 resultInArg0: true, 1948 asm: x86.ASUBSD, 1949 reg: regInfo{ 1950 inputs: []inputInfo{ 1951 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1952 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1953 }, 1954 outputs: []outputInfo{ 1955 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1956 }, 1957 }, 1958 }, 1959 { 1960 name: "MULSS", 1961 argLen: 2, 1962 commutative: true, 1963 resultInArg0: true, 1964 usesScratch: true, 1965 asm: x86.AMULSS, 1966 reg: regInfo{ 1967 inputs: []inputInfo{ 1968 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1969 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1970 }, 1971 outputs: []outputInfo{ 1972 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1973 }, 1974 }, 1975 }, 1976 { 1977 name: "MULSD", 1978 argLen: 2, 1979 commutative: true, 1980 resultInArg0: true, 1981 asm: x86.AMULSD, 1982 reg: regInfo{ 1983 inputs: []inputInfo{ 1984 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1985 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1986 }, 1987 outputs: []outputInfo{ 1988 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1989 }, 1990 }, 1991 }, 1992 { 1993 name: "DIVSS", 1994 argLen: 2, 1995 resultInArg0: true, 1996 usesScratch: true, 1997 asm: x86.ADIVSS, 1998 reg: regInfo{ 1999 inputs: []inputInfo{ 2000 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2001 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2002 }, 2003 outputs: []outputInfo{ 2004 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2005 }, 2006 }, 2007 }, 2008 { 2009 name: "DIVSD", 2010 argLen: 2, 2011 resultInArg0: true, 2012 asm: x86.ADIVSD, 2013 reg: regInfo{ 2014 inputs: []inputInfo{ 2015 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2016 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2017 }, 2018 outputs: []outputInfo{ 2019 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2020 }, 2021 }, 2022 }, 2023 { 2024 name: "MOVSSload", 2025 auxType: auxSymOff, 2026 argLen: 2, 2027 faultOnNilArg0: true, 2028 asm: x86.AMOVSS, 2029 reg: regInfo{ 2030 inputs: []inputInfo{ 2031 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2032 }, 2033 outputs: []outputInfo{ 2034 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2035 }, 2036 }, 2037 }, 2038 { 2039 name: "MOVSDload", 2040 auxType: auxSymOff, 2041 argLen: 2, 2042 faultOnNilArg0: true, 2043 asm: x86.AMOVSD, 2044 reg: regInfo{ 2045 inputs: []inputInfo{ 2046 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2047 }, 2048 outputs: []outputInfo{ 2049 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2050 }, 2051 }, 2052 }, 2053 { 2054 name: "MOVSSconst", 2055 auxType: auxFloat32, 2056 argLen: 0, 2057 rematerializeable: true, 2058 asm: x86.AMOVSS, 2059 reg: regInfo{ 2060 outputs: []outputInfo{ 2061 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2062 }, 2063 }, 2064 }, 2065 { 2066 name: "MOVSDconst", 2067 auxType: auxFloat64, 2068 argLen: 0, 2069 rematerializeable: true, 2070 asm: x86.AMOVSD, 2071 reg: regInfo{ 2072 outputs: []outputInfo{ 2073 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2074 }, 2075 }, 2076 }, 2077 { 2078 name: "MOVSSloadidx1", 2079 auxType: auxSymOff, 2080 argLen: 3, 2081 asm: x86.AMOVSS, 2082 reg: regInfo{ 2083 inputs: []inputInfo{ 2084 {1, 255}, // AX CX DX BX SP BP SI DI 2085 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2086 }, 2087 outputs: []outputInfo{ 2088 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2089 }, 2090 }, 2091 }, 2092 { 2093 name: "MOVSSloadidx4", 2094 auxType: auxSymOff, 2095 argLen: 3, 2096 asm: x86.AMOVSS, 2097 reg: regInfo{ 2098 inputs: []inputInfo{ 2099 {1, 255}, // AX CX DX BX SP BP SI DI 2100 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2101 }, 2102 outputs: []outputInfo{ 2103 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2104 }, 2105 }, 2106 }, 2107 { 2108 name: "MOVSDloadidx1", 2109 auxType: auxSymOff, 2110 argLen: 3, 2111 asm: x86.AMOVSD, 2112 reg: regInfo{ 2113 inputs: []inputInfo{ 2114 {1, 255}, // AX CX DX BX SP BP SI DI 2115 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2116 }, 2117 outputs: []outputInfo{ 2118 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2119 }, 2120 }, 2121 }, 2122 { 2123 name: "MOVSDloadidx8", 2124 auxType: auxSymOff, 2125 argLen: 3, 2126 asm: x86.AMOVSD, 2127 reg: regInfo{ 2128 inputs: []inputInfo{ 2129 {1, 255}, // AX CX DX BX SP BP SI DI 2130 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2131 }, 2132 outputs: []outputInfo{ 2133 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2134 }, 2135 }, 2136 }, 2137 { 2138 name: "MOVSSstore", 2139 auxType: auxSymOff, 2140 argLen: 3, 2141 faultOnNilArg0: true, 2142 asm: x86.AMOVSS, 2143 reg: regInfo{ 2144 inputs: []inputInfo{ 2145 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2146 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2147 }, 2148 }, 2149 }, 2150 { 2151 name: "MOVSDstore", 2152 auxType: auxSymOff, 2153 argLen: 3, 2154 faultOnNilArg0: true, 2155 asm: x86.AMOVSD, 2156 reg: regInfo{ 2157 inputs: []inputInfo{ 2158 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2159 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2160 }, 2161 }, 2162 }, 2163 { 2164 name: "MOVSSstoreidx1", 2165 auxType: auxSymOff, 2166 argLen: 4, 2167 asm: x86.AMOVSS, 2168 reg: regInfo{ 2169 inputs: []inputInfo{ 2170 {1, 255}, // AX CX DX BX SP BP SI DI 2171 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2172 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2173 }, 2174 }, 2175 }, 2176 { 2177 name: "MOVSSstoreidx4", 2178 auxType: auxSymOff, 2179 argLen: 4, 2180 asm: x86.AMOVSS, 2181 reg: regInfo{ 2182 inputs: []inputInfo{ 2183 {1, 255}, // AX CX DX BX SP BP SI DI 2184 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2185 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2186 }, 2187 }, 2188 }, 2189 { 2190 name: "MOVSDstoreidx1", 2191 auxType: auxSymOff, 2192 argLen: 4, 2193 asm: x86.AMOVSD, 2194 reg: regInfo{ 2195 inputs: []inputInfo{ 2196 {1, 255}, // AX CX DX BX SP BP SI DI 2197 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2198 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2199 }, 2200 }, 2201 }, 2202 { 2203 name: "MOVSDstoreidx8", 2204 auxType: auxSymOff, 2205 argLen: 4, 2206 asm: x86.AMOVSD, 2207 reg: regInfo{ 2208 inputs: []inputInfo{ 2209 {1, 255}, // AX CX DX BX SP BP SI DI 2210 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2211 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2212 }, 2213 }, 2214 }, 2215 { 2216 name: "ADDL", 2217 argLen: 2, 2218 commutative: true, 2219 clobberFlags: true, 2220 asm: x86.AADDL, 2221 reg: regInfo{ 2222 inputs: []inputInfo{ 2223 {1, 239}, // AX CX DX BX BP SI DI 2224 {0, 255}, // AX CX DX BX SP BP SI DI 2225 }, 2226 outputs: []outputInfo{ 2227 {0, 239}, // AX CX DX BX BP SI DI 2228 }, 2229 }, 2230 }, 2231 { 2232 name: "ADDLconst", 2233 auxType: auxInt32, 2234 argLen: 1, 2235 clobberFlags: true, 2236 asm: x86.AADDL, 2237 reg: regInfo{ 2238 inputs: []inputInfo{ 2239 {0, 255}, // AX CX DX BX SP BP SI DI 2240 }, 2241 outputs: []outputInfo{ 2242 {0, 239}, // AX CX DX BX BP SI DI 2243 }, 2244 }, 2245 }, 2246 { 2247 name: "ADDLcarry", 2248 argLen: 2, 2249 commutative: true, 2250 resultInArg0: true, 2251 asm: x86.AADDL, 2252 reg: regInfo{ 2253 inputs: []inputInfo{ 2254 {0, 239}, // AX CX DX BX BP SI DI 2255 {1, 239}, // AX CX DX BX BP SI DI 2256 }, 2257 outputs: []outputInfo{ 2258 {1, 0}, 2259 {0, 239}, // AX CX DX BX BP SI DI 2260 }, 2261 }, 2262 }, 2263 { 2264 name: "ADDLconstcarry", 2265 auxType: auxInt32, 2266 argLen: 1, 2267 resultInArg0: true, 2268 asm: x86.AADDL, 2269 reg: regInfo{ 2270 inputs: []inputInfo{ 2271 {0, 239}, // AX CX DX BX BP SI DI 2272 }, 2273 outputs: []outputInfo{ 2274 {1, 0}, 2275 {0, 239}, // AX CX DX BX BP SI DI 2276 }, 2277 }, 2278 }, 2279 { 2280 name: "ADCL", 2281 argLen: 3, 2282 commutative: true, 2283 resultInArg0: true, 2284 clobberFlags: true, 2285 asm: x86.AADCL, 2286 reg: regInfo{ 2287 inputs: []inputInfo{ 2288 {0, 239}, // AX CX DX BX BP SI DI 2289 {1, 239}, // AX CX DX BX BP SI DI 2290 }, 2291 outputs: []outputInfo{ 2292 {0, 239}, // AX CX DX BX BP SI DI 2293 }, 2294 }, 2295 }, 2296 { 2297 name: "ADCLconst", 2298 auxType: auxInt32, 2299 argLen: 2, 2300 resultInArg0: true, 2301 clobberFlags: true, 2302 asm: x86.AADCL, 2303 reg: regInfo{ 2304 inputs: []inputInfo{ 2305 {0, 239}, // AX CX DX BX BP SI DI 2306 }, 2307 outputs: []outputInfo{ 2308 {0, 239}, // AX CX DX BX BP SI DI 2309 }, 2310 }, 2311 }, 2312 { 2313 name: "SUBL", 2314 argLen: 2, 2315 resultInArg0: true, 2316 clobberFlags: true, 2317 asm: x86.ASUBL, 2318 reg: regInfo{ 2319 inputs: []inputInfo{ 2320 {0, 239}, // AX CX DX BX BP SI DI 2321 {1, 239}, // AX CX DX BX BP SI DI 2322 }, 2323 outputs: []outputInfo{ 2324 {0, 239}, // AX CX DX BX BP SI DI 2325 }, 2326 }, 2327 }, 2328 { 2329 name: "SUBLconst", 2330 auxType: auxInt32, 2331 argLen: 1, 2332 resultInArg0: true, 2333 clobberFlags: true, 2334 asm: x86.ASUBL, 2335 reg: regInfo{ 2336 inputs: []inputInfo{ 2337 {0, 239}, // AX CX DX BX BP SI DI 2338 }, 2339 outputs: []outputInfo{ 2340 {0, 239}, // AX CX DX BX BP SI DI 2341 }, 2342 }, 2343 }, 2344 { 2345 name: "SUBLcarry", 2346 argLen: 2, 2347 resultInArg0: true, 2348 asm: x86.ASUBL, 2349 reg: regInfo{ 2350 inputs: []inputInfo{ 2351 {0, 239}, // AX CX DX BX BP SI DI 2352 {1, 239}, // AX CX DX BX BP SI DI 2353 }, 2354 outputs: []outputInfo{ 2355 {1, 0}, 2356 {0, 239}, // AX CX DX BX BP SI DI 2357 }, 2358 }, 2359 }, 2360 { 2361 name: "SUBLconstcarry", 2362 auxType: auxInt32, 2363 argLen: 1, 2364 resultInArg0: true, 2365 asm: x86.ASUBL, 2366 reg: regInfo{ 2367 inputs: []inputInfo{ 2368 {0, 239}, // AX CX DX BX BP SI DI 2369 }, 2370 outputs: []outputInfo{ 2371 {1, 0}, 2372 {0, 239}, // AX CX DX BX BP SI DI 2373 }, 2374 }, 2375 }, 2376 { 2377 name: "SBBL", 2378 argLen: 3, 2379 resultInArg0: true, 2380 clobberFlags: true, 2381 asm: x86.ASBBL, 2382 reg: regInfo{ 2383 inputs: []inputInfo{ 2384 {0, 239}, // AX CX DX BX BP SI DI 2385 {1, 239}, // AX CX DX BX BP SI DI 2386 }, 2387 outputs: []outputInfo{ 2388 {0, 239}, // AX CX DX BX BP SI DI 2389 }, 2390 }, 2391 }, 2392 { 2393 name: "SBBLconst", 2394 auxType: auxInt32, 2395 argLen: 2, 2396 resultInArg0: true, 2397 clobberFlags: true, 2398 asm: x86.ASBBL, 2399 reg: regInfo{ 2400 inputs: []inputInfo{ 2401 {0, 239}, // AX CX DX BX BP SI DI 2402 }, 2403 outputs: []outputInfo{ 2404 {0, 239}, // AX CX DX BX BP SI DI 2405 }, 2406 }, 2407 }, 2408 { 2409 name: "MULL", 2410 argLen: 2, 2411 commutative: true, 2412 resultInArg0: true, 2413 clobberFlags: true, 2414 asm: x86.AIMULL, 2415 reg: regInfo{ 2416 inputs: []inputInfo{ 2417 {0, 239}, // AX CX DX BX BP SI DI 2418 {1, 239}, // AX CX DX BX BP SI DI 2419 }, 2420 outputs: []outputInfo{ 2421 {0, 239}, // AX CX DX BX BP SI DI 2422 }, 2423 }, 2424 }, 2425 { 2426 name: "MULLconst", 2427 auxType: auxInt32, 2428 argLen: 1, 2429 resultInArg0: true, 2430 clobberFlags: true, 2431 asm: x86.AIMULL, 2432 reg: regInfo{ 2433 inputs: []inputInfo{ 2434 {0, 239}, // AX CX DX BX BP SI DI 2435 }, 2436 outputs: []outputInfo{ 2437 {0, 239}, // AX CX DX BX BP SI DI 2438 }, 2439 }, 2440 }, 2441 { 2442 name: "HMULL", 2443 argLen: 2, 2444 clobberFlags: true, 2445 asm: x86.AIMULL, 2446 reg: regInfo{ 2447 inputs: []inputInfo{ 2448 {0, 1}, // AX 2449 {1, 255}, // AX CX DX BX SP BP SI DI 2450 }, 2451 clobbers: 1, // AX 2452 outputs: []outputInfo{ 2453 {0, 4}, // DX 2454 }, 2455 }, 2456 }, 2457 { 2458 name: "HMULLU", 2459 argLen: 2, 2460 clobberFlags: true, 2461 asm: x86.AMULL, 2462 reg: regInfo{ 2463 inputs: []inputInfo{ 2464 {0, 1}, // AX 2465 {1, 255}, // AX CX DX BX SP BP SI DI 2466 }, 2467 clobbers: 1, // AX 2468 outputs: []outputInfo{ 2469 {0, 4}, // DX 2470 }, 2471 }, 2472 }, 2473 { 2474 name: "HMULW", 2475 argLen: 2, 2476 clobberFlags: true, 2477 asm: x86.AIMULW, 2478 reg: regInfo{ 2479 inputs: []inputInfo{ 2480 {0, 1}, // AX 2481 {1, 255}, // AX CX DX BX SP BP SI DI 2482 }, 2483 clobbers: 1, // AX 2484 outputs: []outputInfo{ 2485 {0, 4}, // DX 2486 }, 2487 }, 2488 }, 2489 { 2490 name: "HMULB", 2491 argLen: 2, 2492 clobberFlags: true, 2493 asm: x86.AIMULB, 2494 reg: regInfo{ 2495 inputs: []inputInfo{ 2496 {0, 1}, // AX 2497 {1, 255}, // AX CX DX BX SP BP SI DI 2498 }, 2499 clobbers: 1, // AX 2500 outputs: []outputInfo{ 2501 {0, 4}, // DX 2502 }, 2503 }, 2504 }, 2505 { 2506 name: "HMULWU", 2507 argLen: 2, 2508 clobberFlags: true, 2509 asm: x86.AMULW, 2510 reg: regInfo{ 2511 inputs: []inputInfo{ 2512 {0, 1}, // AX 2513 {1, 255}, // AX CX DX BX SP BP SI DI 2514 }, 2515 clobbers: 1, // AX 2516 outputs: []outputInfo{ 2517 {0, 4}, // DX 2518 }, 2519 }, 2520 }, 2521 { 2522 name: "HMULBU", 2523 argLen: 2, 2524 clobberFlags: true, 2525 asm: x86.AMULB, 2526 reg: regInfo{ 2527 inputs: []inputInfo{ 2528 {0, 1}, // AX 2529 {1, 255}, // AX CX DX BX SP BP SI DI 2530 }, 2531 clobbers: 1, // AX 2532 outputs: []outputInfo{ 2533 {0, 4}, // DX 2534 }, 2535 }, 2536 }, 2537 { 2538 name: "MULLQU", 2539 argLen: 2, 2540 clobberFlags: true, 2541 asm: x86.AMULL, 2542 reg: regInfo{ 2543 inputs: []inputInfo{ 2544 {0, 1}, // AX 2545 {1, 255}, // AX CX DX BX SP BP SI DI 2546 }, 2547 outputs: []outputInfo{ 2548 {0, 4}, // DX 2549 {1, 1}, // AX 2550 }, 2551 }, 2552 }, 2553 { 2554 name: "DIVL", 2555 argLen: 2, 2556 clobberFlags: true, 2557 asm: x86.AIDIVL, 2558 reg: regInfo{ 2559 inputs: []inputInfo{ 2560 {0, 1}, // AX 2561 {1, 251}, // AX CX BX SP BP SI DI 2562 }, 2563 clobbers: 4, // DX 2564 outputs: []outputInfo{ 2565 {0, 1}, // AX 2566 }, 2567 }, 2568 }, 2569 { 2570 name: "DIVW", 2571 argLen: 2, 2572 clobberFlags: true, 2573 asm: x86.AIDIVW, 2574 reg: regInfo{ 2575 inputs: []inputInfo{ 2576 {0, 1}, // AX 2577 {1, 251}, // AX CX BX SP BP SI DI 2578 }, 2579 clobbers: 4, // DX 2580 outputs: []outputInfo{ 2581 {0, 1}, // AX 2582 }, 2583 }, 2584 }, 2585 { 2586 name: "DIVLU", 2587 argLen: 2, 2588 clobberFlags: true, 2589 asm: x86.ADIVL, 2590 reg: regInfo{ 2591 inputs: []inputInfo{ 2592 {0, 1}, // AX 2593 {1, 251}, // AX CX BX SP BP SI DI 2594 }, 2595 clobbers: 4, // DX 2596 outputs: []outputInfo{ 2597 {0, 1}, // AX 2598 }, 2599 }, 2600 }, 2601 { 2602 name: "DIVWU", 2603 argLen: 2, 2604 clobberFlags: true, 2605 asm: x86.ADIVW, 2606 reg: regInfo{ 2607 inputs: []inputInfo{ 2608 {0, 1}, // AX 2609 {1, 251}, // AX CX BX SP BP SI DI 2610 }, 2611 clobbers: 4, // DX 2612 outputs: []outputInfo{ 2613 {0, 1}, // AX 2614 }, 2615 }, 2616 }, 2617 { 2618 name: "MODL", 2619 argLen: 2, 2620 clobberFlags: true, 2621 asm: x86.AIDIVL, 2622 reg: regInfo{ 2623 inputs: []inputInfo{ 2624 {0, 1}, // AX 2625 {1, 251}, // AX CX BX SP BP SI DI 2626 }, 2627 clobbers: 1, // AX 2628 outputs: []outputInfo{ 2629 {0, 4}, // DX 2630 }, 2631 }, 2632 }, 2633 { 2634 name: "MODW", 2635 argLen: 2, 2636 clobberFlags: true, 2637 asm: x86.AIDIVW, 2638 reg: regInfo{ 2639 inputs: []inputInfo{ 2640 {0, 1}, // AX 2641 {1, 251}, // AX CX BX SP BP SI DI 2642 }, 2643 clobbers: 1, // AX 2644 outputs: []outputInfo{ 2645 {0, 4}, // DX 2646 }, 2647 }, 2648 }, 2649 { 2650 name: "MODLU", 2651 argLen: 2, 2652 clobberFlags: true, 2653 asm: x86.ADIVL, 2654 reg: regInfo{ 2655 inputs: []inputInfo{ 2656 {0, 1}, // AX 2657 {1, 251}, // AX CX BX SP BP SI DI 2658 }, 2659 clobbers: 1, // AX 2660 outputs: []outputInfo{ 2661 {0, 4}, // DX 2662 }, 2663 }, 2664 }, 2665 { 2666 name: "MODWU", 2667 argLen: 2, 2668 clobberFlags: true, 2669 asm: x86.ADIVW, 2670 reg: regInfo{ 2671 inputs: []inputInfo{ 2672 {0, 1}, // AX 2673 {1, 251}, // AX CX BX SP BP SI DI 2674 }, 2675 clobbers: 1, // AX 2676 outputs: []outputInfo{ 2677 {0, 4}, // DX 2678 }, 2679 }, 2680 }, 2681 { 2682 name: "ANDL", 2683 argLen: 2, 2684 commutative: true, 2685 resultInArg0: true, 2686 clobberFlags: true, 2687 asm: x86.AANDL, 2688 reg: regInfo{ 2689 inputs: []inputInfo{ 2690 {0, 239}, // AX CX DX BX BP SI DI 2691 {1, 239}, // AX CX DX BX BP SI DI 2692 }, 2693 outputs: []outputInfo{ 2694 {0, 239}, // AX CX DX BX BP SI DI 2695 }, 2696 }, 2697 }, 2698 { 2699 name: "ANDLconst", 2700 auxType: auxInt32, 2701 argLen: 1, 2702 resultInArg0: true, 2703 clobberFlags: true, 2704 asm: x86.AANDL, 2705 reg: regInfo{ 2706 inputs: []inputInfo{ 2707 {0, 239}, // AX CX DX BX BP SI DI 2708 }, 2709 outputs: []outputInfo{ 2710 {0, 239}, // AX CX DX BX BP SI DI 2711 }, 2712 }, 2713 }, 2714 { 2715 name: "ORL", 2716 argLen: 2, 2717 commutative: true, 2718 resultInArg0: true, 2719 clobberFlags: true, 2720 asm: x86.AORL, 2721 reg: regInfo{ 2722 inputs: []inputInfo{ 2723 {0, 239}, // AX CX DX BX BP SI DI 2724 {1, 239}, // AX CX DX BX BP SI DI 2725 }, 2726 outputs: []outputInfo{ 2727 {0, 239}, // AX CX DX BX BP SI DI 2728 }, 2729 }, 2730 }, 2731 { 2732 name: "ORLconst", 2733 auxType: auxInt32, 2734 argLen: 1, 2735 resultInArg0: true, 2736 clobberFlags: true, 2737 asm: x86.AORL, 2738 reg: regInfo{ 2739 inputs: []inputInfo{ 2740 {0, 239}, // AX CX DX BX BP SI DI 2741 }, 2742 outputs: []outputInfo{ 2743 {0, 239}, // AX CX DX BX BP SI DI 2744 }, 2745 }, 2746 }, 2747 { 2748 name: "XORL", 2749 argLen: 2, 2750 commutative: true, 2751 resultInArg0: true, 2752 clobberFlags: true, 2753 asm: x86.AXORL, 2754 reg: regInfo{ 2755 inputs: []inputInfo{ 2756 {0, 239}, // AX CX DX BX BP SI DI 2757 {1, 239}, // AX CX DX BX BP SI DI 2758 }, 2759 outputs: []outputInfo{ 2760 {0, 239}, // AX CX DX BX BP SI DI 2761 }, 2762 }, 2763 }, 2764 { 2765 name: "XORLconst", 2766 auxType: auxInt32, 2767 argLen: 1, 2768 resultInArg0: true, 2769 clobberFlags: true, 2770 asm: x86.AXORL, 2771 reg: regInfo{ 2772 inputs: []inputInfo{ 2773 {0, 239}, // AX CX DX BX BP SI DI 2774 }, 2775 outputs: []outputInfo{ 2776 {0, 239}, // AX CX DX BX BP SI DI 2777 }, 2778 }, 2779 }, 2780 { 2781 name: "CMPL", 2782 argLen: 2, 2783 asm: x86.ACMPL, 2784 reg: regInfo{ 2785 inputs: []inputInfo{ 2786 {0, 255}, // AX CX DX BX SP BP SI DI 2787 {1, 255}, // AX CX DX BX SP BP SI DI 2788 }, 2789 }, 2790 }, 2791 { 2792 name: "CMPW", 2793 argLen: 2, 2794 asm: x86.ACMPW, 2795 reg: regInfo{ 2796 inputs: []inputInfo{ 2797 {0, 255}, // AX CX DX BX SP BP SI DI 2798 {1, 255}, // AX CX DX BX SP BP SI DI 2799 }, 2800 }, 2801 }, 2802 { 2803 name: "CMPB", 2804 argLen: 2, 2805 asm: x86.ACMPB, 2806 reg: regInfo{ 2807 inputs: []inputInfo{ 2808 {0, 255}, // AX CX DX BX SP BP SI DI 2809 {1, 255}, // AX CX DX BX SP BP SI DI 2810 }, 2811 }, 2812 }, 2813 { 2814 name: "CMPLconst", 2815 auxType: auxInt32, 2816 argLen: 1, 2817 asm: x86.ACMPL, 2818 reg: regInfo{ 2819 inputs: []inputInfo{ 2820 {0, 255}, // AX CX DX BX SP BP SI DI 2821 }, 2822 }, 2823 }, 2824 { 2825 name: "CMPWconst", 2826 auxType: auxInt16, 2827 argLen: 1, 2828 asm: x86.ACMPW, 2829 reg: regInfo{ 2830 inputs: []inputInfo{ 2831 {0, 255}, // AX CX DX BX SP BP SI DI 2832 }, 2833 }, 2834 }, 2835 { 2836 name: "CMPBconst", 2837 auxType: auxInt8, 2838 argLen: 1, 2839 asm: x86.ACMPB, 2840 reg: regInfo{ 2841 inputs: []inputInfo{ 2842 {0, 255}, // AX CX DX BX SP BP SI DI 2843 }, 2844 }, 2845 }, 2846 { 2847 name: "UCOMISS", 2848 argLen: 2, 2849 usesScratch: true, 2850 asm: x86.AUCOMISS, 2851 reg: regInfo{ 2852 inputs: []inputInfo{ 2853 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2854 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2855 }, 2856 }, 2857 }, 2858 { 2859 name: "UCOMISD", 2860 argLen: 2, 2861 usesScratch: true, 2862 asm: x86.AUCOMISD, 2863 reg: regInfo{ 2864 inputs: []inputInfo{ 2865 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2866 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2867 }, 2868 }, 2869 }, 2870 { 2871 name: "TESTL", 2872 argLen: 2, 2873 asm: x86.ATESTL, 2874 reg: regInfo{ 2875 inputs: []inputInfo{ 2876 {0, 255}, // AX CX DX BX SP BP SI DI 2877 {1, 255}, // AX CX DX BX SP BP SI DI 2878 }, 2879 }, 2880 }, 2881 { 2882 name: "TESTW", 2883 argLen: 2, 2884 asm: x86.ATESTW, 2885 reg: regInfo{ 2886 inputs: []inputInfo{ 2887 {0, 255}, // AX CX DX BX SP BP SI DI 2888 {1, 255}, // AX CX DX BX SP BP SI DI 2889 }, 2890 }, 2891 }, 2892 { 2893 name: "TESTB", 2894 argLen: 2, 2895 asm: x86.ATESTB, 2896 reg: regInfo{ 2897 inputs: []inputInfo{ 2898 {0, 255}, // AX CX DX BX SP BP SI DI 2899 {1, 255}, // AX CX DX BX SP BP SI DI 2900 }, 2901 }, 2902 }, 2903 { 2904 name: "TESTLconst", 2905 auxType: auxInt32, 2906 argLen: 1, 2907 asm: x86.ATESTL, 2908 reg: regInfo{ 2909 inputs: []inputInfo{ 2910 {0, 255}, // AX CX DX BX SP BP SI DI 2911 }, 2912 }, 2913 }, 2914 { 2915 name: "TESTWconst", 2916 auxType: auxInt16, 2917 argLen: 1, 2918 asm: x86.ATESTW, 2919 reg: regInfo{ 2920 inputs: []inputInfo{ 2921 {0, 255}, // AX CX DX BX SP BP SI DI 2922 }, 2923 }, 2924 }, 2925 { 2926 name: "TESTBconst", 2927 auxType: auxInt8, 2928 argLen: 1, 2929 asm: x86.ATESTB, 2930 reg: regInfo{ 2931 inputs: []inputInfo{ 2932 {0, 255}, // AX CX DX BX SP BP SI DI 2933 }, 2934 }, 2935 }, 2936 { 2937 name: "SHLL", 2938 argLen: 2, 2939 resultInArg0: true, 2940 clobberFlags: true, 2941 asm: x86.ASHLL, 2942 reg: regInfo{ 2943 inputs: []inputInfo{ 2944 {1, 2}, // CX 2945 {0, 239}, // AX CX DX BX BP SI DI 2946 }, 2947 outputs: []outputInfo{ 2948 {0, 239}, // AX CX DX BX BP SI DI 2949 }, 2950 }, 2951 }, 2952 { 2953 name: "SHLLconst", 2954 auxType: auxInt32, 2955 argLen: 1, 2956 resultInArg0: true, 2957 clobberFlags: true, 2958 asm: x86.ASHLL, 2959 reg: regInfo{ 2960 inputs: []inputInfo{ 2961 {0, 239}, // AX CX DX BX BP SI DI 2962 }, 2963 outputs: []outputInfo{ 2964 {0, 239}, // AX CX DX BX BP SI DI 2965 }, 2966 }, 2967 }, 2968 { 2969 name: "SHRL", 2970 argLen: 2, 2971 resultInArg0: true, 2972 clobberFlags: true, 2973 asm: x86.ASHRL, 2974 reg: regInfo{ 2975 inputs: []inputInfo{ 2976 {1, 2}, // CX 2977 {0, 239}, // AX CX DX BX BP SI DI 2978 }, 2979 outputs: []outputInfo{ 2980 {0, 239}, // AX CX DX BX BP SI DI 2981 }, 2982 }, 2983 }, 2984 { 2985 name: "SHRW", 2986 argLen: 2, 2987 resultInArg0: true, 2988 clobberFlags: true, 2989 asm: x86.ASHRW, 2990 reg: regInfo{ 2991 inputs: []inputInfo{ 2992 {1, 2}, // CX 2993 {0, 239}, // AX CX DX BX BP SI DI 2994 }, 2995 outputs: []outputInfo{ 2996 {0, 239}, // AX CX DX BX BP SI DI 2997 }, 2998 }, 2999 }, 3000 { 3001 name: "SHRB", 3002 argLen: 2, 3003 resultInArg0: true, 3004 clobberFlags: true, 3005 asm: x86.ASHRB, 3006 reg: regInfo{ 3007 inputs: []inputInfo{ 3008 {1, 2}, // CX 3009 {0, 239}, // AX CX DX BX BP SI DI 3010 }, 3011 outputs: []outputInfo{ 3012 {0, 239}, // AX CX DX BX BP SI DI 3013 }, 3014 }, 3015 }, 3016 { 3017 name: "SHRLconst", 3018 auxType: auxInt32, 3019 argLen: 1, 3020 resultInArg0: true, 3021 clobberFlags: true, 3022 asm: x86.ASHRL, 3023 reg: regInfo{ 3024 inputs: []inputInfo{ 3025 {0, 239}, // AX CX DX BX BP SI DI 3026 }, 3027 outputs: []outputInfo{ 3028 {0, 239}, // AX CX DX BX BP SI DI 3029 }, 3030 }, 3031 }, 3032 { 3033 name: "SHRWconst", 3034 auxType: auxInt16, 3035 argLen: 1, 3036 resultInArg0: true, 3037 clobberFlags: true, 3038 asm: x86.ASHRW, 3039 reg: regInfo{ 3040 inputs: []inputInfo{ 3041 {0, 239}, // AX CX DX BX BP SI DI 3042 }, 3043 outputs: []outputInfo{ 3044 {0, 239}, // AX CX DX BX BP SI DI 3045 }, 3046 }, 3047 }, 3048 { 3049 name: "SHRBconst", 3050 auxType: auxInt8, 3051 argLen: 1, 3052 resultInArg0: true, 3053 clobberFlags: true, 3054 asm: x86.ASHRB, 3055 reg: regInfo{ 3056 inputs: []inputInfo{ 3057 {0, 239}, // AX CX DX BX BP SI DI 3058 }, 3059 outputs: []outputInfo{ 3060 {0, 239}, // AX CX DX BX BP SI DI 3061 }, 3062 }, 3063 }, 3064 { 3065 name: "SARL", 3066 argLen: 2, 3067 resultInArg0: true, 3068 clobberFlags: true, 3069 asm: x86.ASARL, 3070 reg: regInfo{ 3071 inputs: []inputInfo{ 3072 {1, 2}, // CX 3073 {0, 239}, // AX CX DX BX BP SI DI 3074 }, 3075 outputs: []outputInfo{ 3076 {0, 239}, // AX CX DX BX BP SI DI 3077 }, 3078 }, 3079 }, 3080 { 3081 name: "SARW", 3082 argLen: 2, 3083 resultInArg0: true, 3084 clobberFlags: true, 3085 asm: x86.ASARW, 3086 reg: regInfo{ 3087 inputs: []inputInfo{ 3088 {1, 2}, // CX 3089 {0, 239}, // AX CX DX BX BP SI DI 3090 }, 3091 outputs: []outputInfo{ 3092 {0, 239}, // AX CX DX BX BP SI DI 3093 }, 3094 }, 3095 }, 3096 { 3097 name: "SARB", 3098 argLen: 2, 3099 resultInArg0: true, 3100 clobberFlags: true, 3101 asm: x86.ASARB, 3102 reg: regInfo{ 3103 inputs: []inputInfo{ 3104 {1, 2}, // CX 3105 {0, 239}, // AX CX DX BX BP SI DI 3106 }, 3107 outputs: []outputInfo{ 3108 {0, 239}, // AX CX DX BX BP SI DI 3109 }, 3110 }, 3111 }, 3112 { 3113 name: "SARLconst", 3114 auxType: auxInt32, 3115 argLen: 1, 3116 resultInArg0: true, 3117 clobberFlags: true, 3118 asm: x86.ASARL, 3119 reg: regInfo{ 3120 inputs: []inputInfo{ 3121 {0, 239}, // AX CX DX BX BP SI DI 3122 }, 3123 outputs: []outputInfo{ 3124 {0, 239}, // AX CX DX BX BP SI DI 3125 }, 3126 }, 3127 }, 3128 { 3129 name: "SARWconst", 3130 auxType: auxInt16, 3131 argLen: 1, 3132 resultInArg0: true, 3133 clobberFlags: true, 3134 asm: x86.ASARW, 3135 reg: regInfo{ 3136 inputs: []inputInfo{ 3137 {0, 239}, // AX CX DX BX BP SI DI 3138 }, 3139 outputs: []outputInfo{ 3140 {0, 239}, // AX CX DX BX BP SI DI 3141 }, 3142 }, 3143 }, 3144 { 3145 name: "SARBconst", 3146 auxType: auxInt8, 3147 argLen: 1, 3148 resultInArg0: true, 3149 clobberFlags: true, 3150 asm: x86.ASARB, 3151 reg: regInfo{ 3152 inputs: []inputInfo{ 3153 {0, 239}, // AX CX DX BX BP SI DI 3154 }, 3155 outputs: []outputInfo{ 3156 {0, 239}, // AX CX DX BX BP SI DI 3157 }, 3158 }, 3159 }, 3160 { 3161 name: "ROLLconst", 3162 auxType: auxInt32, 3163 argLen: 1, 3164 resultInArg0: true, 3165 clobberFlags: true, 3166 asm: x86.AROLL, 3167 reg: regInfo{ 3168 inputs: []inputInfo{ 3169 {0, 239}, // AX CX DX BX BP SI DI 3170 }, 3171 outputs: []outputInfo{ 3172 {0, 239}, // AX CX DX BX BP SI DI 3173 }, 3174 }, 3175 }, 3176 { 3177 name: "ROLWconst", 3178 auxType: auxInt16, 3179 argLen: 1, 3180 resultInArg0: true, 3181 clobberFlags: true, 3182 asm: x86.AROLW, 3183 reg: regInfo{ 3184 inputs: []inputInfo{ 3185 {0, 239}, // AX CX DX BX BP SI DI 3186 }, 3187 outputs: []outputInfo{ 3188 {0, 239}, // AX CX DX BX BP SI DI 3189 }, 3190 }, 3191 }, 3192 { 3193 name: "ROLBconst", 3194 auxType: auxInt8, 3195 argLen: 1, 3196 resultInArg0: true, 3197 clobberFlags: true, 3198 asm: x86.AROLB, 3199 reg: regInfo{ 3200 inputs: []inputInfo{ 3201 {0, 239}, // AX CX DX BX BP SI DI 3202 }, 3203 outputs: []outputInfo{ 3204 {0, 239}, // AX CX DX BX BP SI DI 3205 }, 3206 }, 3207 }, 3208 { 3209 name: "NEGL", 3210 argLen: 1, 3211 resultInArg0: true, 3212 clobberFlags: true, 3213 asm: x86.ANEGL, 3214 reg: regInfo{ 3215 inputs: []inputInfo{ 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 outputs: []outputInfo{ 3219 {0, 239}, // AX CX DX BX BP SI DI 3220 }, 3221 }, 3222 }, 3223 { 3224 name: "NOTL", 3225 argLen: 1, 3226 resultInArg0: true, 3227 clobberFlags: true, 3228 asm: x86.ANOTL, 3229 reg: regInfo{ 3230 inputs: []inputInfo{ 3231 {0, 239}, // AX CX DX BX BP SI DI 3232 }, 3233 outputs: []outputInfo{ 3234 {0, 239}, // AX CX DX BX BP SI DI 3235 }, 3236 }, 3237 }, 3238 { 3239 name: "BSFL", 3240 argLen: 1, 3241 clobberFlags: true, 3242 asm: x86.ABSFL, 3243 reg: regInfo{ 3244 inputs: []inputInfo{ 3245 {0, 239}, // AX CX DX BX BP SI DI 3246 }, 3247 outputs: []outputInfo{ 3248 {0, 239}, // AX CX DX BX BP SI DI 3249 }, 3250 }, 3251 }, 3252 { 3253 name: "BSFW", 3254 argLen: 1, 3255 clobberFlags: true, 3256 asm: x86.ABSFW, 3257 reg: regInfo{ 3258 inputs: []inputInfo{ 3259 {0, 239}, // AX CX DX BX BP SI DI 3260 }, 3261 outputs: []outputInfo{ 3262 {0, 239}, // AX CX DX BX BP SI DI 3263 }, 3264 }, 3265 }, 3266 { 3267 name: "BSRL", 3268 argLen: 1, 3269 clobberFlags: true, 3270 asm: x86.ABSRL, 3271 reg: regInfo{ 3272 inputs: []inputInfo{ 3273 {0, 239}, // AX CX DX BX BP SI DI 3274 }, 3275 outputs: []outputInfo{ 3276 {0, 239}, // AX CX DX BX BP SI DI 3277 }, 3278 }, 3279 }, 3280 { 3281 name: "BSRW", 3282 argLen: 1, 3283 clobberFlags: true, 3284 asm: x86.ABSRW, 3285 reg: regInfo{ 3286 inputs: []inputInfo{ 3287 {0, 239}, // AX CX DX BX BP SI DI 3288 }, 3289 outputs: []outputInfo{ 3290 {0, 239}, // AX CX DX BX BP SI DI 3291 }, 3292 }, 3293 }, 3294 { 3295 name: "BSWAPL", 3296 argLen: 1, 3297 resultInArg0: true, 3298 clobberFlags: true, 3299 asm: x86.ABSWAPL, 3300 reg: regInfo{ 3301 inputs: []inputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 outputs: []outputInfo{ 3305 {0, 239}, // AX CX DX BX BP SI DI 3306 }, 3307 }, 3308 }, 3309 { 3310 name: "SQRTSD", 3311 argLen: 1, 3312 asm: x86.ASQRTSD, 3313 reg: regInfo{ 3314 inputs: []inputInfo{ 3315 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3316 }, 3317 outputs: []outputInfo{ 3318 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3319 }, 3320 }, 3321 }, 3322 { 3323 name: "SBBLcarrymask", 3324 argLen: 1, 3325 asm: x86.ASBBL, 3326 reg: regInfo{ 3327 outputs: []outputInfo{ 3328 {0, 239}, // AX CX DX BX BP SI DI 3329 }, 3330 }, 3331 }, 3332 { 3333 name: "SETEQ", 3334 argLen: 1, 3335 asm: x86.ASETEQ, 3336 reg: regInfo{ 3337 outputs: []outputInfo{ 3338 {0, 239}, // AX CX DX BX BP SI DI 3339 }, 3340 }, 3341 }, 3342 { 3343 name: "SETNE", 3344 argLen: 1, 3345 asm: x86.ASETNE, 3346 reg: regInfo{ 3347 outputs: []outputInfo{ 3348 {0, 239}, // AX CX DX BX BP SI DI 3349 }, 3350 }, 3351 }, 3352 { 3353 name: "SETL", 3354 argLen: 1, 3355 asm: x86.ASETLT, 3356 reg: regInfo{ 3357 outputs: []outputInfo{ 3358 {0, 239}, // AX CX DX BX BP SI DI 3359 }, 3360 }, 3361 }, 3362 { 3363 name: "SETLE", 3364 argLen: 1, 3365 asm: x86.ASETLE, 3366 reg: regInfo{ 3367 outputs: []outputInfo{ 3368 {0, 239}, // AX CX DX BX BP SI DI 3369 }, 3370 }, 3371 }, 3372 { 3373 name: "SETG", 3374 argLen: 1, 3375 asm: x86.ASETGT, 3376 reg: regInfo{ 3377 outputs: []outputInfo{ 3378 {0, 239}, // AX CX DX BX BP SI DI 3379 }, 3380 }, 3381 }, 3382 { 3383 name: "SETGE", 3384 argLen: 1, 3385 asm: x86.ASETGE, 3386 reg: regInfo{ 3387 outputs: []outputInfo{ 3388 {0, 239}, // AX CX DX BX BP SI DI 3389 }, 3390 }, 3391 }, 3392 { 3393 name: "SETB", 3394 argLen: 1, 3395 asm: x86.ASETCS, 3396 reg: regInfo{ 3397 outputs: []outputInfo{ 3398 {0, 239}, // AX CX DX BX BP SI DI 3399 }, 3400 }, 3401 }, 3402 { 3403 name: "SETBE", 3404 argLen: 1, 3405 asm: x86.ASETLS, 3406 reg: regInfo{ 3407 outputs: []outputInfo{ 3408 {0, 239}, // AX CX DX BX BP SI DI 3409 }, 3410 }, 3411 }, 3412 { 3413 name: "SETA", 3414 argLen: 1, 3415 asm: x86.ASETHI, 3416 reg: regInfo{ 3417 outputs: []outputInfo{ 3418 {0, 239}, // AX CX DX BX BP SI DI 3419 }, 3420 }, 3421 }, 3422 { 3423 name: "SETAE", 3424 argLen: 1, 3425 asm: x86.ASETCC, 3426 reg: regInfo{ 3427 outputs: []outputInfo{ 3428 {0, 239}, // AX CX DX BX BP SI DI 3429 }, 3430 }, 3431 }, 3432 { 3433 name: "SETEQF", 3434 argLen: 1, 3435 clobberFlags: true, 3436 asm: x86.ASETEQ, 3437 reg: regInfo{ 3438 clobbers: 1, // AX 3439 outputs: []outputInfo{ 3440 {0, 238}, // CX DX BX BP SI DI 3441 }, 3442 }, 3443 }, 3444 { 3445 name: "SETNEF", 3446 argLen: 1, 3447 clobberFlags: true, 3448 asm: x86.ASETNE, 3449 reg: regInfo{ 3450 clobbers: 1, // AX 3451 outputs: []outputInfo{ 3452 {0, 238}, // CX DX BX BP SI DI 3453 }, 3454 }, 3455 }, 3456 { 3457 name: "SETORD", 3458 argLen: 1, 3459 asm: x86.ASETPC, 3460 reg: regInfo{ 3461 outputs: []outputInfo{ 3462 {0, 239}, // AX CX DX BX BP SI DI 3463 }, 3464 }, 3465 }, 3466 { 3467 name: "SETNAN", 3468 argLen: 1, 3469 asm: x86.ASETPS, 3470 reg: regInfo{ 3471 outputs: []outputInfo{ 3472 {0, 239}, // AX CX DX BX BP SI DI 3473 }, 3474 }, 3475 }, 3476 { 3477 name: "SETGF", 3478 argLen: 1, 3479 asm: x86.ASETHI, 3480 reg: regInfo{ 3481 outputs: []outputInfo{ 3482 {0, 239}, // AX CX DX BX BP SI DI 3483 }, 3484 }, 3485 }, 3486 { 3487 name: "SETGEF", 3488 argLen: 1, 3489 asm: x86.ASETCC, 3490 reg: regInfo{ 3491 outputs: []outputInfo{ 3492 {0, 239}, // AX CX DX BX BP SI DI 3493 }, 3494 }, 3495 }, 3496 { 3497 name: "MOVBLSX", 3498 argLen: 1, 3499 asm: x86.AMOVBLSX, 3500 reg: regInfo{ 3501 inputs: []inputInfo{ 3502 {0, 239}, // AX CX DX BX BP SI DI 3503 }, 3504 outputs: []outputInfo{ 3505 {0, 239}, // AX CX DX BX BP SI DI 3506 }, 3507 }, 3508 }, 3509 { 3510 name: "MOVBLZX", 3511 argLen: 1, 3512 asm: x86.AMOVBLZX, 3513 reg: regInfo{ 3514 inputs: []inputInfo{ 3515 {0, 239}, // AX CX DX BX BP SI DI 3516 }, 3517 outputs: []outputInfo{ 3518 {0, 239}, // AX CX DX BX BP SI DI 3519 }, 3520 }, 3521 }, 3522 { 3523 name: "MOVWLSX", 3524 argLen: 1, 3525 asm: x86.AMOVWLSX, 3526 reg: regInfo{ 3527 inputs: []inputInfo{ 3528 {0, 239}, // AX CX DX BX BP SI DI 3529 }, 3530 outputs: []outputInfo{ 3531 {0, 239}, // AX CX DX BX BP SI DI 3532 }, 3533 }, 3534 }, 3535 { 3536 name: "MOVWLZX", 3537 argLen: 1, 3538 asm: x86.AMOVWLZX, 3539 reg: regInfo{ 3540 inputs: []inputInfo{ 3541 {0, 239}, // AX CX DX BX BP SI DI 3542 }, 3543 outputs: []outputInfo{ 3544 {0, 239}, // AX CX DX BX BP SI DI 3545 }, 3546 }, 3547 }, 3548 { 3549 name: "MOVLconst", 3550 auxType: auxInt32, 3551 argLen: 0, 3552 rematerializeable: true, 3553 asm: x86.AMOVL, 3554 reg: regInfo{ 3555 outputs: []outputInfo{ 3556 {0, 239}, // AX CX DX BX BP SI DI 3557 }, 3558 }, 3559 }, 3560 { 3561 name: "CVTTSD2SL", 3562 argLen: 1, 3563 usesScratch: true, 3564 asm: x86.ACVTTSD2SL, 3565 reg: regInfo{ 3566 inputs: []inputInfo{ 3567 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3568 }, 3569 outputs: []outputInfo{ 3570 {0, 239}, // AX CX DX BX BP SI DI 3571 }, 3572 }, 3573 }, 3574 { 3575 name: "CVTTSS2SL", 3576 argLen: 1, 3577 usesScratch: true, 3578 asm: x86.ACVTTSS2SL, 3579 reg: regInfo{ 3580 inputs: []inputInfo{ 3581 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3582 }, 3583 outputs: []outputInfo{ 3584 {0, 239}, // AX CX DX BX BP SI DI 3585 }, 3586 }, 3587 }, 3588 { 3589 name: "CVTSL2SS", 3590 argLen: 1, 3591 usesScratch: true, 3592 asm: x86.ACVTSL2SS, 3593 reg: regInfo{ 3594 inputs: []inputInfo{ 3595 {0, 239}, // AX CX DX BX BP SI DI 3596 }, 3597 outputs: []outputInfo{ 3598 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3599 }, 3600 }, 3601 }, 3602 { 3603 name: "CVTSL2SD", 3604 argLen: 1, 3605 usesScratch: true, 3606 asm: x86.ACVTSL2SD, 3607 reg: regInfo{ 3608 inputs: []inputInfo{ 3609 {0, 239}, // AX CX DX BX BP SI DI 3610 }, 3611 outputs: []outputInfo{ 3612 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3613 }, 3614 }, 3615 }, 3616 { 3617 name: "CVTSD2SS", 3618 argLen: 1, 3619 usesScratch: true, 3620 asm: x86.ACVTSD2SS, 3621 reg: regInfo{ 3622 inputs: []inputInfo{ 3623 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3624 }, 3625 outputs: []outputInfo{ 3626 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3627 }, 3628 }, 3629 }, 3630 { 3631 name: "CVTSS2SD", 3632 argLen: 1, 3633 asm: x86.ACVTSS2SD, 3634 reg: regInfo{ 3635 inputs: []inputInfo{ 3636 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3637 }, 3638 outputs: []outputInfo{ 3639 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3640 }, 3641 }, 3642 }, 3643 { 3644 name: "PXOR", 3645 argLen: 2, 3646 commutative: true, 3647 resultInArg0: true, 3648 asm: x86.APXOR, 3649 reg: regInfo{ 3650 inputs: []inputInfo{ 3651 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3652 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3653 }, 3654 outputs: []outputInfo{ 3655 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3656 }, 3657 }, 3658 }, 3659 { 3660 name: "LEAL", 3661 auxType: auxSymOff, 3662 argLen: 1, 3663 rematerializeable: true, 3664 reg: regInfo{ 3665 inputs: []inputInfo{ 3666 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3667 }, 3668 outputs: []outputInfo{ 3669 {0, 239}, // AX CX DX BX BP SI DI 3670 }, 3671 }, 3672 }, 3673 { 3674 name: "LEAL1", 3675 auxType: auxSymOff, 3676 argLen: 2, 3677 reg: regInfo{ 3678 inputs: []inputInfo{ 3679 {1, 255}, // AX CX DX BX SP BP SI DI 3680 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3681 }, 3682 outputs: []outputInfo{ 3683 {0, 239}, // AX CX DX BX BP SI DI 3684 }, 3685 }, 3686 }, 3687 { 3688 name: "LEAL2", 3689 auxType: auxSymOff, 3690 argLen: 2, 3691 reg: regInfo{ 3692 inputs: []inputInfo{ 3693 {1, 255}, // AX CX DX BX SP BP SI DI 3694 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3695 }, 3696 outputs: []outputInfo{ 3697 {0, 239}, // AX CX DX BX BP SI DI 3698 }, 3699 }, 3700 }, 3701 { 3702 name: "LEAL4", 3703 auxType: auxSymOff, 3704 argLen: 2, 3705 reg: regInfo{ 3706 inputs: []inputInfo{ 3707 {1, 255}, // AX CX DX BX SP BP SI DI 3708 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3709 }, 3710 outputs: []outputInfo{ 3711 {0, 239}, // AX CX DX BX BP SI DI 3712 }, 3713 }, 3714 }, 3715 { 3716 name: "LEAL8", 3717 auxType: auxSymOff, 3718 argLen: 2, 3719 reg: regInfo{ 3720 inputs: []inputInfo{ 3721 {1, 255}, // AX CX DX BX SP BP SI DI 3722 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3723 }, 3724 outputs: []outputInfo{ 3725 {0, 239}, // AX CX DX BX BP SI DI 3726 }, 3727 }, 3728 }, 3729 { 3730 name: "MOVBload", 3731 auxType: auxSymOff, 3732 argLen: 2, 3733 faultOnNilArg0: true, 3734 asm: x86.AMOVBLZX, 3735 reg: regInfo{ 3736 inputs: []inputInfo{ 3737 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3738 }, 3739 outputs: []outputInfo{ 3740 {0, 239}, // AX CX DX BX BP SI DI 3741 }, 3742 }, 3743 }, 3744 { 3745 name: "MOVBLSXload", 3746 auxType: auxSymOff, 3747 argLen: 2, 3748 faultOnNilArg0: true, 3749 asm: x86.AMOVBLSX, 3750 reg: regInfo{ 3751 inputs: []inputInfo{ 3752 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3753 }, 3754 outputs: []outputInfo{ 3755 {0, 239}, // AX CX DX BX BP SI DI 3756 }, 3757 }, 3758 }, 3759 { 3760 name: "MOVWload", 3761 auxType: auxSymOff, 3762 argLen: 2, 3763 faultOnNilArg0: true, 3764 asm: x86.AMOVWLZX, 3765 reg: regInfo{ 3766 inputs: []inputInfo{ 3767 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3768 }, 3769 outputs: []outputInfo{ 3770 {0, 239}, // AX CX DX BX BP SI DI 3771 }, 3772 }, 3773 }, 3774 { 3775 name: "MOVWLSXload", 3776 auxType: auxSymOff, 3777 argLen: 2, 3778 faultOnNilArg0: true, 3779 asm: x86.AMOVWLSX, 3780 reg: regInfo{ 3781 inputs: []inputInfo{ 3782 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3783 }, 3784 outputs: []outputInfo{ 3785 {0, 239}, // AX CX DX BX BP SI DI 3786 }, 3787 }, 3788 }, 3789 { 3790 name: "MOVLload", 3791 auxType: auxSymOff, 3792 argLen: 2, 3793 faultOnNilArg0: true, 3794 asm: x86.AMOVL, 3795 reg: regInfo{ 3796 inputs: []inputInfo{ 3797 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3798 }, 3799 outputs: []outputInfo{ 3800 {0, 239}, // AX CX DX BX BP SI DI 3801 }, 3802 }, 3803 }, 3804 { 3805 name: "MOVBstore", 3806 auxType: auxSymOff, 3807 argLen: 3, 3808 faultOnNilArg0: true, 3809 asm: x86.AMOVB, 3810 reg: regInfo{ 3811 inputs: []inputInfo{ 3812 {1, 255}, // AX CX DX BX SP BP SI DI 3813 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3814 }, 3815 }, 3816 }, 3817 { 3818 name: "MOVWstore", 3819 auxType: auxSymOff, 3820 argLen: 3, 3821 faultOnNilArg0: true, 3822 asm: x86.AMOVW, 3823 reg: regInfo{ 3824 inputs: []inputInfo{ 3825 {1, 255}, // AX CX DX BX SP BP SI DI 3826 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3827 }, 3828 }, 3829 }, 3830 { 3831 name: "MOVLstore", 3832 auxType: auxSymOff, 3833 argLen: 3, 3834 faultOnNilArg0: true, 3835 asm: x86.AMOVL, 3836 reg: regInfo{ 3837 inputs: []inputInfo{ 3838 {1, 255}, // AX CX DX BX SP BP SI DI 3839 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3840 }, 3841 }, 3842 }, 3843 { 3844 name: "MOVBloadidx1", 3845 auxType: auxSymOff, 3846 argLen: 3, 3847 asm: x86.AMOVBLZX, 3848 reg: regInfo{ 3849 inputs: []inputInfo{ 3850 {1, 255}, // AX CX DX BX SP BP SI DI 3851 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3852 }, 3853 outputs: []outputInfo{ 3854 {0, 239}, // AX CX DX BX BP SI DI 3855 }, 3856 }, 3857 }, 3858 { 3859 name: "MOVWloadidx1", 3860 auxType: auxSymOff, 3861 argLen: 3, 3862 asm: x86.AMOVWLZX, 3863 reg: regInfo{ 3864 inputs: []inputInfo{ 3865 {1, 255}, // AX CX DX BX SP BP SI DI 3866 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3867 }, 3868 outputs: []outputInfo{ 3869 {0, 239}, // AX CX DX BX BP SI DI 3870 }, 3871 }, 3872 }, 3873 { 3874 name: "MOVWloadidx2", 3875 auxType: auxSymOff, 3876 argLen: 3, 3877 asm: x86.AMOVWLZX, 3878 reg: regInfo{ 3879 inputs: []inputInfo{ 3880 {1, 255}, // AX CX DX BX SP BP SI DI 3881 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3882 }, 3883 outputs: []outputInfo{ 3884 {0, 239}, // AX CX DX BX BP SI DI 3885 }, 3886 }, 3887 }, 3888 { 3889 name: "MOVLloadidx1", 3890 auxType: auxSymOff, 3891 argLen: 3, 3892 asm: x86.AMOVL, 3893 reg: regInfo{ 3894 inputs: []inputInfo{ 3895 {1, 255}, // AX CX DX BX SP BP SI DI 3896 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3897 }, 3898 outputs: []outputInfo{ 3899 {0, 239}, // AX CX DX BX BP SI DI 3900 }, 3901 }, 3902 }, 3903 { 3904 name: "MOVLloadidx4", 3905 auxType: auxSymOff, 3906 argLen: 3, 3907 asm: x86.AMOVL, 3908 reg: regInfo{ 3909 inputs: []inputInfo{ 3910 {1, 255}, // AX CX DX BX SP BP SI DI 3911 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3912 }, 3913 outputs: []outputInfo{ 3914 {0, 239}, // AX CX DX BX BP SI DI 3915 }, 3916 }, 3917 }, 3918 { 3919 name: "MOVBstoreidx1", 3920 auxType: auxSymOff, 3921 argLen: 4, 3922 asm: x86.AMOVB, 3923 reg: regInfo{ 3924 inputs: []inputInfo{ 3925 {1, 255}, // AX CX DX BX SP BP SI DI 3926 {2, 255}, // AX CX DX BX SP BP SI DI 3927 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3928 }, 3929 }, 3930 }, 3931 { 3932 name: "MOVWstoreidx1", 3933 auxType: auxSymOff, 3934 argLen: 4, 3935 asm: x86.AMOVW, 3936 reg: regInfo{ 3937 inputs: []inputInfo{ 3938 {1, 255}, // AX CX DX BX SP BP SI DI 3939 {2, 255}, // AX CX DX BX SP BP SI DI 3940 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3941 }, 3942 }, 3943 }, 3944 { 3945 name: "MOVWstoreidx2", 3946 auxType: auxSymOff, 3947 argLen: 4, 3948 asm: x86.AMOVW, 3949 reg: regInfo{ 3950 inputs: []inputInfo{ 3951 {1, 255}, // AX CX DX BX SP BP SI DI 3952 {2, 255}, // AX CX DX BX SP BP SI DI 3953 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3954 }, 3955 }, 3956 }, 3957 { 3958 name: "MOVLstoreidx1", 3959 auxType: auxSymOff, 3960 argLen: 4, 3961 asm: x86.AMOVL, 3962 reg: regInfo{ 3963 inputs: []inputInfo{ 3964 {1, 255}, // AX CX DX BX SP BP SI DI 3965 {2, 255}, // AX CX DX BX SP BP SI DI 3966 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3967 }, 3968 }, 3969 }, 3970 { 3971 name: "MOVLstoreidx4", 3972 auxType: auxSymOff, 3973 argLen: 4, 3974 asm: x86.AMOVL, 3975 reg: regInfo{ 3976 inputs: []inputInfo{ 3977 {1, 255}, // AX CX DX BX SP BP SI DI 3978 {2, 255}, // AX CX DX BX SP BP SI DI 3979 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3980 }, 3981 }, 3982 }, 3983 { 3984 name: "MOVBstoreconst", 3985 auxType: auxSymValAndOff, 3986 argLen: 2, 3987 faultOnNilArg0: true, 3988 asm: x86.AMOVB, 3989 reg: regInfo{ 3990 inputs: []inputInfo{ 3991 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3992 }, 3993 }, 3994 }, 3995 { 3996 name: "MOVWstoreconst", 3997 auxType: auxSymValAndOff, 3998 argLen: 2, 3999 faultOnNilArg0: true, 4000 asm: x86.AMOVW, 4001 reg: regInfo{ 4002 inputs: []inputInfo{ 4003 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4004 }, 4005 }, 4006 }, 4007 { 4008 name: "MOVLstoreconst", 4009 auxType: auxSymValAndOff, 4010 argLen: 2, 4011 faultOnNilArg0: true, 4012 asm: x86.AMOVL, 4013 reg: regInfo{ 4014 inputs: []inputInfo{ 4015 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4016 }, 4017 }, 4018 }, 4019 { 4020 name: "MOVBstoreconstidx1", 4021 auxType: auxSymValAndOff, 4022 argLen: 3, 4023 asm: x86.AMOVB, 4024 reg: regInfo{ 4025 inputs: []inputInfo{ 4026 {1, 255}, // AX CX DX BX SP BP SI DI 4027 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4028 }, 4029 }, 4030 }, 4031 { 4032 name: "MOVWstoreconstidx1", 4033 auxType: auxSymValAndOff, 4034 argLen: 3, 4035 asm: x86.AMOVW, 4036 reg: regInfo{ 4037 inputs: []inputInfo{ 4038 {1, 255}, // AX CX DX BX SP BP SI DI 4039 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4040 }, 4041 }, 4042 }, 4043 { 4044 name: "MOVWstoreconstidx2", 4045 auxType: auxSymValAndOff, 4046 argLen: 3, 4047 asm: x86.AMOVW, 4048 reg: regInfo{ 4049 inputs: []inputInfo{ 4050 {1, 255}, // AX CX DX BX SP BP SI DI 4051 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4052 }, 4053 }, 4054 }, 4055 { 4056 name: "MOVLstoreconstidx1", 4057 auxType: auxSymValAndOff, 4058 argLen: 3, 4059 asm: x86.AMOVL, 4060 reg: regInfo{ 4061 inputs: []inputInfo{ 4062 {1, 255}, // AX CX DX BX SP BP SI DI 4063 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4064 }, 4065 }, 4066 }, 4067 { 4068 name: "MOVLstoreconstidx4", 4069 auxType: auxSymValAndOff, 4070 argLen: 3, 4071 asm: x86.AMOVL, 4072 reg: regInfo{ 4073 inputs: []inputInfo{ 4074 {1, 255}, // AX CX DX BX SP BP SI DI 4075 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4076 }, 4077 }, 4078 }, 4079 { 4080 name: "DUFFZERO", 4081 auxType: auxInt64, 4082 argLen: 3, 4083 reg: regInfo{ 4084 inputs: []inputInfo{ 4085 {0, 128}, // DI 4086 {1, 1}, // AX 4087 }, 4088 clobbers: 130, // CX DI 4089 }, 4090 }, 4091 { 4092 name: "REPSTOSL", 4093 argLen: 4, 4094 reg: regInfo{ 4095 inputs: []inputInfo{ 4096 {0, 128}, // DI 4097 {1, 2}, // CX 4098 {2, 1}, // AX 4099 }, 4100 clobbers: 130, // CX DI 4101 }, 4102 }, 4103 { 4104 name: "CALLstatic", 4105 auxType: auxSymOff, 4106 argLen: 1, 4107 clobberFlags: true, 4108 call: true, 4109 reg: regInfo{ 4110 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4111 }, 4112 }, 4113 { 4114 name: "CALLclosure", 4115 auxType: auxInt64, 4116 argLen: 3, 4117 clobberFlags: true, 4118 call: true, 4119 reg: regInfo{ 4120 inputs: []inputInfo{ 4121 {1, 4}, // DX 4122 {0, 255}, // AX CX DX BX SP BP SI DI 4123 }, 4124 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4125 }, 4126 }, 4127 { 4128 name: "CALLdefer", 4129 auxType: auxInt64, 4130 argLen: 1, 4131 clobberFlags: true, 4132 call: true, 4133 reg: regInfo{ 4134 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4135 }, 4136 }, 4137 { 4138 name: "CALLgo", 4139 auxType: auxInt64, 4140 argLen: 1, 4141 clobberFlags: true, 4142 call: true, 4143 reg: regInfo{ 4144 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4145 }, 4146 }, 4147 { 4148 name: "CALLinter", 4149 auxType: auxInt64, 4150 argLen: 2, 4151 clobberFlags: true, 4152 call: true, 4153 reg: regInfo{ 4154 inputs: []inputInfo{ 4155 {0, 239}, // AX CX DX BX BP SI DI 4156 }, 4157 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4158 }, 4159 }, 4160 { 4161 name: "DUFFCOPY", 4162 auxType: auxInt64, 4163 argLen: 3, 4164 clobberFlags: true, 4165 reg: regInfo{ 4166 inputs: []inputInfo{ 4167 {0, 128}, // DI 4168 {1, 64}, // SI 4169 }, 4170 clobbers: 194, // CX SI DI 4171 }, 4172 }, 4173 { 4174 name: "REPMOVSL", 4175 argLen: 4, 4176 reg: regInfo{ 4177 inputs: []inputInfo{ 4178 {0, 128}, // DI 4179 {1, 64}, // SI 4180 {2, 2}, // CX 4181 }, 4182 clobbers: 194, // CX SI DI 4183 }, 4184 }, 4185 { 4186 name: "InvertFlags", 4187 argLen: 1, 4188 reg: regInfo{}, 4189 }, 4190 { 4191 name: "LoweredGetG", 4192 argLen: 1, 4193 reg: regInfo{ 4194 outputs: []outputInfo{ 4195 {0, 239}, // AX CX DX BX BP SI DI 4196 }, 4197 }, 4198 }, 4199 { 4200 name: "LoweredGetClosurePtr", 4201 argLen: 0, 4202 reg: regInfo{ 4203 outputs: []outputInfo{ 4204 {0, 4}, // DX 4205 }, 4206 }, 4207 }, 4208 { 4209 name: "LoweredNilCheck", 4210 argLen: 2, 4211 clobberFlags: true, 4212 nilCheck: true, 4213 faultOnNilArg0: true, 4214 reg: regInfo{ 4215 inputs: []inputInfo{ 4216 {0, 255}, // AX CX DX BX SP BP SI DI 4217 }, 4218 }, 4219 }, 4220 { 4221 name: "MOVLconvert", 4222 argLen: 2, 4223 asm: x86.AMOVL, 4224 reg: regInfo{ 4225 inputs: []inputInfo{ 4226 {0, 239}, // AX CX DX BX BP SI DI 4227 }, 4228 outputs: []outputInfo{ 4229 {0, 239}, // AX CX DX BX BP SI DI 4230 }, 4231 }, 4232 }, 4233 { 4234 name: "FlagEQ", 4235 argLen: 0, 4236 reg: regInfo{}, 4237 }, 4238 { 4239 name: "FlagLT_ULT", 4240 argLen: 0, 4241 reg: regInfo{}, 4242 }, 4243 { 4244 name: "FlagLT_UGT", 4245 argLen: 0, 4246 reg: regInfo{}, 4247 }, 4248 { 4249 name: "FlagGT_UGT", 4250 argLen: 0, 4251 reg: regInfo{}, 4252 }, 4253 { 4254 name: "FlagGT_ULT", 4255 argLen: 0, 4256 reg: regInfo{}, 4257 }, 4258 { 4259 name: "FCHS", 4260 argLen: 1, 4261 reg: regInfo{ 4262 inputs: []inputInfo{ 4263 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4264 }, 4265 outputs: []outputInfo{ 4266 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4267 }, 4268 }, 4269 }, 4270 { 4271 name: "MOVSSconst1", 4272 auxType: auxFloat32, 4273 argLen: 0, 4274 reg: regInfo{ 4275 outputs: []outputInfo{ 4276 {0, 239}, // AX CX DX BX BP SI DI 4277 }, 4278 }, 4279 }, 4280 { 4281 name: "MOVSDconst1", 4282 auxType: auxFloat64, 4283 argLen: 0, 4284 reg: regInfo{ 4285 outputs: []outputInfo{ 4286 {0, 239}, // AX CX DX BX BP SI DI 4287 }, 4288 }, 4289 }, 4290 { 4291 name: "MOVSSconst2", 4292 argLen: 1, 4293 asm: x86.AMOVSS, 4294 reg: regInfo{ 4295 inputs: []inputInfo{ 4296 {0, 239}, // AX CX DX BX BP SI DI 4297 }, 4298 outputs: []outputInfo{ 4299 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4300 }, 4301 }, 4302 }, 4303 { 4304 name: "MOVSDconst2", 4305 argLen: 1, 4306 asm: x86.AMOVSD, 4307 reg: regInfo{ 4308 inputs: []inputInfo{ 4309 {0, 239}, // AX CX DX BX BP SI DI 4310 }, 4311 outputs: []outputInfo{ 4312 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4313 }, 4314 }, 4315 }, 4316 4317 { 4318 name: "ADDSS", 4319 argLen: 2, 4320 commutative: true, 4321 resultInArg0: true, 4322 asm: x86.AADDSS, 4323 reg: regInfo{ 4324 inputs: []inputInfo{ 4325 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4326 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4327 }, 4328 outputs: []outputInfo{ 4329 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4330 }, 4331 }, 4332 }, 4333 { 4334 name: "ADDSD", 4335 argLen: 2, 4336 commutative: true, 4337 resultInArg0: true, 4338 asm: x86.AADDSD, 4339 reg: regInfo{ 4340 inputs: []inputInfo{ 4341 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4342 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4343 }, 4344 outputs: []outputInfo{ 4345 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4346 }, 4347 }, 4348 }, 4349 { 4350 name: "SUBSS", 4351 argLen: 2, 4352 resultInArg0: true, 4353 asm: x86.ASUBSS, 4354 reg: regInfo{ 4355 inputs: []inputInfo{ 4356 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4357 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4358 }, 4359 outputs: []outputInfo{ 4360 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4361 }, 4362 }, 4363 }, 4364 { 4365 name: "SUBSD", 4366 argLen: 2, 4367 resultInArg0: true, 4368 asm: x86.ASUBSD, 4369 reg: regInfo{ 4370 inputs: []inputInfo{ 4371 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4372 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4373 }, 4374 outputs: []outputInfo{ 4375 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4376 }, 4377 }, 4378 }, 4379 { 4380 name: "MULSS", 4381 argLen: 2, 4382 commutative: true, 4383 resultInArg0: true, 4384 asm: x86.AMULSS, 4385 reg: regInfo{ 4386 inputs: []inputInfo{ 4387 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4388 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4389 }, 4390 outputs: []outputInfo{ 4391 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4392 }, 4393 }, 4394 }, 4395 { 4396 name: "MULSD", 4397 argLen: 2, 4398 commutative: true, 4399 resultInArg0: true, 4400 asm: x86.AMULSD, 4401 reg: regInfo{ 4402 inputs: []inputInfo{ 4403 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4404 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4405 }, 4406 outputs: []outputInfo{ 4407 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4408 }, 4409 }, 4410 }, 4411 { 4412 name: "DIVSS", 4413 argLen: 2, 4414 resultInArg0: true, 4415 asm: x86.ADIVSS, 4416 reg: regInfo{ 4417 inputs: []inputInfo{ 4418 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4419 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4420 }, 4421 outputs: []outputInfo{ 4422 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4423 }, 4424 }, 4425 }, 4426 { 4427 name: "DIVSD", 4428 argLen: 2, 4429 resultInArg0: true, 4430 asm: x86.ADIVSD, 4431 reg: regInfo{ 4432 inputs: []inputInfo{ 4433 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4434 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4435 }, 4436 outputs: []outputInfo{ 4437 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4438 }, 4439 }, 4440 }, 4441 { 4442 name: "MOVSSload", 4443 auxType: auxSymOff, 4444 argLen: 2, 4445 faultOnNilArg0: true, 4446 asm: x86.AMOVSS, 4447 reg: regInfo{ 4448 inputs: []inputInfo{ 4449 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4450 }, 4451 outputs: []outputInfo{ 4452 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4453 }, 4454 }, 4455 }, 4456 { 4457 name: "MOVSDload", 4458 auxType: auxSymOff, 4459 argLen: 2, 4460 faultOnNilArg0: true, 4461 asm: x86.AMOVSD, 4462 reg: regInfo{ 4463 inputs: []inputInfo{ 4464 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4465 }, 4466 outputs: []outputInfo{ 4467 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4468 }, 4469 }, 4470 }, 4471 { 4472 name: "MOVSSconst", 4473 auxType: auxFloat32, 4474 argLen: 0, 4475 rematerializeable: true, 4476 asm: x86.AMOVSS, 4477 reg: regInfo{ 4478 outputs: []outputInfo{ 4479 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4480 }, 4481 }, 4482 }, 4483 { 4484 name: "MOVSDconst", 4485 auxType: auxFloat64, 4486 argLen: 0, 4487 rematerializeable: true, 4488 asm: x86.AMOVSD, 4489 reg: regInfo{ 4490 outputs: []outputInfo{ 4491 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4492 }, 4493 }, 4494 }, 4495 { 4496 name: "MOVSSloadidx1", 4497 auxType: auxSymOff, 4498 argLen: 3, 4499 asm: x86.AMOVSS, 4500 reg: regInfo{ 4501 inputs: []inputInfo{ 4502 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4503 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4504 }, 4505 outputs: []outputInfo{ 4506 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4507 }, 4508 }, 4509 }, 4510 { 4511 name: "MOVSSloadidx4", 4512 auxType: auxSymOff, 4513 argLen: 3, 4514 asm: x86.AMOVSS, 4515 reg: regInfo{ 4516 inputs: []inputInfo{ 4517 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4518 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4519 }, 4520 outputs: []outputInfo{ 4521 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4522 }, 4523 }, 4524 }, 4525 { 4526 name: "MOVSDloadidx1", 4527 auxType: auxSymOff, 4528 argLen: 3, 4529 asm: x86.AMOVSD, 4530 reg: regInfo{ 4531 inputs: []inputInfo{ 4532 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4533 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4534 }, 4535 outputs: []outputInfo{ 4536 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4537 }, 4538 }, 4539 }, 4540 { 4541 name: "MOVSDloadidx8", 4542 auxType: auxSymOff, 4543 argLen: 3, 4544 asm: x86.AMOVSD, 4545 reg: regInfo{ 4546 inputs: []inputInfo{ 4547 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4548 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4549 }, 4550 outputs: []outputInfo{ 4551 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4552 }, 4553 }, 4554 }, 4555 { 4556 name: "MOVSSstore", 4557 auxType: auxSymOff, 4558 argLen: 3, 4559 faultOnNilArg0: true, 4560 asm: x86.AMOVSS, 4561 reg: regInfo{ 4562 inputs: []inputInfo{ 4563 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4564 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4565 }, 4566 }, 4567 }, 4568 { 4569 name: "MOVSDstore", 4570 auxType: auxSymOff, 4571 argLen: 3, 4572 faultOnNilArg0: true, 4573 asm: x86.AMOVSD, 4574 reg: regInfo{ 4575 inputs: []inputInfo{ 4576 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4577 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4578 }, 4579 }, 4580 }, 4581 { 4582 name: "MOVSSstoreidx1", 4583 auxType: auxSymOff, 4584 argLen: 4, 4585 asm: x86.AMOVSS, 4586 reg: regInfo{ 4587 inputs: []inputInfo{ 4588 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4589 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4590 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4591 }, 4592 }, 4593 }, 4594 { 4595 name: "MOVSSstoreidx4", 4596 auxType: auxSymOff, 4597 argLen: 4, 4598 asm: x86.AMOVSS, 4599 reg: regInfo{ 4600 inputs: []inputInfo{ 4601 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4602 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4603 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4604 }, 4605 }, 4606 }, 4607 { 4608 name: "MOVSDstoreidx1", 4609 auxType: auxSymOff, 4610 argLen: 4, 4611 asm: x86.AMOVSD, 4612 reg: regInfo{ 4613 inputs: []inputInfo{ 4614 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4615 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4616 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4617 }, 4618 }, 4619 }, 4620 { 4621 name: "MOVSDstoreidx8", 4622 auxType: auxSymOff, 4623 argLen: 4, 4624 asm: x86.AMOVSD, 4625 reg: regInfo{ 4626 inputs: []inputInfo{ 4627 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4628 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4629 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4630 }, 4631 }, 4632 }, 4633 { 4634 name: "ADDQ", 4635 argLen: 2, 4636 commutative: true, 4637 clobberFlags: true, 4638 asm: x86.AADDQ, 4639 reg: regInfo{ 4640 inputs: []inputInfo{ 4641 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4642 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4643 }, 4644 outputs: []outputInfo{ 4645 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4646 }, 4647 }, 4648 }, 4649 { 4650 name: "ADDL", 4651 argLen: 2, 4652 commutative: true, 4653 clobberFlags: true, 4654 asm: x86.AADDL, 4655 reg: regInfo{ 4656 inputs: []inputInfo{ 4657 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4658 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4659 }, 4660 outputs: []outputInfo{ 4661 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4662 }, 4663 }, 4664 }, 4665 { 4666 name: "ADDQconst", 4667 auxType: auxInt64, 4668 argLen: 1, 4669 clobberFlags: true, 4670 asm: x86.AADDQ, 4671 reg: regInfo{ 4672 inputs: []inputInfo{ 4673 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4674 }, 4675 outputs: []outputInfo{ 4676 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4677 }, 4678 }, 4679 }, 4680 { 4681 name: "ADDLconst", 4682 auxType: auxInt32, 4683 argLen: 1, 4684 clobberFlags: true, 4685 asm: x86.AADDL, 4686 reg: regInfo{ 4687 inputs: []inputInfo{ 4688 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4689 }, 4690 outputs: []outputInfo{ 4691 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4692 }, 4693 }, 4694 }, 4695 { 4696 name: "SUBQ", 4697 argLen: 2, 4698 resultInArg0: true, 4699 clobberFlags: true, 4700 asm: x86.ASUBQ, 4701 reg: regInfo{ 4702 inputs: []inputInfo{ 4703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4704 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4705 }, 4706 outputs: []outputInfo{ 4707 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4708 }, 4709 }, 4710 }, 4711 { 4712 name: "SUBL", 4713 argLen: 2, 4714 resultInArg0: true, 4715 clobberFlags: true, 4716 asm: x86.ASUBL, 4717 reg: regInfo{ 4718 inputs: []inputInfo{ 4719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4720 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4721 }, 4722 outputs: []outputInfo{ 4723 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4724 }, 4725 }, 4726 }, 4727 { 4728 name: "SUBQconst", 4729 auxType: auxInt64, 4730 argLen: 1, 4731 resultInArg0: true, 4732 clobberFlags: true, 4733 asm: x86.ASUBQ, 4734 reg: regInfo{ 4735 inputs: []inputInfo{ 4736 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4737 }, 4738 outputs: []outputInfo{ 4739 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4740 }, 4741 }, 4742 }, 4743 { 4744 name: "SUBLconst", 4745 auxType: auxInt32, 4746 argLen: 1, 4747 resultInArg0: true, 4748 clobberFlags: true, 4749 asm: x86.ASUBL, 4750 reg: regInfo{ 4751 inputs: []inputInfo{ 4752 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4753 }, 4754 outputs: []outputInfo{ 4755 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4756 }, 4757 }, 4758 }, 4759 { 4760 name: "MULQ", 4761 argLen: 2, 4762 commutative: true, 4763 resultInArg0: true, 4764 clobberFlags: true, 4765 asm: x86.AIMULQ, 4766 reg: regInfo{ 4767 inputs: []inputInfo{ 4768 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4769 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4770 }, 4771 outputs: []outputInfo{ 4772 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4773 }, 4774 }, 4775 }, 4776 { 4777 name: "MULL", 4778 argLen: 2, 4779 commutative: true, 4780 resultInArg0: true, 4781 clobberFlags: true, 4782 asm: x86.AIMULL, 4783 reg: regInfo{ 4784 inputs: []inputInfo{ 4785 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4786 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4787 }, 4788 outputs: []outputInfo{ 4789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4790 }, 4791 }, 4792 }, 4793 { 4794 name: "MULQconst", 4795 auxType: auxInt64, 4796 argLen: 1, 4797 resultInArg0: true, 4798 clobberFlags: true, 4799 asm: x86.AIMULQ, 4800 reg: regInfo{ 4801 inputs: []inputInfo{ 4802 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4803 }, 4804 outputs: []outputInfo{ 4805 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4806 }, 4807 }, 4808 }, 4809 { 4810 name: "MULLconst", 4811 auxType: auxInt32, 4812 argLen: 1, 4813 resultInArg0: true, 4814 clobberFlags: true, 4815 asm: x86.AIMULL, 4816 reg: regInfo{ 4817 inputs: []inputInfo{ 4818 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4819 }, 4820 outputs: []outputInfo{ 4821 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4822 }, 4823 }, 4824 }, 4825 { 4826 name: "HMULQ", 4827 argLen: 2, 4828 clobberFlags: true, 4829 asm: x86.AIMULQ, 4830 reg: regInfo{ 4831 inputs: []inputInfo{ 4832 {0, 1}, // AX 4833 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4834 }, 4835 clobbers: 1, // AX 4836 outputs: []outputInfo{ 4837 {0, 4}, // DX 4838 }, 4839 }, 4840 }, 4841 { 4842 name: "HMULL", 4843 argLen: 2, 4844 clobberFlags: true, 4845 asm: x86.AIMULL, 4846 reg: regInfo{ 4847 inputs: []inputInfo{ 4848 {0, 1}, // AX 4849 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4850 }, 4851 clobbers: 1, // AX 4852 outputs: []outputInfo{ 4853 {0, 4}, // DX 4854 }, 4855 }, 4856 }, 4857 { 4858 name: "HMULW", 4859 argLen: 2, 4860 clobberFlags: true, 4861 asm: x86.AIMULW, 4862 reg: regInfo{ 4863 inputs: []inputInfo{ 4864 {0, 1}, // AX 4865 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4866 }, 4867 clobbers: 1, // AX 4868 outputs: []outputInfo{ 4869 {0, 4}, // DX 4870 }, 4871 }, 4872 }, 4873 { 4874 name: "HMULB", 4875 argLen: 2, 4876 clobberFlags: true, 4877 asm: x86.AIMULB, 4878 reg: regInfo{ 4879 inputs: []inputInfo{ 4880 {0, 1}, // AX 4881 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4882 }, 4883 clobbers: 1, // AX 4884 outputs: []outputInfo{ 4885 {0, 4}, // DX 4886 }, 4887 }, 4888 }, 4889 { 4890 name: "HMULQU", 4891 argLen: 2, 4892 clobberFlags: true, 4893 asm: x86.AMULQ, 4894 reg: regInfo{ 4895 inputs: []inputInfo{ 4896 {0, 1}, // AX 4897 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4898 }, 4899 clobbers: 1, // AX 4900 outputs: []outputInfo{ 4901 {0, 4}, // DX 4902 }, 4903 }, 4904 }, 4905 { 4906 name: "HMULLU", 4907 argLen: 2, 4908 clobberFlags: true, 4909 asm: x86.AMULL, 4910 reg: regInfo{ 4911 inputs: []inputInfo{ 4912 {0, 1}, // AX 4913 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4914 }, 4915 clobbers: 1, // AX 4916 outputs: []outputInfo{ 4917 {0, 4}, // DX 4918 }, 4919 }, 4920 }, 4921 { 4922 name: "HMULWU", 4923 argLen: 2, 4924 clobberFlags: true, 4925 asm: x86.AMULW, 4926 reg: regInfo{ 4927 inputs: []inputInfo{ 4928 {0, 1}, // AX 4929 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4930 }, 4931 clobbers: 1, // AX 4932 outputs: []outputInfo{ 4933 {0, 4}, // DX 4934 }, 4935 }, 4936 }, 4937 { 4938 name: "HMULBU", 4939 argLen: 2, 4940 clobberFlags: true, 4941 asm: x86.AMULB, 4942 reg: regInfo{ 4943 inputs: []inputInfo{ 4944 {0, 1}, // AX 4945 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4946 }, 4947 clobbers: 1, // AX 4948 outputs: []outputInfo{ 4949 {0, 4}, // DX 4950 }, 4951 }, 4952 }, 4953 { 4954 name: "AVGQU", 4955 argLen: 2, 4956 commutative: true, 4957 resultInArg0: true, 4958 clobberFlags: true, 4959 reg: regInfo{ 4960 inputs: []inputInfo{ 4961 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4962 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4963 }, 4964 outputs: []outputInfo{ 4965 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4966 }, 4967 }, 4968 }, 4969 { 4970 name: "DIVQ", 4971 argLen: 2, 4972 clobberFlags: true, 4973 asm: x86.AIDIVQ, 4974 reg: regInfo{ 4975 inputs: []inputInfo{ 4976 {0, 1}, // AX 4977 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4978 }, 4979 outputs: []outputInfo{ 4980 {0, 1}, // AX 4981 {1, 4}, // DX 4982 }, 4983 }, 4984 }, 4985 { 4986 name: "DIVL", 4987 argLen: 2, 4988 clobberFlags: true, 4989 asm: x86.AIDIVL, 4990 reg: regInfo{ 4991 inputs: []inputInfo{ 4992 {0, 1}, // AX 4993 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4994 }, 4995 outputs: []outputInfo{ 4996 {0, 1}, // AX 4997 {1, 4}, // DX 4998 }, 4999 }, 5000 }, 5001 { 5002 name: "DIVW", 5003 argLen: 2, 5004 clobberFlags: true, 5005 asm: x86.AIDIVW, 5006 reg: regInfo{ 5007 inputs: []inputInfo{ 5008 {0, 1}, // AX 5009 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5010 }, 5011 outputs: []outputInfo{ 5012 {0, 1}, // AX 5013 {1, 4}, // DX 5014 }, 5015 }, 5016 }, 5017 { 5018 name: "DIVQU", 5019 argLen: 2, 5020 clobberFlags: true, 5021 asm: x86.ADIVQ, 5022 reg: regInfo{ 5023 inputs: []inputInfo{ 5024 {0, 1}, // AX 5025 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5026 }, 5027 outputs: []outputInfo{ 5028 {0, 1}, // AX 5029 {1, 4}, // DX 5030 }, 5031 }, 5032 }, 5033 { 5034 name: "DIVLU", 5035 argLen: 2, 5036 clobberFlags: true, 5037 asm: x86.ADIVL, 5038 reg: regInfo{ 5039 inputs: []inputInfo{ 5040 {0, 1}, // AX 5041 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5042 }, 5043 outputs: []outputInfo{ 5044 {0, 1}, // AX 5045 {1, 4}, // DX 5046 }, 5047 }, 5048 }, 5049 { 5050 name: "DIVWU", 5051 argLen: 2, 5052 clobberFlags: true, 5053 asm: x86.ADIVW, 5054 reg: regInfo{ 5055 inputs: []inputInfo{ 5056 {0, 1}, // AX 5057 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5058 }, 5059 outputs: []outputInfo{ 5060 {0, 1}, // AX 5061 {1, 4}, // DX 5062 }, 5063 }, 5064 }, 5065 { 5066 name: "MULQU2", 5067 argLen: 2, 5068 clobberFlags: true, 5069 asm: x86.AMULQ, 5070 reg: regInfo{ 5071 inputs: []inputInfo{ 5072 {0, 1}, // AX 5073 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5074 }, 5075 outputs: []outputInfo{ 5076 {0, 4}, // DX 5077 {1, 1}, // AX 5078 }, 5079 }, 5080 }, 5081 { 5082 name: "DIVQU2", 5083 argLen: 3, 5084 clobberFlags: true, 5085 asm: x86.ADIVQ, 5086 reg: regInfo{ 5087 inputs: []inputInfo{ 5088 {0, 4}, // DX 5089 {1, 1}, // AX 5090 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5091 }, 5092 outputs: []outputInfo{ 5093 {0, 1}, // AX 5094 {1, 4}, // DX 5095 }, 5096 }, 5097 }, 5098 { 5099 name: "ANDQ", 5100 argLen: 2, 5101 commutative: true, 5102 resultInArg0: true, 5103 clobberFlags: true, 5104 asm: x86.AANDQ, 5105 reg: regInfo{ 5106 inputs: []inputInfo{ 5107 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5108 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5109 }, 5110 outputs: []outputInfo{ 5111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5112 }, 5113 }, 5114 }, 5115 { 5116 name: "ANDL", 5117 argLen: 2, 5118 commutative: true, 5119 resultInArg0: true, 5120 clobberFlags: true, 5121 asm: x86.AANDL, 5122 reg: regInfo{ 5123 inputs: []inputInfo{ 5124 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5125 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5126 }, 5127 outputs: []outputInfo{ 5128 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5129 }, 5130 }, 5131 }, 5132 { 5133 name: "ANDQconst", 5134 auxType: auxInt64, 5135 argLen: 1, 5136 resultInArg0: true, 5137 clobberFlags: true, 5138 asm: x86.AANDQ, 5139 reg: regInfo{ 5140 inputs: []inputInfo{ 5141 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5142 }, 5143 outputs: []outputInfo{ 5144 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5145 }, 5146 }, 5147 }, 5148 { 5149 name: "ANDLconst", 5150 auxType: auxInt32, 5151 argLen: 1, 5152 resultInArg0: true, 5153 clobberFlags: true, 5154 asm: x86.AANDL, 5155 reg: regInfo{ 5156 inputs: []inputInfo{ 5157 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5158 }, 5159 outputs: []outputInfo{ 5160 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5161 }, 5162 }, 5163 }, 5164 { 5165 name: "ORQ", 5166 argLen: 2, 5167 commutative: true, 5168 resultInArg0: true, 5169 clobberFlags: true, 5170 asm: x86.AORQ, 5171 reg: regInfo{ 5172 inputs: []inputInfo{ 5173 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5174 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5175 }, 5176 outputs: []outputInfo{ 5177 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5178 }, 5179 }, 5180 }, 5181 { 5182 name: "ORL", 5183 argLen: 2, 5184 commutative: true, 5185 resultInArg0: true, 5186 clobberFlags: true, 5187 asm: x86.AORL, 5188 reg: regInfo{ 5189 inputs: []inputInfo{ 5190 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5191 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5192 }, 5193 outputs: []outputInfo{ 5194 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5195 }, 5196 }, 5197 }, 5198 { 5199 name: "ORQconst", 5200 auxType: auxInt64, 5201 argLen: 1, 5202 resultInArg0: true, 5203 clobberFlags: true, 5204 asm: x86.AORQ, 5205 reg: regInfo{ 5206 inputs: []inputInfo{ 5207 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5208 }, 5209 outputs: []outputInfo{ 5210 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5211 }, 5212 }, 5213 }, 5214 { 5215 name: "ORLconst", 5216 auxType: auxInt32, 5217 argLen: 1, 5218 resultInArg0: true, 5219 clobberFlags: true, 5220 asm: x86.AORL, 5221 reg: regInfo{ 5222 inputs: []inputInfo{ 5223 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5224 }, 5225 outputs: []outputInfo{ 5226 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5227 }, 5228 }, 5229 }, 5230 { 5231 name: "XORQ", 5232 argLen: 2, 5233 commutative: true, 5234 resultInArg0: true, 5235 clobberFlags: true, 5236 asm: x86.AXORQ, 5237 reg: regInfo{ 5238 inputs: []inputInfo{ 5239 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5240 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5241 }, 5242 outputs: []outputInfo{ 5243 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5244 }, 5245 }, 5246 }, 5247 { 5248 name: "XORL", 5249 argLen: 2, 5250 commutative: true, 5251 resultInArg0: true, 5252 clobberFlags: true, 5253 asm: x86.AXORL, 5254 reg: regInfo{ 5255 inputs: []inputInfo{ 5256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5257 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5258 }, 5259 outputs: []outputInfo{ 5260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5261 }, 5262 }, 5263 }, 5264 { 5265 name: "XORQconst", 5266 auxType: auxInt64, 5267 argLen: 1, 5268 resultInArg0: true, 5269 clobberFlags: true, 5270 asm: x86.AXORQ, 5271 reg: regInfo{ 5272 inputs: []inputInfo{ 5273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5274 }, 5275 outputs: []outputInfo{ 5276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5277 }, 5278 }, 5279 }, 5280 { 5281 name: "XORLconst", 5282 auxType: auxInt32, 5283 argLen: 1, 5284 resultInArg0: true, 5285 clobberFlags: true, 5286 asm: x86.AXORL, 5287 reg: regInfo{ 5288 inputs: []inputInfo{ 5289 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5290 }, 5291 outputs: []outputInfo{ 5292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5293 }, 5294 }, 5295 }, 5296 { 5297 name: "CMPQ", 5298 argLen: 2, 5299 asm: x86.ACMPQ, 5300 reg: regInfo{ 5301 inputs: []inputInfo{ 5302 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5303 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5304 }, 5305 }, 5306 }, 5307 { 5308 name: "CMPL", 5309 argLen: 2, 5310 asm: x86.ACMPL, 5311 reg: regInfo{ 5312 inputs: []inputInfo{ 5313 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5314 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5315 }, 5316 }, 5317 }, 5318 { 5319 name: "CMPW", 5320 argLen: 2, 5321 asm: x86.ACMPW, 5322 reg: regInfo{ 5323 inputs: []inputInfo{ 5324 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5325 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5326 }, 5327 }, 5328 }, 5329 { 5330 name: "CMPB", 5331 argLen: 2, 5332 asm: x86.ACMPB, 5333 reg: regInfo{ 5334 inputs: []inputInfo{ 5335 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5336 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5337 }, 5338 }, 5339 }, 5340 { 5341 name: "CMPQconst", 5342 auxType: auxInt64, 5343 argLen: 1, 5344 asm: x86.ACMPQ, 5345 reg: regInfo{ 5346 inputs: []inputInfo{ 5347 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5348 }, 5349 }, 5350 }, 5351 { 5352 name: "CMPLconst", 5353 auxType: auxInt32, 5354 argLen: 1, 5355 asm: x86.ACMPL, 5356 reg: regInfo{ 5357 inputs: []inputInfo{ 5358 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5359 }, 5360 }, 5361 }, 5362 { 5363 name: "CMPWconst", 5364 auxType: auxInt16, 5365 argLen: 1, 5366 asm: x86.ACMPW, 5367 reg: regInfo{ 5368 inputs: []inputInfo{ 5369 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5370 }, 5371 }, 5372 }, 5373 { 5374 name: "CMPBconst", 5375 auxType: auxInt8, 5376 argLen: 1, 5377 asm: x86.ACMPB, 5378 reg: regInfo{ 5379 inputs: []inputInfo{ 5380 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5381 }, 5382 }, 5383 }, 5384 { 5385 name: "UCOMISS", 5386 argLen: 2, 5387 asm: x86.AUCOMISS, 5388 reg: regInfo{ 5389 inputs: []inputInfo{ 5390 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5391 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5392 }, 5393 }, 5394 }, 5395 { 5396 name: "UCOMISD", 5397 argLen: 2, 5398 asm: x86.AUCOMISD, 5399 reg: regInfo{ 5400 inputs: []inputInfo{ 5401 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5402 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5403 }, 5404 }, 5405 }, 5406 { 5407 name: "TESTQ", 5408 argLen: 2, 5409 asm: x86.ATESTQ, 5410 reg: regInfo{ 5411 inputs: []inputInfo{ 5412 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5413 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5414 }, 5415 }, 5416 }, 5417 { 5418 name: "TESTL", 5419 argLen: 2, 5420 asm: x86.ATESTL, 5421 reg: regInfo{ 5422 inputs: []inputInfo{ 5423 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5424 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5425 }, 5426 }, 5427 }, 5428 { 5429 name: "TESTW", 5430 argLen: 2, 5431 asm: x86.ATESTW, 5432 reg: regInfo{ 5433 inputs: []inputInfo{ 5434 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5435 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5436 }, 5437 }, 5438 }, 5439 { 5440 name: "TESTB", 5441 argLen: 2, 5442 asm: x86.ATESTB, 5443 reg: regInfo{ 5444 inputs: []inputInfo{ 5445 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5446 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5447 }, 5448 }, 5449 }, 5450 { 5451 name: "TESTQconst", 5452 auxType: auxInt64, 5453 argLen: 1, 5454 asm: x86.ATESTQ, 5455 reg: regInfo{ 5456 inputs: []inputInfo{ 5457 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5458 }, 5459 }, 5460 }, 5461 { 5462 name: "TESTLconst", 5463 auxType: auxInt32, 5464 argLen: 1, 5465 asm: x86.ATESTL, 5466 reg: regInfo{ 5467 inputs: []inputInfo{ 5468 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5469 }, 5470 }, 5471 }, 5472 { 5473 name: "TESTWconst", 5474 auxType: auxInt16, 5475 argLen: 1, 5476 asm: x86.ATESTW, 5477 reg: regInfo{ 5478 inputs: []inputInfo{ 5479 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5480 }, 5481 }, 5482 }, 5483 { 5484 name: "TESTBconst", 5485 auxType: auxInt8, 5486 argLen: 1, 5487 asm: x86.ATESTB, 5488 reg: regInfo{ 5489 inputs: []inputInfo{ 5490 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5491 }, 5492 }, 5493 }, 5494 { 5495 name: "SHLQ", 5496 argLen: 2, 5497 resultInArg0: true, 5498 clobberFlags: true, 5499 asm: x86.ASHLQ, 5500 reg: regInfo{ 5501 inputs: []inputInfo{ 5502 {1, 2}, // CX 5503 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5504 }, 5505 outputs: []outputInfo{ 5506 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5507 }, 5508 }, 5509 }, 5510 { 5511 name: "SHLL", 5512 argLen: 2, 5513 resultInArg0: true, 5514 clobberFlags: true, 5515 asm: x86.ASHLL, 5516 reg: regInfo{ 5517 inputs: []inputInfo{ 5518 {1, 2}, // CX 5519 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5520 }, 5521 outputs: []outputInfo{ 5522 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5523 }, 5524 }, 5525 }, 5526 { 5527 name: "SHLQconst", 5528 auxType: auxInt64, 5529 argLen: 1, 5530 resultInArg0: true, 5531 clobberFlags: true, 5532 asm: x86.ASHLQ, 5533 reg: regInfo{ 5534 inputs: []inputInfo{ 5535 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5536 }, 5537 outputs: []outputInfo{ 5538 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5539 }, 5540 }, 5541 }, 5542 { 5543 name: "SHLLconst", 5544 auxType: auxInt32, 5545 argLen: 1, 5546 resultInArg0: true, 5547 clobberFlags: true, 5548 asm: x86.ASHLL, 5549 reg: regInfo{ 5550 inputs: []inputInfo{ 5551 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5552 }, 5553 outputs: []outputInfo{ 5554 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5555 }, 5556 }, 5557 }, 5558 { 5559 name: "SHRQ", 5560 argLen: 2, 5561 resultInArg0: true, 5562 clobberFlags: true, 5563 asm: x86.ASHRQ, 5564 reg: regInfo{ 5565 inputs: []inputInfo{ 5566 {1, 2}, // CX 5567 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5568 }, 5569 outputs: []outputInfo{ 5570 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5571 }, 5572 }, 5573 }, 5574 { 5575 name: "SHRL", 5576 argLen: 2, 5577 resultInArg0: true, 5578 clobberFlags: true, 5579 asm: x86.ASHRL, 5580 reg: regInfo{ 5581 inputs: []inputInfo{ 5582 {1, 2}, // CX 5583 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5584 }, 5585 outputs: []outputInfo{ 5586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5587 }, 5588 }, 5589 }, 5590 { 5591 name: "SHRW", 5592 argLen: 2, 5593 resultInArg0: true, 5594 clobberFlags: true, 5595 asm: x86.ASHRW, 5596 reg: regInfo{ 5597 inputs: []inputInfo{ 5598 {1, 2}, // CX 5599 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5600 }, 5601 outputs: []outputInfo{ 5602 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5603 }, 5604 }, 5605 }, 5606 { 5607 name: "SHRB", 5608 argLen: 2, 5609 resultInArg0: true, 5610 clobberFlags: true, 5611 asm: x86.ASHRB, 5612 reg: regInfo{ 5613 inputs: []inputInfo{ 5614 {1, 2}, // CX 5615 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5616 }, 5617 outputs: []outputInfo{ 5618 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5619 }, 5620 }, 5621 }, 5622 { 5623 name: "SHRQconst", 5624 auxType: auxInt64, 5625 argLen: 1, 5626 resultInArg0: true, 5627 clobberFlags: true, 5628 asm: x86.ASHRQ, 5629 reg: regInfo{ 5630 inputs: []inputInfo{ 5631 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5632 }, 5633 outputs: []outputInfo{ 5634 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5635 }, 5636 }, 5637 }, 5638 { 5639 name: "SHRLconst", 5640 auxType: auxInt32, 5641 argLen: 1, 5642 resultInArg0: true, 5643 clobberFlags: true, 5644 asm: x86.ASHRL, 5645 reg: regInfo{ 5646 inputs: []inputInfo{ 5647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5648 }, 5649 outputs: []outputInfo{ 5650 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5651 }, 5652 }, 5653 }, 5654 { 5655 name: "SHRWconst", 5656 auxType: auxInt16, 5657 argLen: 1, 5658 resultInArg0: true, 5659 clobberFlags: true, 5660 asm: x86.ASHRW, 5661 reg: regInfo{ 5662 inputs: []inputInfo{ 5663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5664 }, 5665 outputs: []outputInfo{ 5666 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5667 }, 5668 }, 5669 }, 5670 { 5671 name: "SHRBconst", 5672 auxType: auxInt8, 5673 argLen: 1, 5674 resultInArg0: true, 5675 clobberFlags: true, 5676 asm: x86.ASHRB, 5677 reg: regInfo{ 5678 inputs: []inputInfo{ 5679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5680 }, 5681 outputs: []outputInfo{ 5682 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5683 }, 5684 }, 5685 }, 5686 { 5687 name: "SARQ", 5688 argLen: 2, 5689 resultInArg0: true, 5690 clobberFlags: true, 5691 asm: x86.ASARQ, 5692 reg: regInfo{ 5693 inputs: []inputInfo{ 5694 {1, 2}, // CX 5695 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5696 }, 5697 outputs: []outputInfo{ 5698 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5699 }, 5700 }, 5701 }, 5702 { 5703 name: "SARL", 5704 argLen: 2, 5705 resultInArg0: true, 5706 clobberFlags: true, 5707 asm: x86.ASARL, 5708 reg: regInfo{ 5709 inputs: []inputInfo{ 5710 {1, 2}, // CX 5711 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5712 }, 5713 outputs: []outputInfo{ 5714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5715 }, 5716 }, 5717 }, 5718 { 5719 name: "SARW", 5720 argLen: 2, 5721 resultInArg0: true, 5722 clobberFlags: true, 5723 asm: x86.ASARW, 5724 reg: regInfo{ 5725 inputs: []inputInfo{ 5726 {1, 2}, // CX 5727 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5728 }, 5729 outputs: []outputInfo{ 5730 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5731 }, 5732 }, 5733 }, 5734 { 5735 name: "SARB", 5736 argLen: 2, 5737 resultInArg0: true, 5738 clobberFlags: true, 5739 asm: x86.ASARB, 5740 reg: regInfo{ 5741 inputs: []inputInfo{ 5742 {1, 2}, // CX 5743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5744 }, 5745 outputs: []outputInfo{ 5746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5747 }, 5748 }, 5749 }, 5750 { 5751 name: "SARQconst", 5752 auxType: auxInt64, 5753 argLen: 1, 5754 resultInArg0: true, 5755 clobberFlags: true, 5756 asm: x86.ASARQ, 5757 reg: regInfo{ 5758 inputs: []inputInfo{ 5759 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5760 }, 5761 outputs: []outputInfo{ 5762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5763 }, 5764 }, 5765 }, 5766 { 5767 name: "SARLconst", 5768 auxType: auxInt32, 5769 argLen: 1, 5770 resultInArg0: true, 5771 clobberFlags: true, 5772 asm: x86.ASARL, 5773 reg: regInfo{ 5774 inputs: []inputInfo{ 5775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5776 }, 5777 outputs: []outputInfo{ 5778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 }, 5781 }, 5782 { 5783 name: "SARWconst", 5784 auxType: auxInt16, 5785 argLen: 1, 5786 resultInArg0: true, 5787 clobberFlags: true, 5788 asm: x86.ASARW, 5789 reg: regInfo{ 5790 inputs: []inputInfo{ 5791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5792 }, 5793 outputs: []outputInfo{ 5794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5795 }, 5796 }, 5797 }, 5798 { 5799 name: "SARBconst", 5800 auxType: auxInt8, 5801 argLen: 1, 5802 resultInArg0: true, 5803 clobberFlags: true, 5804 asm: x86.ASARB, 5805 reg: regInfo{ 5806 inputs: []inputInfo{ 5807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5808 }, 5809 outputs: []outputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 }, 5813 }, 5814 { 5815 name: "ROLQconst", 5816 auxType: auxInt64, 5817 argLen: 1, 5818 resultInArg0: true, 5819 clobberFlags: true, 5820 asm: x86.AROLQ, 5821 reg: regInfo{ 5822 inputs: []inputInfo{ 5823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5824 }, 5825 outputs: []outputInfo{ 5826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5827 }, 5828 }, 5829 }, 5830 { 5831 name: "ROLLconst", 5832 auxType: auxInt32, 5833 argLen: 1, 5834 resultInArg0: true, 5835 clobberFlags: true, 5836 asm: x86.AROLL, 5837 reg: regInfo{ 5838 inputs: []inputInfo{ 5839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5840 }, 5841 outputs: []outputInfo{ 5842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5843 }, 5844 }, 5845 }, 5846 { 5847 name: "ROLWconst", 5848 auxType: auxInt16, 5849 argLen: 1, 5850 resultInArg0: true, 5851 clobberFlags: true, 5852 asm: x86.AROLW, 5853 reg: regInfo{ 5854 inputs: []inputInfo{ 5855 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5856 }, 5857 outputs: []outputInfo{ 5858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5859 }, 5860 }, 5861 }, 5862 { 5863 name: "ROLBconst", 5864 auxType: auxInt8, 5865 argLen: 1, 5866 resultInArg0: true, 5867 clobberFlags: true, 5868 asm: x86.AROLB, 5869 reg: regInfo{ 5870 inputs: []inputInfo{ 5871 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5872 }, 5873 outputs: []outputInfo{ 5874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5875 }, 5876 }, 5877 }, 5878 { 5879 name: "NEGQ", 5880 argLen: 1, 5881 resultInArg0: true, 5882 clobberFlags: true, 5883 asm: x86.ANEGQ, 5884 reg: regInfo{ 5885 inputs: []inputInfo{ 5886 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5887 }, 5888 outputs: []outputInfo{ 5889 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5890 }, 5891 }, 5892 }, 5893 { 5894 name: "NEGL", 5895 argLen: 1, 5896 resultInArg0: true, 5897 clobberFlags: true, 5898 asm: x86.ANEGL, 5899 reg: regInfo{ 5900 inputs: []inputInfo{ 5901 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5902 }, 5903 outputs: []outputInfo{ 5904 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5905 }, 5906 }, 5907 }, 5908 { 5909 name: "NOTQ", 5910 argLen: 1, 5911 resultInArg0: true, 5912 clobberFlags: true, 5913 asm: x86.ANOTQ, 5914 reg: regInfo{ 5915 inputs: []inputInfo{ 5916 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5917 }, 5918 outputs: []outputInfo{ 5919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5920 }, 5921 }, 5922 }, 5923 { 5924 name: "NOTL", 5925 argLen: 1, 5926 resultInArg0: true, 5927 clobberFlags: true, 5928 asm: x86.ANOTL, 5929 reg: regInfo{ 5930 inputs: []inputInfo{ 5931 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5932 }, 5933 outputs: []outputInfo{ 5934 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5935 }, 5936 }, 5937 }, 5938 { 5939 name: "BSFQ", 5940 argLen: 1, 5941 asm: x86.ABSFQ, 5942 reg: regInfo{ 5943 inputs: []inputInfo{ 5944 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5945 }, 5946 outputs: []outputInfo{ 5947 {1, 0}, 5948 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5949 }, 5950 }, 5951 }, 5952 { 5953 name: "BSFL", 5954 argLen: 1, 5955 asm: x86.ABSFL, 5956 reg: regInfo{ 5957 inputs: []inputInfo{ 5958 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5959 }, 5960 outputs: []outputInfo{ 5961 {1, 0}, 5962 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5963 }, 5964 }, 5965 }, 5966 { 5967 name: "CMOVQEQ", 5968 argLen: 3, 5969 resultInArg0: true, 5970 asm: x86.ACMOVQEQ, 5971 reg: regInfo{ 5972 inputs: []inputInfo{ 5973 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5974 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5975 }, 5976 outputs: []outputInfo{ 5977 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5978 }, 5979 }, 5980 }, 5981 { 5982 name: "CMOVLEQ", 5983 argLen: 3, 5984 resultInArg0: true, 5985 asm: x86.ACMOVLEQ, 5986 reg: regInfo{ 5987 inputs: []inputInfo{ 5988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5989 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5990 }, 5991 outputs: []outputInfo{ 5992 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5993 }, 5994 }, 5995 }, 5996 { 5997 name: "BSWAPQ", 5998 argLen: 1, 5999 resultInArg0: true, 6000 clobberFlags: true, 6001 asm: x86.ABSWAPQ, 6002 reg: regInfo{ 6003 inputs: []inputInfo{ 6004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6005 }, 6006 outputs: []outputInfo{ 6007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6008 }, 6009 }, 6010 }, 6011 { 6012 name: "BSWAPL", 6013 argLen: 1, 6014 resultInArg0: true, 6015 clobberFlags: true, 6016 asm: x86.ABSWAPL, 6017 reg: regInfo{ 6018 inputs: []inputInfo{ 6019 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6020 }, 6021 outputs: []outputInfo{ 6022 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6023 }, 6024 }, 6025 }, 6026 { 6027 name: "SQRTSD", 6028 argLen: 1, 6029 asm: x86.ASQRTSD, 6030 reg: regInfo{ 6031 inputs: []inputInfo{ 6032 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6033 }, 6034 outputs: []outputInfo{ 6035 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6036 }, 6037 }, 6038 }, 6039 { 6040 name: "SBBQcarrymask", 6041 argLen: 1, 6042 asm: x86.ASBBQ, 6043 reg: regInfo{ 6044 outputs: []outputInfo{ 6045 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6046 }, 6047 }, 6048 }, 6049 { 6050 name: "SBBLcarrymask", 6051 argLen: 1, 6052 asm: x86.ASBBL, 6053 reg: regInfo{ 6054 outputs: []outputInfo{ 6055 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6056 }, 6057 }, 6058 }, 6059 { 6060 name: "SETEQ", 6061 argLen: 1, 6062 asm: x86.ASETEQ, 6063 reg: regInfo{ 6064 outputs: []outputInfo{ 6065 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6066 }, 6067 }, 6068 }, 6069 { 6070 name: "SETNE", 6071 argLen: 1, 6072 asm: x86.ASETNE, 6073 reg: regInfo{ 6074 outputs: []outputInfo{ 6075 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6076 }, 6077 }, 6078 }, 6079 { 6080 name: "SETL", 6081 argLen: 1, 6082 asm: x86.ASETLT, 6083 reg: regInfo{ 6084 outputs: []outputInfo{ 6085 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6086 }, 6087 }, 6088 }, 6089 { 6090 name: "SETLE", 6091 argLen: 1, 6092 asm: x86.ASETLE, 6093 reg: regInfo{ 6094 outputs: []outputInfo{ 6095 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6096 }, 6097 }, 6098 }, 6099 { 6100 name: "SETG", 6101 argLen: 1, 6102 asm: x86.ASETGT, 6103 reg: regInfo{ 6104 outputs: []outputInfo{ 6105 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6106 }, 6107 }, 6108 }, 6109 { 6110 name: "SETGE", 6111 argLen: 1, 6112 asm: x86.ASETGE, 6113 reg: regInfo{ 6114 outputs: []outputInfo{ 6115 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6116 }, 6117 }, 6118 }, 6119 { 6120 name: "SETB", 6121 argLen: 1, 6122 asm: x86.ASETCS, 6123 reg: regInfo{ 6124 outputs: []outputInfo{ 6125 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6126 }, 6127 }, 6128 }, 6129 { 6130 name: "SETBE", 6131 argLen: 1, 6132 asm: x86.ASETLS, 6133 reg: regInfo{ 6134 outputs: []outputInfo{ 6135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6136 }, 6137 }, 6138 }, 6139 { 6140 name: "SETA", 6141 argLen: 1, 6142 asm: x86.ASETHI, 6143 reg: regInfo{ 6144 outputs: []outputInfo{ 6145 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6146 }, 6147 }, 6148 }, 6149 { 6150 name: "SETAE", 6151 argLen: 1, 6152 asm: x86.ASETCC, 6153 reg: regInfo{ 6154 outputs: []outputInfo{ 6155 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6156 }, 6157 }, 6158 }, 6159 { 6160 name: "SETEQF", 6161 argLen: 1, 6162 clobberFlags: true, 6163 asm: x86.ASETEQ, 6164 reg: regInfo{ 6165 clobbers: 1, // AX 6166 outputs: []outputInfo{ 6167 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6168 }, 6169 }, 6170 }, 6171 { 6172 name: "SETNEF", 6173 argLen: 1, 6174 clobberFlags: true, 6175 asm: x86.ASETNE, 6176 reg: regInfo{ 6177 clobbers: 1, // AX 6178 outputs: []outputInfo{ 6179 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6180 }, 6181 }, 6182 }, 6183 { 6184 name: "SETORD", 6185 argLen: 1, 6186 asm: x86.ASETPC, 6187 reg: regInfo{ 6188 outputs: []outputInfo{ 6189 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6190 }, 6191 }, 6192 }, 6193 { 6194 name: "SETNAN", 6195 argLen: 1, 6196 asm: x86.ASETPS, 6197 reg: regInfo{ 6198 outputs: []outputInfo{ 6199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6200 }, 6201 }, 6202 }, 6203 { 6204 name: "SETGF", 6205 argLen: 1, 6206 asm: x86.ASETHI, 6207 reg: regInfo{ 6208 outputs: []outputInfo{ 6209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6210 }, 6211 }, 6212 }, 6213 { 6214 name: "SETGEF", 6215 argLen: 1, 6216 asm: x86.ASETCC, 6217 reg: regInfo{ 6218 outputs: []outputInfo{ 6219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6220 }, 6221 }, 6222 }, 6223 { 6224 name: "MOVBQSX", 6225 argLen: 1, 6226 asm: x86.AMOVBQSX, 6227 reg: regInfo{ 6228 inputs: []inputInfo{ 6229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6230 }, 6231 outputs: []outputInfo{ 6232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6233 }, 6234 }, 6235 }, 6236 { 6237 name: "MOVBQZX", 6238 argLen: 1, 6239 asm: x86.AMOVBLZX, 6240 reg: regInfo{ 6241 inputs: []inputInfo{ 6242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6243 }, 6244 outputs: []outputInfo{ 6245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6246 }, 6247 }, 6248 }, 6249 { 6250 name: "MOVWQSX", 6251 argLen: 1, 6252 asm: x86.AMOVWQSX, 6253 reg: regInfo{ 6254 inputs: []inputInfo{ 6255 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6256 }, 6257 outputs: []outputInfo{ 6258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6259 }, 6260 }, 6261 }, 6262 { 6263 name: "MOVWQZX", 6264 argLen: 1, 6265 asm: x86.AMOVWLZX, 6266 reg: regInfo{ 6267 inputs: []inputInfo{ 6268 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6269 }, 6270 outputs: []outputInfo{ 6271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6272 }, 6273 }, 6274 }, 6275 { 6276 name: "MOVLQSX", 6277 argLen: 1, 6278 asm: x86.AMOVLQSX, 6279 reg: regInfo{ 6280 inputs: []inputInfo{ 6281 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6282 }, 6283 outputs: []outputInfo{ 6284 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6285 }, 6286 }, 6287 }, 6288 { 6289 name: "MOVLQZX", 6290 argLen: 1, 6291 asm: x86.AMOVL, 6292 reg: regInfo{ 6293 inputs: []inputInfo{ 6294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6295 }, 6296 outputs: []outputInfo{ 6297 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6298 }, 6299 }, 6300 }, 6301 { 6302 name: "MOVLconst", 6303 auxType: auxInt32, 6304 argLen: 0, 6305 rematerializeable: true, 6306 asm: x86.AMOVL, 6307 reg: regInfo{ 6308 outputs: []outputInfo{ 6309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6310 }, 6311 }, 6312 }, 6313 { 6314 name: "MOVQconst", 6315 auxType: auxInt64, 6316 argLen: 0, 6317 rematerializeable: true, 6318 asm: x86.AMOVQ, 6319 reg: regInfo{ 6320 outputs: []outputInfo{ 6321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6322 }, 6323 }, 6324 }, 6325 { 6326 name: "CVTTSD2SL", 6327 argLen: 1, 6328 asm: x86.ACVTTSD2SL, 6329 reg: regInfo{ 6330 inputs: []inputInfo{ 6331 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6332 }, 6333 outputs: []outputInfo{ 6334 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6335 }, 6336 }, 6337 }, 6338 { 6339 name: "CVTTSD2SQ", 6340 argLen: 1, 6341 asm: x86.ACVTTSD2SQ, 6342 reg: regInfo{ 6343 inputs: []inputInfo{ 6344 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6345 }, 6346 outputs: []outputInfo{ 6347 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6348 }, 6349 }, 6350 }, 6351 { 6352 name: "CVTTSS2SL", 6353 argLen: 1, 6354 asm: x86.ACVTTSS2SL, 6355 reg: regInfo{ 6356 inputs: []inputInfo{ 6357 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6358 }, 6359 outputs: []outputInfo{ 6360 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6361 }, 6362 }, 6363 }, 6364 { 6365 name: "CVTTSS2SQ", 6366 argLen: 1, 6367 asm: x86.ACVTTSS2SQ, 6368 reg: regInfo{ 6369 inputs: []inputInfo{ 6370 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6371 }, 6372 outputs: []outputInfo{ 6373 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6374 }, 6375 }, 6376 }, 6377 { 6378 name: "CVTSL2SS", 6379 argLen: 1, 6380 asm: x86.ACVTSL2SS, 6381 reg: regInfo{ 6382 inputs: []inputInfo{ 6383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6384 }, 6385 outputs: []outputInfo{ 6386 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6387 }, 6388 }, 6389 }, 6390 { 6391 name: "CVTSL2SD", 6392 argLen: 1, 6393 asm: x86.ACVTSL2SD, 6394 reg: regInfo{ 6395 inputs: []inputInfo{ 6396 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6397 }, 6398 outputs: []outputInfo{ 6399 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6400 }, 6401 }, 6402 }, 6403 { 6404 name: "CVTSQ2SS", 6405 argLen: 1, 6406 asm: x86.ACVTSQ2SS, 6407 reg: regInfo{ 6408 inputs: []inputInfo{ 6409 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6410 }, 6411 outputs: []outputInfo{ 6412 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6413 }, 6414 }, 6415 }, 6416 { 6417 name: "CVTSQ2SD", 6418 argLen: 1, 6419 asm: x86.ACVTSQ2SD, 6420 reg: regInfo{ 6421 inputs: []inputInfo{ 6422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6423 }, 6424 outputs: []outputInfo{ 6425 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6426 }, 6427 }, 6428 }, 6429 { 6430 name: "CVTSD2SS", 6431 argLen: 1, 6432 asm: x86.ACVTSD2SS, 6433 reg: regInfo{ 6434 inputs: []inputInfo{ 6435 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6436 }, 6437 outputs: []outputInfo{ 6438 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6439 }, 6440 }, 6441 }, 6442 { 6443 name: "CVTSS2SD", 6444 argLen: 1, 6445 asm: x86.ACVTSS2SD, 6446 reg: regInfo{ 6447 inputs: []inputInfo{ 6448 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6449 }, 6450 outputs: []outputInfo{ 6451 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6452 }, 6453 }, 6454 }, 6455 { 6456 name: "PXOR", 6457 argLen: 2, 6458 commutative: true, 6459 resultInArg0: true, 6460 asm: x86.APXOR, 6461 reg: regInfo{ 6462 inputs: []inputInfo{ 6463 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6464 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6465 }, 6466 outputs: []outputInfo{ 6467 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6468 }, 6469 }, 6470 }, 6471 { 6472 name: "LEAQ", 6473 auxType: auxSymOff, 6474 argLen: 1, 6475 rematerializeable: true, 6476 asm: x86.ALEAQ, 6477 reg: regInfo{ 6478 inputs: []inputInfo{ 6479 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6480 }, 6481 outputs: []outputInfo{ 6482 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6483 }, 6484 }, 6485 }, 6486 { 6487 name: "LEAQ1", 6488 auxType: auxSymOff, 6489 argLen: 2, 6490 reg: regInfo{ 6491 inputs: []inputInfo{ 6492 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6493 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6494 }, 6495 outputs: []outputInfo{ 6496 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6497 }, 6498 }, 6499 }, 6500 { 6501 name: "LEAQ2", 6502 auxType: auxSymOff, 6503 argLen: 2, 6504 reg: regInfo{ 6505 inputs: []inputInfo{ 6506 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6507 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6508 }, 6509 outputs: []outputInfo{ 6510 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6511 }, 6512 }, 6513 }, 6514 { 6515 name: "LEAQ4", 6516 auxType: auxSymOff, 6517 argLen: 2, 6518 reg: regInfo{ 6519 inputs: []inputInfo{ 6520 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6521 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6522 }, 6523 outputs: []outputInfo{ 6524 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6525 }, 6526 }, 6527 }, 6528 { 6529 name: "LEAQ8", 6530 auxType: auxSymOff, 6531 argLen: 2, 6532 reg: regInfo{ 6533 inputs: []inputInfo{ 6534 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6535 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6536 }, 6537 outputs: []outputInfo{ 6538 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6539 }, 6540 }, 6541 }, 6542 { 6543 name: "LEAL", 6544 auxType: auxSymOff, 6545 argLen: 1, 6546 rematerializeable: true, 6547 asm: x86.ALEAL, 6548 reg: regInfo{ 6549 inputs: []inputInfo{ 6550 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6551 }, 6552 outputs: []outputInfo{ 6553 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6554 }, 6555 }, 6556 }, 6557 { 6558 name: "MOVBload", 6559 auxType: auxSymOff, 6560 argLen: 2, 6561 faultOnNilArg0: true, 6562 asm: x86.AMOVBLZX, 6563 reg: regInfo{ 6564 inputs: []inputInfo{ 6565 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6566 }, 6567 outputs: []outputInfo{ 6568 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6569 }, 6570 }, 6571 }, 6572 { 6573 name: "MOVBQSXload", 6574 auxType: auxSymOff, 6575 argLen: 2, 6576 faultOnNilArg0: true, 6577 asm: x86.AMOVBQSX, 6578 reg: regInfo{ 6579 inputs: []inputInfo{ 6580 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6581 }, 6582 outputs: []outputInfo{ 6583 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6584 }, 6585 }, 6586 }, 6587 { 6588 name: "MOVWload", 6589 auxType: auxSymOff, 6590 argLen: 2, 6591 faultOnNilArg0: true, 6592 asm: x86.AMOVWLZX, 6593 reg: regInfo{ 6594 inputs: []inputInfo{ 6595 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6596 }, 6597 outputs: []outputInfo{ 6598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6599 }, 6600 }, 6601 }, 6602 { 6603 name: "MOVWQSXload", 6604 auxType: auxSymOff, 6605 argLen: 2, 6606 faultOnNilArg0: true, 6607 asm: x86.AMOVWQSX, 6608 reg: regInfo{ 6609 inputs: []inputInfo{ 6610 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6611 }, 6612 outputs: []outputInfo{ 6613 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6614 }, 6615 }, 6616 }, 6617 { 6618 name: "MOVLload", 6619 auxType: auxSymOff, 6620 argLen: 2, 6621 faultOnNilArg0: true, 6622 asm: x86.AMOVL, 6623 reg: regInfo{ 6624 inputs: []inputInfo{ 6625 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6626 }, 6627 outputs: []outputInfo{ 6628 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6629 }, 6630 }, 6631 }, 6632 { 6633 name: "MOVLQSXload", 6634 auxType: auxSymOff, 6635 argLen: 2, 6636 faultOnNilArg0: true, 6637 asm: x86.AMOVLQSX, 6638 reg: regInfo{ 6639 inputs: []inputInfo{ 6640 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6641 }, 6642 outputs: []outputInfo{ 6643 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6644 }, 6645 }, 6646 }, 6647 { 6648 name: "MOVQload", 6649 auxType: auxSymOff, 6650 argLen: 2, 6651 faultOnNilArg0: true, 6652 asm: x86.AMOVQ, 6653 reg: regInfo{ 6654 inputs: []inputInfo{ 6655 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6656 }, 6657 outputs: []outputInfo{ 6658 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6659 }, 6660 }, 6661 }, 6662 { 6663 name: "MOVBstore", 6664 auxType: auxSymOff, 6665 argLen: 3, 6666 faultOnNilArg0: true, 6667 asm: x86.AMOVB, 6668 reg: regInfo{ 6669 inputs: []inputInfo{ 6670 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6671 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6672 }, 6673 }, 6674 }, 6675 { 6676 name: "MOVWstore", 6677 auxType: auxSymOff, 6678 argLen: 3, 6679 faultOnNilArg0: true, 6680 asm: x86.AMOVW, 6681 reg: regInfo{ 6682 inputs: []inputInfo{ 6683 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6684 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6685 }, 6686 }, 6687 }, 6688 { 6689 name: "MOVLstore", 6690 auxType: auxSymOff, 6691 argLen: 3, 6692 faultOnNilArg0: true, 6693 asm: x86.AMOVL, 6694 reg: regInfo{ 6695 inputs: []inputInfo{ 6696 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6697 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6698 }, 6699 }, 6700 }, 6701 { 6702 name: "MOVQstore", 6703 auxType: auxSymOff, 6704 argLen: 3, 6705 faultOnNilArg0: true, 6706 asm: x86.AMOVQ, 6707 reg: regInfo{ 6708 inputs: []inputInfo{ 6709 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6710 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6711 }, 6712 }, 6713 }, 6714 { 6715 name: "MOVOload", 6716 auxType: auxSymOff, 6717 argLen: 2, 6718 faultOnNilArg0: true, 6719 asm: x86.AMOVUPS, 6720 reg: regInfo{ 6721 inputs: []inputInfo{ 6722 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6723 }, 6724 outputs: []outputInfo{ 6725 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6726 }, 6727 }, 6728 }, 6729 { 6730 name: "MOVOstore", 6731 auxType: auxSymOff, 6732 argLen: 3, 6733 faultOnNilArg0: true, 6734 asm: x86.AMOVUPS, 6735 reg: regInfo{ 6736 inputs: []inputInfo{ 6737 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6738 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6739 }, 6740 }, 6741 }, 6742 { 6743 name: "MOVBloadidx1", 6744 auxType: auxSymOff, 6745 argLen: 3, 6746 asm: x86.AMOVBLZX, 6747 reg: regInfo{ 6748 inputs: []inputInfo{ 6749 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6750 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6751 }, 6752 outputs: []outputInfo{ 6753 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6754 }, 6755 }, 6756 }, 6757 { 6758 name: "MOVWloadidx1", 6759 auxType: auxSymOff, 6760 argLen: 3, 6761 asm: x86.AMOVWLZX, 6762 reg: regInfo{ 6763 inputs: []inputInfo{ 6764 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6765 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6766 }, 6767 outputs: []outputInfo{ 6768 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6769 }, 6770 }, 6771 }, 6772 { 6773 name: "MOVWloadidx2", 6774 auxType: auxSymOff, 6775 argLen: 3, 6776 asm: x86.AMOVWLZX, 6777 reg: regInfo{ 6778 inputs: []inputInfo{ 6779 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6780 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6781 }, 6782 outputs: []outputInfo{ 6783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6784 }, 6785 }, 6786 }, 6787 { 6788 name: "MOVLloadidx1", 6789 auxType: auxSymOff, 6790 argLen: 3, 6791 asm: x86.AMOVL, 6792 reg: regInfo{ 6793 inputs: []inputInfo{ 6794 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6795 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6796 }, 6797 outputs: []outputInfo{ 6798 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6799 }, 6800 }, 6801 }, 6802 { 6803 name: "MOVLloadidx4", 6804 auxType: auxSymOff, 6805 argLen: 3, 6806 asm: x86.AMOVL, 6807 reg: regInfo{ 6808 inputs: []inputInfo{ 6809 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6810 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6811 }, 6812 outputs: []outputInfo{ 6813 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6814 }, 6815 }, 6816 }, 6817 { 6818 name: "MOVQloadidx1", 6819 auxType: auxSymOff, 6820 argLen: 3, 6821 asm: x86.AMOVQ, 6822 reg: regInfo{ 6823 inputs: []inputInfo{ 6824 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6825 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6826 }, 6827 outputs: []outputInfo{ 6828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6829 }, 6830 }, 6831 }, 6832 { 6833 name: "MOVQloadidx8", 6834 auxType: auxSymOff, 6835 argLen: 3, 6836 asm: x86.AMOVQ, 6837 reg: regInfo{ 6838 inputs: []inputInfo{ 6839 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6840 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6841 }, 6842 outputs: []outputInfo{ 6843 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6844 }, 6845 }, 6846 }, 6847 { 6848 name: "MOVBstoreidx1", 6849 auxType: auxSymOff, 6850 argLen: 4, 6851 asm: x86.AMOVB, 6852 reg: regInfo{ 6853 inputs: []inputInfo{ 6854 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6855 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6856 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6857 }, 6858 }, 6859 }, 6860 { 6861 name: "MOVWstoreidx1", 6862 auxType: auxSymOff, 6863 argLen: 4, 6864 asm: x86.AMOVW, 6865 reg: regInfo{ 6866 inputs: []inputInfo{ 6867 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6868 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6869 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6870 }, 6871 }, 6872 }, 6873 { 6874 name: "MOVWstoreidx2", 6875 auxType: auxSymOff, 6876 argLen: 4, 6877 asm: x86.AMOVW, 6878 reg: regInfo{ 6879 inputs: []inputInfo{ 6880 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6881 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6882 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6883 }, 6884 }, 6885 }, 6886 { 6887 name: "MOVLstoreidx1", 6888 auxType: auxSymOff, 6889 argLen: 4, 6890 asm: x86.AMOVL, 6891 reg: regInfo{ 6892 inputs: []inputInfo{ 6893 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6894 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6895 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6896 }, 6897 }, 6898 }, 6899 { 6900 name: "MOVLstoreidx4", 6901 auxType: auxSymOff, 6902 argLen: 4, 6903 asm: x86.AMOVL, 6904 reg: regInfo{ 6905 inputs: []inputInfo{ 6906 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6907 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6908 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6909 }, 6910 }, 6911 }, 6912 { 6913 name: "MOVQstoreidx1", 6914 auxType: auxSymOff, 6915 argLen: 4, 6916 asm: x86.AMOVQ, 6917 reg: regInfo{ 6918 inputs: []inputInfo{ 6919 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6920 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6921 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6922 }, 6923 }, 6924 }, 6925 { 6926 name: "MOVQstoreidx8", 6927 auxType: auxSymOff, 6928 argLen: 4, 6929 asm: x86.AMOVQ, 6930 reg: regInfo{ 6931 inputs: []inputInfo{ 6932 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6933 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6934 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6935 }, 6936 }, 6937 }, 6938 { 6939 name: "MOVBstoreconst", 6940 auxType: auxSymValAndOff, 6941 argLen: 2, 6942 faultOnNilArg0: true, 6943 asm: x86.AMOVB, 6944 reg: regInfo{ 6945 inputs: []inputInfo{ 6946 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6947 }, 6948 }, 6949 }, 6950 { 6951 name: "MOVWstoreconst", 6952 auxType: auxSymValAndOff, 6953 argLen: 2, 6954 faultOnNilArg0: true, 6955 asm: x86.AMOVW, 6956 reg: regInfo{ 6957 inputs: []inputInfo{ 6958 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6959 }, 6960 }, 6961 }, 6962 { 6963 name: "MOVLstoreconst", 6964 auxType: auxSymValAndOff, 6965 argLen: 2, 6966 faultOnNilArg0: true, 6967 asm: x86.AMOVL, 6968 reg: regInfo{ 6969 inputs: []inputInfo{ 6970 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6971 }, 6972 }, 6973 }, 6974 { 6975 name: "MOVQstoreconst", 6976 auxType: auxSymValAndOff, 6977 argLen: 2, 6978 faultOnNilArg0: true, 6979 asm: x86.AMOVQ, 6980 reg: regInfo{ 6981 inputs: []inputInfo{ 6982 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6983 }, 6984 }, 6985 }, 6986 { 6987 name: "MOVBstoreconstidx1", 6988 auxType: auxSymValAndOff, 6989 argLen: 3, 6990 asm: x86.AMOVB, 6991 reg: regInfo{ 6992 inputs: []inputInfo{ 6993 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6994 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6995 }, 6996 }, 6997 }, 6998 { 6999 name: "MOVWstoreconstidx1", 7000 auxType: auxSymValAndOff, 7001 argLen: 3, 7002 asm: x86.AMOVW, 7003 reg: regInfo{ 7004 inputs: []inputInfo{ 7005 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7006 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7007 }, 7008 }, 7009 }, 7010 { 7011 name: "MOVWstoreconstidx2", 7012 auxType: auxSymValAndOff, 7013 argLen: 3, 7014 asm: x86.AMOVW, 7015 reg: regInfo{ 7016 inputs: []inputInfo{ 7017 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7018 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7019 }, 7020 }, 7021 }, 7022 { 7023 name: "MOVLstoreconstidx1", 7024 auxType: auxSymValAndOff, 7025 argLen: 3, 7026 asm: x86.AMOVL, 7027 reg: regInfo{ 7028 inputs: []inputInfo{ 7029 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7030 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7031 }, 7032 }, 7033 }, 7034 { 7035 name: "MOVLstoreconstidx4", 7036 auxType: auxSymValAndOff, 7037 argLen: 3, 7038 asm: x86.AMOVL, 7039 reg: regInfo{ 7040 inputs: []inputInfo{ 7041 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7042 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7043 }, 7044 }, 7045 }, 7046 { 7047 name: "MOVQstoreconstidx1", 7048 auxType: auxSymValAndOff, 7049 argLen: 3, 7050 asm: x86.AMOVQ, 7051 reg: regInfo{ 7052 inputs: []inputInfo{ 7053 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7054 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7055 }, 7056 }, 7057 }, 7058 { 7059 name: "MOVQstoreconstidx8", 7060 auxType: auxSymValAndOff, 7061 argLen: 3, 7062 asm: x86.AMOVQ, 7063 reg: regInfo{ 7064 inputs: []inputInfo{ 7065 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7066 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7067 }, 7068 }, 7069 }, 7070 { 7071 name: "DUFFZERO", 7072 auxType: auxInt64, 7073 argLen: 3, 7074 clobberFlags: true, 7075 reg: regInfo{ 7076 inputs: []inputInfo{ 7077 {0, 128}, // DI 7078 {1, 65536}, // X0 7079 }, 7080 clobbers: 128, // DI 7081 }, 7082 }, 7083 { 7084 name: "MOVOconst", 7085 auxType: auxInt128, 7086 argLen: 0, 7087 rematerializeable: true, 7088 reg: regInfo{ 7089 outputs: []outputInfo{ 7090 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7091 }, 7092 }, 7093 }, 7094 { 7095 name: "REPSTOSQ", 7096 argLen: 4, 7097 reg: regInfo{ 7098 inputs: []inputInfo{ 7099 {0, 128}, // DI 7100 {1, 2}, // CX 7101 {2, 1}, // AX 7102 }, 7103 clobbers: 130, // CX DI 7104 }, 7105 }, 7106 { 7107 name: "CALLstatic", 7108 auxType: auxSymOff, 7109 argLen: 1, 7110 clobberFlags: true, 7111 call: true, 7112 reg: regInfo{ 7113 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7114 }, 7115 }, 7116 { 7117 name: "CALLclosure", 7118 auxType: auxInt64, 7119 argLen: 3, 7120 clobberFlags: true, 7121 call: true, 7122 reg: regInfo{ 7123 inputs: []inputInfo{ 7124 {1, 4}, // DX 7125 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7126 }, 7127 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7128 }, 7129 }, 7130 { 7131 name: "CALLdefer", 7132 auxType: auxInt64, 7133 argLen: 1, 7134 clobberFlags: true, 7135 call: true, 7136 reg: regInfo{ 7137 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7138 }, 7139 }, 7140 { 7141 name: "CALLgo", 7142 auxType: auxInt64, 7143 argLen: 1, 7144 clobberFlags: true, 7145 call: true, 7146 reg: regInfo{ 7147 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7148 }, 7149 }, 7150 { 7151 name: "CALLinter", 7152 auxType: auxInt64, 7153 argLen: 2, 7154 clobberFlags: true, 7155 call: true, 7156 reg: regInfo{ 7157 inputs: []inputInfo{ 7158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7159 }, 7160 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7161 }, 7162 }, 7163 { 7164 name: "DUFFCOPY", 7165 auxType: auxInt64, 7166 argLen: 3, 7167 clobberFlags: true, 7168 reg: regInfo{ 7169 inputs: []inputInfo{ 7170 {0, 128}, // DI 7171 {1, 64}, // SI 7172 }, 7173 clobbers: 65728, // SI DI X0 7174 }, 7175 }, 7176 { 7177 name: "REPMOVSQ", 7178 argLen: 4, 7179 reg: regInfo{ 7180 inputs: []inputInfo{ 7181 {0, 128}, // DI 7182 {1, 64}, // SI 7183 {2, 2}, // CX 7184 }, 7185 clobbers: 194, // CX SI DI 7186 }, 7187 }, 7188 { 7189 name: "InvertFlags", 7190 argLen: 1, 7191 reg: regInfo{}, 7192 }, 7193 { 7194 name: "LoweredGetG", 7195 argLen: 1, 7196 reg: regInfo{ 7197 outputs: []outputInfo{ 7198 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7199 }, 7200 }, 7201 }, 7202 { 7203 name: "LoweredGetClosurePtr", 7204 argLen: 0, 7205 reg: regInfo{ 7206 outputs: []outputInfo{ 7207 {0, 4}, // DX 7208 }, 7209 }, 7210 }, 7211 { 7212 name: "LoweredNilCheck", 7213 argLen: 2, 7214 clobberFlags: true, 7215 nilCheck: true, 7216 faultOnNilArg0: true, 7217 reg: regInfo{ 7218 inputs: []inputInfo{ 7219 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7220 }, 7221 }, 7222 }, 7223 { 7224 name: "MOVQconvert", 7225 argLen: 2, 7226 asm: x86.AMOVQ, 7227 reg: regInfo{ 7228 inputs: []inputInfo{ 7229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7230 }, 7231 outputs: []outputInfo{ 7232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7233 }, 7234 }, 7235 }, 7236 { 7237 name: "MOVLconvert", 7238 argLen: 2, 7239 asm: x86.AMOVL, 7240 reg: regInfo{ 7241 inputs: []inputInfo{ 7242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7243 }, 7244 outputs: []outputInfo{ 7245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7246 }, 7247 }, 7248 }, 7249 { 7250 name: "FlagEQ", 7251 argLen: 0, 7252 reg: regInfo{}, 7253 }, 7254 { 7255 name: "FlagLT_ULT", 7256 argLen: 0, 7257 reg: regInfo{}, 7258 }, 7259 { 7260 name: "FlagLT_UGT", 7261 argLen: 0, 7262 reg: regInfo{}, 7263 }, 7264 { 7265 name: "FlagGT_UGT", 7266 argLen: 0, 7267 reg: regInfo{}, 7268 }, 7269 { 7270 name: "FlagGT_ULT", 7271 argLen: 0, 7272 reg: regInfo{}, 7273 }, 7274 { 7275 name: "MOVLatomicload", 7276 auxType: auxSymOff, 7277 argLen: 2, 7278 faultOnNilArg0: true, 7279 asm: x86.AMOVL, 7280 reg: regInfo{ 7281 inputs: []inputInfo{ 7282 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7283 }, 7284 outputs: []outputInfo{ 7285 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7286 }, 7287 }, 7288 }, 7289 { 7290 name: "MOVQatomicload", 7291 auxType: auxSymOff, 7292 argLen: 2, 7293 faultOnNilArg0: true, 7294 asm: x86.AMOVQ, 7295 reg: regInfo{ 7296 inputs: []inputInfo{ 7297 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7298 }, 7299 outputs: []outputInfo{ 7300 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7301 }, 7302 }, 7303 }, 7304 { 7305 name: "XCHGL", 7306 auxType: auxSymOff, 7307 argLen: 3, 7308 resultInArg0: true, 7309 faultOnNilArg1: true, 7310 asm: x86.AXCHGL, 7311 reg: regInfo{ 7312 inputs: []inputInfo{ 7313 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7314 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7315 }, 7316 outputs: []outputInfo{ 7317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7318 }, 7319 }, 7320 }, 7321 { 7322 name: "XCHGQ", 7323 auxType: auxSymOff, 7324 argLen: 3, 7325 resultInArg0: true, 7326 faultOnNilArg1: true, 7327 asm: x86.AXCHGQ, 7328 reg: regInfo{ 7329 inputs: []inputInfo{ 7330 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7331 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7332 }, 7333 outputs: []outputInfo{ 7334 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7335 }, 7336 }, 7337 }, 7338 { 7339 name: "XADDLlock", 7340 auxType: auxSymOff, 7341 argLen: 3, 7342 resultInArg0: true, 7343 clobberFlags: true, 7344 faultOnNilArg1: true, 7345 asm: x86.AXADDL, 7346 reg: regInfo{ 7347 inputs: []inputInfo{ 7348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7349 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7350 }, 7351 outputs: []outputInfo{ 7352 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7353 }, 7354 }, 7355 }, 7356 { 7357 name: "XADDQlock", 7358 auxType: auxSymOff, 7359 argLen: 3, 7360 resultInArg0: true, 7361 clobberFlags: true, 7362 faultOnNilArg1: true, 7363 asm: x86.AXADDQ, 7364 reg: regInfo{ 7365 inputs: []inputInfo{ 7366 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7367 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7368 }, 7369 outputs: []outputInfo{ 7370 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7371 }, 7372 }, 7373 }, 7374 { 7375 name: "AddTupleFirst32", 7376 argLen: 2, 7377 reg: regInfo{}, 7378 }, 7379 { 7380 name: "AddTupleFirst64", 7381 argLen: 2, 7382 reg: regInfo{}, 7383 }, 7384 { 7385 name: "CMPXCHGLlock", 7386 auxType: auxSymOff, 7387 argLen: 4, 7388 clobberFlags: true, 7389 faultOnNilArg0: true, 7390 asm: x86.ACMPXCHGL, 7391 reg: regInfo{ 7392 inputs: []inputInfo{ 7393 {1, 1}, // AX 7394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7395 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7396 }, 7397 clobbers: 1, // AX 7398 outputs: []outputInfo{ 7399 {1, 0}, 7400 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7401 }, 7402 }, 7403 }, 7404 { 7405 name: "CMPXCHGQlock", 7406 auxType: auxSymOff, 7407 argLen: 4, 7408 clobberFlags: true, 7409 faultOnNilArg0: true, 7410 asm: x86.ACMPXCHGQ, 7411 reg: regInfo{ 7412 inputs: []inputInfo{ 7413 {1, 1}, // AX 7414 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7415 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7416 }, 7417 clobbers: 1, // AX 7418 outputs: []outputInfo{ 7419 {1, 0}, 7420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7421 }, 7422 }, 7423 }, 7424 { 7425 name: "ANDBlock", 7426 auxType: auxSymOff, 7427 argLen: 3, 7428 clobberFlags: true, 7429 faultOnNilArg0: true, 7430 asm: x86.AANDB, 7431 reg: regInfo{ 7432 inputs: []inputInfo{ 7433 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7434 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7435 }, 7436 }, 7437 }, 7438 { 7439 name: "ORBlock", 7440 auxType: auxSymOff, 7441 argLen: 3, 7442 clobberFlags: true, 7443 faultOnNilArg0: true, 7444 asm: x86.AORB, 7445 reg: regInfo{ 7446 inputs: []inputInfo{ 7447 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7448 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7449 }, 7450 }, 7451 }, 7452 7453 { 7454 name: "ADD", 7455 argLen: 2, 7456 commutative: true, 7457 asm: arm.AADD, 7458 reg: regInfo{ 7459 inputs: []inputInfo{ 7460 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7461 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7462 }, 7463 outputs: []outputInfo{ 7464 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7465 }, 7466 }, 7467 }, 7468 { 7469 name: "ADDconst", 7470 auxType: auxInt32, 7471 argLen: 1, 7472 asm: arm.AADD, 7473 reg: regInfo{ 7474 inputs: []inputInfo{ 7475 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7476 }, 7477 outputs: []outputInfo{ 7478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7479 }, 7480 }, 7481 }, 7482 { 7483 name: "SUB", 7484 argLen: 2, 7485 asm: arm.ASUB, 7486 reg: regInfo{ 7487 inputs: []inputInfo{ 7488 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7489 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7490 }, 7491 outputs: []outputInfo{ 7492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7493 }, 7494 }, 7495 }, 7496 { 7497 name: "SUBconst", 7498 auxType: auxInt32, 7499 argLen: 1, 7500 asm: arm.ASUB, 7501 reg: regInfo{ 7502 inputs: []inputInfo{ 7503 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7504 }, 7505 outputs: []outputInfo{ 7506 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7507 }, 7508 }, 7509 }, 7510 { 7511 name: "RSB", 7512 argLen: 2, 7513 asm: arm.ARSB, 7514 reg: regInfo{ 7515 inputs: []inputInfo{ 7516 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7517 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7518 }, 7519 outputs: []outputInfo{ 7520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7521 }, 7522 }, 7523 }, 7524 { 7525 name: "RSBconst", 7526 auxType: auxInt32, 7527 argLen: 1, 7528 asm: arm.ARSB, 7529 reg: regInfo{ 7530 inputs: []inputInfo{ 7531 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7532 }, 7533 outputs: []outputInfo{ 7534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7535 }, 7536 }, 7537 }, 7538 { 7539 name: "MUL", 7540 argLen: 2, 7541 commutative: true, 7542 asm: arm.AMUL, 7543 reg: regInfo{ 7544 inputs: []inputInfo{ 7545 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7546 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7547 }, 7548 outputs: []outputInfo{ 7549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7550 }, 7551 }, 7552 }, 7553 { 7554 name: "HMUL", 7555 argLen: 2, 7556 commutative: true, 7557 asm: arm.AMULL, 7558 reg: regInfo{ 7559 inputs: []inputInfo{ 7560 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7561 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7562 }, 7563 outputs: []outputInfo{ 7564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7565 }, 7566 }, 7567 }, 7568 { 7569 name: "HMULU", 7570 argLen: 2, 7571 commutative: true, 7572 asm: arm.AMULLU, 7573 reg: regInfo{ 7574 inputs: []inputInfo{ 7575 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7576 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7577 }, 7578 outputs: []outputInfo{ 7579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7580 }, 7581 }, 7582 }, 7583 { 7584 name: "UDIVrtcall", 7585 argLen: 2, 7586 clobberFlags: true, 7587 reg: regInfo{ 7588 inputs: []inputInfo{ 7589 {0, 2}, // R1 7590 {1, 1}, // R0 7591 }, 7592 clobbers: 16396, // R2 R3 R14 7593 outputs: []outputInfo{ 7594 {0, 1}, // R0 7595 {1, 2}, // R1 7596 }, 7597 }, 7598 }, 7599 { 7600 name: "ADDS", 7601 argLen: 2, 7602 commutative: true, 7603 asm: arm.AADD, 7604 reg: regInfo{ 7605 inputs: []inputInfo{ 7606 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7607 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7608 }, 7609 outputs: []outputInfo{ 7610 {1, 0}, 7611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7612 }, 7613 }, 7614 }, 7615 { 7616 name: "ADDSconst", 7617 auxType: auxInt32, 7618 argLen: 1, 7619 asm: arm.AADD, 7620 reg: regInfo{ 7621 inputs: []inputInfo{ 7622 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7623 }, 7624 outputs: []outputInfo{ 7625 {1, 0}, 7626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7627 }, 7628 }, 7629 }, 7630 { 7631 name: "ADC", 7632 argLen: 3, 7633 commutative: true, 7634 asm: arm.AADC, 7635 reg: regInfo{ 7636 inputs: []inputInfo{ 7637 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7638 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7639 }, 7640 outputs: []outputInfo{ 7641 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7642 }, 7643 }, 7644 }, 7645 { 7646 name: "ADCconst", 7647 auxType: auxInt32, 7648 argLen: 2, 7649 asm: arm.AADC, 7650 reg: regInfo{ 7651 inputs: []inputInfo{ 7652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7653 }, 7654 outputs: []outputInfo{ 7655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7656 }, 7657 }, 7658 }, 7659 { 7660 name: "SUBS", 7661 argLen: 2, 7662 asm: arm.ASUB, 7663 reg: regInfo{ 7664 inputs: []inputInfo{ 7665 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7666 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7667 }, 7668 outputs: []outputInfo{ 7669 {1, 0}, 7670 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7671 }, 7672 }, 7673 }, 7674 { 7675 name: "SUBSconst", 7676 auxType: auxInt32, 7677 argLen: 1, 7678 asm: arm.ASUB, 7679 reg: regInfo{ 7680 inputs: []inputInfo{ 7681 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7682 }, 7683 outputs: []outputInfo{ 7684 {1, 0}, 7685 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7686 }, 7687 }, 7688 }, 7689 { 7690 name: "RSBSconst", 7691 auxType: auxInt32, 7692 argLen: 1, 7693 asm: arm.ARSB, 7694 reg: regInfo{ 7695 inputs: []inputInfo{ 7696 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7697 }, 7698 outputs: []outputInfo{ 7699 {1, 0}, 7700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7701 }, 7702 }, 7703 }, 7704 { 7705 name: "SBC", 7706 argLen: 3, 7707 asm: arm.ASBC, 7708 reg: regInfo{ 7709 inputs: []inputInfo{ 7710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7711 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7712 }, 7713 outputs: []outputInfo{ 7714 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7715 }, 7716 }, 7717 }, 7718 { 7719 name: "SBCconst", 7720 auxType: auxInt32, 7721 argLen: 2, 7722 asm: arm.ASBC, 7723 reg: regInfo{ 7724 inputs: []inputInfo{ 7725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7726 }, 7727 outputs: []outputInfo{ 7728 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7729 }, 7730 }, 7731 }, 7732 { 7733 name: "RSCconst", 7734 auxType: auxInt32, 7735 argLen: 2, 7736 asm: arm.ARSC, 7737 reg: regInfo{ 7738 inputs: []inputInfo{ 7739 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7740 }, 7741 outputs: []outputInfo{ 7742 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7743 }, 7744 }, 7745 }, 7746 { 7747 name: "MULLU", 7748 argLen: 2, 7749 commutative: true, 7750 asm: arm.AMULLU, 7751 reg: regInfo{ 7752 inputs: []inputInfo{ 7753 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7754 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7755 }, 7756 outputs: []outputInfo{ 7757 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7758 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7759 }, 7760 }, 7761 }, 7762 { 7763 name: "MULA", 7764 argLen: 3, 7765 asm: arm.AMULA, 7766 reg: regInfo{ 7767 inputs: []inputInfo{ 7768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7769 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7770 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7771 }, 7772 outputs: []outputInfo{ 7773 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7774 }, 7775 }, 7776 }, 7777 { 7778 name: "ADDF", 7779 argLen: 2, 7780 commutative: true, 7781 asm: arm.AADDF, 7782 reg: regInfo{ 7783 inputs: []inputInfo{ 7784 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7785 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7786 }, 7787 outputs: []outputInfo{ 7788 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7789 }, 7790 }, 7791 }, 7792 { 7793 name: "ADDD", 7794 argLen: 2, 7795 commutative: true, 7796 asm: arm.AADDD, 7797 reg: regInfo{ 7798 inputs: []inputInfo{ 7799 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7800 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7801 }, 7802 outputs: []outputInfo{ 7803 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7804 }, 7805 }, 7806 }, 7807 { 7808 name: "SUBF", 7809 argLen: 2, 7810 asm: arm.ASUBF, 7811 reg: regInfo{ 7812 inputs: []inputInfo{ 7813 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7814 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7815 }, 7816 outputs: []outputInfo{ 7817 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7818 }, 7819 }, 7820 }, 7821 { 7822 name: "SUBD", 7823 argLen: 2, 7824 asm: arm.ASUBD, 7825 reg: regInfo{ 7826 inputs: []inputInfo{ 7827 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7828 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7829 }, 7830 outputs: []outputInfo{ 7831 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7832 }, 7833 }, 7834 }, 7835 { 7836 name: "MULF", 7837 argLen: 2, 7838 commutative: true, 7839 asm: arm.AMULF, 7840 reg: regInfo{ 7841 inputs: []inputInfo{ 7842 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7843 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7844 }, 7845 outputs: []outputInfo{ 7846 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7847 }, 7848 }, 7849 }, 7850 { 7851 name: "MULD", 7852 argLen: 2, 7853 commutative: true, 7854 asm: arm.AMULD, 7855 reg: regInfo{ 7856 inputs: []inputInfo{ 7857 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7858 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7859 }, 7860 outputs: []outputInfo{ 7861 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7862 }, 7863 }, 7864 }, 7865 { 7866 name: "DIVF", 7867 argLen: 2, 7868 asm: arm.ADIVF, 7869 reg: regInfo{ 7870 inputs: []inputInfo{ 7871 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7872 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7873 }, 7874 outputs: []outputInfo{ 7875 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7876 }, 7877 }, 7878 }, 7879 { 7880 name: "DIVD", 7881 argLen: 2, 7882 asm: arm.ADIVD, 7883 reg: regInfo{ 7884 inputs: []inputInfo{ 7885 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7886 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7887 }, 7888 outputs: []outputInfo{ 7889 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7890 }, 7891 }, 7892 }, 7893 { 7894 name: "AND", 7895 argLen: 2, 7896 commutative: true, 7897 asm: arm.AAND, 7898 reg: regInfo{ 7899 inputs: []inputInfo{ 7900 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7901 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7902 }, 7903 outputs: []outputInfo{ 7904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7905 }, 7906 }, 7907 }, 7908 { 7909 name: "ANDconst", 7910 auxType: auxInt32, 7911 argLen: 1, 7912 asm: arm.AAND, 7913 reg: regInfo{ 7914 inputs: []inputInfo{ 7915 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7916 }, 7917 outputs: []outputInfo{ 7918 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7919 }, 7920 }, 7921 }, 7922 { 7923 name: "OR", 7924 argLen: 2, 7925 commutative: true, 7926 asm: arm.AORR, 7927 reg: regInfo{ 7928 inputs: []inputInfo{ 7929 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7930 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7931 }, 7932 outputs: []outputInfo{ 7933 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7934 }, 7935 }, 7936 }, 7937 { 7938 name: "ORconst", 7939 auxType: auxInt32, 7940 argLen: 1, 7941 asm: arm.AORR, 7942 reg: regInfo{ 7943 inputs: []inputInfo{ 7944 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7945 }, 7946 outputs: []outputInfo{ 7947 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7948 }, 7949 }, 7950 }, 7951 { 7952 name: "XOR", 7953 argLen: 2, 7954 commutative: true, 7955 asm: arm.AEOR, 7956 reg: regInfo{ 7957 inputs: []inputInfo{ 7958 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7959 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7960 }, 7961 outputs: []outputInfo{ 7962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7963 }, 7964 }, 7965 }, 7966 { 7967 name: "XORconst", 7968 auxType: auxInt32, 7969 argLen: 1, 7970 asm: arm.AEOR, 7971 reg: regInfo{ 7972 inputs: []inputInfo{ 7973 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7974 }, 7975 outputs: []outputInfo{ 7976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7977 }, 7978 }, 7979 }, 7980 { 7981 name: "BIC", 7982 argLen: 2, 7983 asm: arm.ABIC, 7984 reg: regInfo{ 7985 inputs: []inputInfo{ 7986 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7987 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7988 }, 7989 outputs: []outputInfo{ 7990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7991 }, 7992 }, 7993 }, 7994 { 7995 name: "BICconst", 7996 auxType: auxInt32, 7997 argLen: 1, 7998 asm: arm.ABIC, 7999 reg: regInfo{ 8000 inputs: []inputInfo{ 8001 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8002 }, 8003 outputs: []outputInfo{ 8004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8005 }, 8006 }, 8007 }, 8008 { 8009 name: "MVN", 8010 argLen: 1, 8011 asm: arm.AMVN, 8012 reg: regInfo{ 8013 inputs: []inputInfo{ 8014 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8015 }, 8016 outputs: []outputInfo{ 8017 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8018 }, 8019 }, 8020 }, 8021 { 8022 name: "NEGF", 8023 argLen: 1, 8024 asm: arm.ANEGF, 8025 reg: regInfo{ 8026 inputs: []inputInfo{ 8027 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8028 }, 8029 outputs: []outputInfo{ 8030 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8031 }, 8032 }, 8033 }, 8034 { 8035 name: "NEGD", 8036 argLen: 1, 8037 asm: arm.ANEGD, 8038 reg: regInfo{ 8039 inputs: []inputInfo{ 8040 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8041 }, 8042 outputs: []outputInfo{ 8043 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8044 }, 8045 }, 8046 }, 8047 { 8048 name: "SQRTD", 8049 argLen: 1, 8050 asm: arm.ASQRTD, 8051 reg: regInfo{ 8052 inputs: []inputInfo{ 8053 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8054 }, 8055 outputs: []outputInfo{ 8056 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8057 }, 8058 }, 8059 }, 8060 { 8061 name: "CLZ", 8062 argLen: 1, 8063 asm: arm.ACLZ, 8064 reg: regInfo{ 8065 inputs: []inputInfo{ 8066 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8067 }, 8068 outputs: []outputInfo{ 8069 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8070 }, 8071 }, 8072 }, 8073 { 8074 name: "SLL", 8075 argLen: 2, 8076 asm: arm.ASLL, 8077 reg: regInfo{ 8078 inputs: []inputInfo{ 8079 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8080 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8081 }, 8082 outputs: []outputInfo{ 8083 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8084 }, 8085 }, 8086 }, 8087 { 8088 name: "SLLconst", 8089 auxType: auxInt32, 8090 argLen: 1, 8091 asm: arm.ASLL, 8092 reg: regInfo{ 8093 inputs: []inputInfo{ 8094 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8095 }, 8096 outputs: []outputInfo{ 8097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8098 }, 8099 }, 8100 }, 8101 { 8102 name: "SRL", 8103 argLen: 2, 8104 asm: arm.ASRL, 8105 reg: regInfo{ 8106 inputs: []inputInfo{ 8107 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8108 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8109 }, 8110 outputs: []outputInfo{ 8111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8112 }, 8113 }, 8114 }, 8115 { 8116 name: "SRLconst", 8117 auxType: auxInt32, 8118 argLen: 1, 8119 asm: arm.ASRL, 8120 reg: regInfo{ 8121 inputs: []inputInfo{ 8122 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8123 }, 8124 outputs: []outputInfo{ 8125 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8126 }, 8127 }, 8128 }, 8129 { 8130 name: "SRA", 8131 argLen: 2, 8132 asm: arm.ASRA, 8133 reg: regInfo{ 8134 inputs: []inputInfo{ 8135 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8136 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8137 }, 8138 outputs: []outputInfo{ 8139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8140 }, 8141 }, 8142 }, 8143 { 8144 name: "SRAconst", 8145 auxType: auxInt32, 8146 argLen: 1, 8147 asm: arm.ASRA, 8148 reg: regInfo{ 8149 inputs: []inputInfo{ 8150 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8151 }, 8152 outputs: []outputInfo{ 8153 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8154 }, 8155 }, 8156 }, 8157 { 8158 name: "SRRconst", 8159 auxType: auxInt32, 8160 argLen: 1, 8161 reg: regInfo{ 8162 inputs: []inputInfo{ 8163 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8164 }, 8165 outputs: []outputInfo{ 8166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8167 }, 8168 }, 8169 }, 8170 { 8171 name: "ADDshiftLL", 8172 auxType: auxInt32, 8173 argLen: 2, 8174 asm: arm.AADD, 8175 reg: regInfo{ 8176 inputs: []inputInfo{ 8177 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8178 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8179 }, 8180 outputs: []outputInfo{ 8181 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8182 }, 8183 }, 8184 }, 8185 { 8186 name: "ADDshiftRL", 8187 auxType: auxInt32, 8188 argLen: 2, 8189 asm: arm.AADD, 8190 reg: regInfo{ 8191 inputs: []inputInfo{ 8192 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8193 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8194 }, 8195 outputs: []outputInfo{ 8196 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8197 }, 8198 }, 8199 }, 8200 { 8201 name: "ADDshiftRA", 8202 auxType: auxInt32, 8203 argLen: 2, 8204 asm: arm.AADD, 8205 reg: regInfo{ 8206 inputs: []inputInfo{ 8207 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8208 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8209 }, 8210 outputs: []outputInfo{ 8211 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8212 }, 8213 }, 8214 }, 8215 { 8216 name: "SUBshiftLL", 8217 auxType: auxInt32, 8218 argLen: 2, 8219 asm: arm.ASUB, 8220 reg: regInfo{ 8221 inputs: []inputInfo{ 8222 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8223 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8224 }, 8225 outputs: []outputInfo{ 8226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8227 }, 8228 }, 8229 }, 8230 { 8231 name: "SUBshiftRL", 8232 auxType: auxInt32, 8233 argLen: 2, 8234 asm: arm.ASUB, 8235 reg: regInfo{ 8236 inputs: []inputInfo{ 8237 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8238 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8239 }, 8240 outputs: []outputInfo{ 8241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8242 }, 8243 }, 8244 }, 8245 { 8246 name: "SUBshiftRA", 8247 auxType: auxInt32, 8248 argLen: 2, 8249 asm: arm.ASUB, 8250 reg: regInfo{ 8251 inputs: []inputInfo{ 8252 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8253 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8254 }, 8255 outputs: []outputInfo{ 8256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8257 }, 8258 }, 8259 }, 8260 { 8261 name: "RSBshiftLL", 8262 auxType: auxInt32, 8263 argLen: 2, 8264 asm: arm.ARSB, 8265 reg: regInfo{ 8266 inputs: []inputInfo{ 8267 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8268 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8269 }, 8270 outputs: []outputInfo{ 8271 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8272 }, 8273 }, 8274 }, 8275 { 8276 name: "RSBshiftRL", 8277 auxType: auxInt32, 8278 argLen: 2, 8279 asm: arm.ARSB, 8280 reg: regInfo{ 8281 inputs: []inputInfo{ 8282 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8283 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8284 }, 8285 outputs: []outputInfo{ 8286 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8287 }, 8288 }, 8289 }, 8290 { 8291 name: "RSBshiftRA", 8292 auxType: auxInt32, 8293 argLen: 2, 8294 asm: arm.ARSB, 8295 reg: regInfo{ 8296 inputs: []inputInfo{ 8297 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8298 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8299 }, 8300 outputs: []outputInfo{ 8301 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8302 }, 8303 }, 8304 }, 8305 { 8306 name: "ANDshiftLL", 8307 auxType: auxInt32, 8308 argLen: 2, 8309 asm: arm.AAND, 8310 reg: regInfo{ 8311 inputs: []inputInfo{ 8312 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8313 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8314 }, 8315 outputs: []outputInfo{ 8316 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8317 }, 8318 }, 8319 }, 8320 { 8321 name: "ANDshiftRL", 8322 auxType: auxInt32, 8323 argLen: 2, 8324 asm: arm.AAND, 8325 reg: regInfo{ 8326 inputs: []inputInfo{ 8327 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8328 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8329 }, 8330 outputs: []outputInfo{ 8331 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8332 }, 8333 }, 8334 }, 8335 { 8336 name: "ANDshiftRA", 8337 auxType: auxInt32, 8338 argLen: 2, 8339 asm: arm.AAND, 8340 reg: regInfo{ 8341 inputs: []inputInfo{ 8342 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8343 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8344 }, 8345 outputs: []outputInfo{ 8346 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8347 }, 8348 }, 8349 }, 8350 { 8351 name: "ORshiftLL", 8352 auxType: auxInt32, 8353 argLen: 2, 8354 asm: arm.AORR, 8355 reg: regInfo{ 8356 inputs: []inputInfo{ 8357 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8358 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8359 }, 8360 outputs: []outputInfo{ 8361 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8362 }, 8363 }, 8364 }, 8365 { 8366 name: "ORshiftRL", 8367 auxType: auxInt32, 8368 argLen: 2, 8369 asm: arm.AORR, 8370 reg: regInfo{ 8371 inputs: []inputInfo{ 8372 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8373 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8374 }, 8375 outputs: []outputInfo{ 8376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8377 }, 8378 }, 8379 }, 8380 { 8381 name: "ORshiftRA", 8382 auxType: auxInt32, 8383 argLen: 2, 8384 asm: arm.AORR, 8385 reg: regInfo{ 8386 inputs: []inputInfo{ 8387 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8388 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8389 }, 8390 outputs: []outputInfo{ 8391 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8392 }, 8393 }, 8394 }, 8395 { 8396 name: "XORshiftLL", 8397 auxType: auxInt32, 8398 argLen: 2, 8399 asm: arm.AEOR, 8400 reg: regInfo{ 8401 inputs: []inputInfo{ 8402 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8403 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8404 }, 8405 outputs: []outputInfo{ 8406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8407 }, 8408 }, 8409 }, 8410 { 8411 name: "XORshiftRL", 8412 auxType: auxInt32, 8413 argLen: 2, 8414 asm: arm.AEOR, 8415 reg: regInfo{ 8416 inputs: []inputInfo{ 8417 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8418 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8419 }, 8420 outputs: []outputInfo{ 8421 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8422 }, 8423 }, 8424 }, 8425 { 8426 name: "XORshiftRA", 8427 auxType: auxInt32, 8428 argLen: 2, 8429 asm: arm.AEOR, 8430 reg: regInfo{ 8431 inputs: []inputInfo{ 8432 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8433 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8434 }, 8435 outputs: []outputInfo{ 8436 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8437 }, 8438 }, 8439 }, 8440 { 8441 name: "XORshiftRR", 8442 auxType: auxInt32, 8443 argLen: 2, 8444 asm: arm.AEOR, 8445 reg: regInfo{ 8446 inputs: []inputInfo{ 8447 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8448 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8449 }, 8450 outputs: []outputInfo{ 8451 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8452 }, 8453 }, 8454 }, 8455 { 8456 name: "BICshiftLL", 8457 auxType: auxInt32, 8458 argLen: 2, 8459 asm: arm.ABIC, 8460 reg: regInfo{ 8461 inputs: []inputInfo{ 8462 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8463 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8464 }, 8465 outputs: []outputInfo{ 8466 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8467 }, 8468 }, 8469 }, 8470 { 8471 name: "BICshiftRL", 8472 auxType: auxInt32, 8473 argLen: 2, 8474 asm: arm.ABIC, 8475 reg: regInfo{ 8476 inputs: []inputInfo{ 8477 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8478 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8479 }, 8480 outputs: []outputInfo{ 8481 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8482 }, 8483 }, 8484 }, 8485 { 8486 name: "BICshiftRA", 8487 auxType: auxInt32, 8488 argLen: 2, 8489 asm: arm.ABIC, 8490 reg: regInfo{ 8491 inputs: []inputInfo{ 8492 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8493 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8494 }, 8495 outputs: []outputInfo{ 8496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8497 }, 8498 }, 8499 }, 8500 { 8501 name: "MVNshiftLL", 8502 auxType: auxInt32, 8503 argLen: 1, 8504 asm: arm.AMVN, 8505 reg: regInfo{ 8506 inputs: []inputInfo{ 8507 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8508 }, 8509 outputs: []outputInfo{ 8510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8511 }, 8512 }, 8513 }, 8514 { 8515 name: "MVNshiftRL", 8516 auxType: auxInt32, 8517 argLen: 1, 8518 asm: arm.AMVN, 8519 reg: regInfo{ 8520 inputs: []inputInfo{ 8521 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8522 }, 8523 outputs: []outputInfo{ 8524 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8525 }, 8526 }, 8527 }, 8528 { 8529 name: "MVNshiftRA", 8530 auxType: auxInt32, 8531 argLen: 1, 8532 asm: arm.AMVN, 8533 reg: regInfo{ 8534 inputs: []inputInfo{ 8535 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8536 }, 8537 outputs: []outputInfo{ 8538 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8539 }, 8540 }, 8541 }, 8542 { 8543 name: "ADCshiftLL", 8544 auxType: auxInt32, 8545 argLen: 3, 8546 asm: arm.AADC, 8547 reg: regInfo{ 8548 inputs: []inputInfo{ 8549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8550 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8551 }, 8552 outputs: []outputInfo{ 8553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8554 }, 8555 }, 8556 }, 8557 { 8558 name: "ADCshiftRL", 8559 auxType: auxInt32, 8560 argLen: 3, 8561 asm: arm.AADC, 8562 reg: regInfo{ 8563 inputs: []inputInfo{ 8564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8565 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8566 }, 8567 outputs: []outputInfo{ 8568 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8569 }, 8570 }, 8571 }, 8572 { 8573 name: "ADCshiftRA", 8574 auxType: auxInt32, 8575 argLen: 3, 8576 asm: arm.AADC, 8577 reg: regInfo{ 8578 inputs: []inputInfo{ 8579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8580 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8581 }, 8582 outputs: []outputInfo{ 8583 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8584 }, 8585 }, 8586 }, 8587 { 8588 name: "SBCshiftLL", 8589 auxType: auxInt32, 8590 argLen: 3, 8591 asm: arm.ASBC, 8592 reg: regInfo{ 8593 inputs: []inputInfo{ 8594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8595 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8596 }, 8597 outputs: []outputInfo{ 8598 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8599 }, 8600 }, 8601 }, 8602 { 8603 name: "SBCshiftRL", 8604 auxType: auxInt32, 8605 argLen: 3, 8606 asm: arm.ASBC, 8607 reg: regInfo{ 8608 inputs: []inputInfo{ 8609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8610 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8611 }, 8612 outputs: []outputInfo{ 8613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8614 }, 8615 }, 8616 }, 8617 { 8618 name: "SBCshiftRA", 8619 auxType: auxInt32, 8620 argLen: 3, 8621 asm: arm.ASBC, 8622 reg: regInfo{ 8623 inputs: []inputInfo{ 8624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8625 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8626 }, 8627 outputs: []outputInfo{ 8628 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8629 }, 8630 }, 8631 }, 8632 { 8633 name: "RSCshiftLL", 8634 auxType: auxInt32, 8635 argLen: 3, 8636 asm: arm.ARSC, 8637 reg: regInfo{ 8638 inputs: []inputInfo{ 8639 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8640 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8641 }, 8642 outputs: []outputInfo{ 8643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8644 }, 8645 }, 8646 }, 8647 { 8648 name: "RSCshiftRL", 8649 auxType: auxInt32, 8650 argLen: 3, 8651 asm: arm.ARSC, 8652 reg: regInfo{ 8653 inputs: []inputInfo{ 8654 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8655 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8656 }, 8657 outputs: []outputInfo{ 8658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8659 }, 8660 }, 8661 }, 8662 { 8663 name: "RSCshiftRA", 8664 auxType: auxInt32, 8665 argLen: 3, 8666 asm: arm.ARSC, 8667 reg: regInfo{ 8668 inputs: []inputInfo{ 8669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8670 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8671 }, 8672 outputs: []outputInfo{ 8673 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8674 }, 8675 }, 8676 }, 8677 { 8678 name: "ADDSshiftLL", 8679 auxType: auxInt32, 8680 argLen: 2, 8681 asm: arm.AADD, 8682 reg: regInfo{ 8683 inputs: []inputInfo{ 8684 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8685 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8686 }, 8687 outputs: []outputInfo{ 8688 {1, 0}, 8689 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8690 }, 8691 }, 8692 }, 8693 { 8694 name: "ADDSshiftRL", 8695 auxType: auxInt32, 8696 argLen: 2, 8697 asm: arm.AADD, 8698 reg: regInfo{ 8699 inputs: []inputInfo{ 8700 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8701 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8702 }, 8703 outputs: []outputInfo{ 8704 {1, 0}, 8705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8706 }, 8707 }, 8708 }, 8709 { 8710 name: "ADDSshiftRA", 8711 auxType: auxInt32, 8712 argLen: 2, 8713 asm: arm.AADD, 8714 reg: regInfo{ 8715 inputs: []inputInfo{ 8716 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8717 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8718 }, 8719 outputs: []outputInfo{ 8720 {1, 0}, 8721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8722 }, 8723 }, 8724 }, 8725 { 8726 name: "SUBSshiftLL", 8727 auxType: auxInt32, 8728 argLen: 2, 8729 asm: arm.ASUB, 8730 reg: regInfo{ 8731 inputs: []inputInfo{ 8732 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8733 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8734 }, 8735 outputs: []outputInfo{ 8736 {1, 0}, 8737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8738 }, 8739 }, 8740 }, 8741 { 8742 name: "SUBSshiftRL", 8743 auxType: auxInt32, 8744 argLen: 2, 8745 asm: arm.ASUB, 8746 reg: regInfo{ 8747 inputs: []inputInfo{ 8748 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8749 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8750 }, 8751 outputs: []outputInfo{ 8752 {1, 0}, 8753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8754 }, 8755 }, 8756 }, 8757 { 8758 name: "SUBSshiftRA", 8759 auxType: auxInt32, 8760 argLen: 2, 8761 asm: arm.ASUB, 8762 reg: regInfo{ 8763 inputs: []inputInfo{ 8764 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8765 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8766 }, 8767 outputs: []outputInfo{ 8768 {1, 0}, 8769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8770 }, 8771 }, 8772 }, 8773 { 8774 name: "RSBSshiftLL", 8775 auxType: auxInt32, 8776 argLen: 2, 8777 asm: arm.ARSB, 8778 reg: regInfo{ 8779 inputs: []inputInfo{ 8780 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8781 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8782 }, 8783 outputs: []outputInfo{ 8784 {1, 0}, 8785 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8786 }, 8787 }, 8788 }, 8789 { 8790 name: "RSBSshiftRL", 8791 auxType: auxInt32, 8792 argLen: 2, 8793 asm: arm.ARSB, 8794 reg: regInfo{ 8795 inputs: []inputInfo{ 8796 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8797 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8798 }, 8799 outputs: []outputInfo{ 8800 {1, 0}, 8801 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8802 }, 8803 }, 8804 }, 8805 { 8806 name: "RSBSshiftRA", 8807 auxType: auxInt32, 8808 argLen: 2, 8809 asm: arm.ARSB, 8810 reg: regInfo{ 8811 inputs: []inputInfo{ 8812 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8813 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8814 }, 8815 outputs: []outputInfo{ 8816 {1, 0}, 8817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8818 }, 8819 }, 8820 }, 8821 { 8822 name: "ADDshiftLLreg", 8823 argLen: 3, 8824 asm: arm.AADD, 8825 reg: regInfo{ 8826 inputs: []inputInfo{ 8827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8828 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8829 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8830 }, 8831 outputs: []outputInfo{ 8832 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8833 }, 8834 }, 8835 }, 8836 { 8837 name: "ADDshiftRLreg", 8838 argLen: 3, 8839 asm: arm.AADD, 8840 reg: regInfo{ 8841 inputs: []inputInfo{ 8842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8843 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8844 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8845 }, 8846 outputs: []outputInfo{ 8847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8848 }, 8849 }, 8850 }, 8851 { 8852 name: "ADDshiftRAreg", 8853 argLen: 3, 8854 asm: arm.AADD, 8855 reg: regInfo{ 8856 inputs: []inputInfo{ 8857 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8858 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8859 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8860 }, 8861 outputs: []outputInfo{ 8862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8863 }, 8864 }, 8865 }, 8866 { 8867 name: "SUBshiftLLreg", 8868 argLen: 3, 8869 asm: arm.ASUB, 8870 reg: regInfo{ 8871 inputs: []inputInfo{ 8872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8873 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8874 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8875 }, 8876 outputs: []outputInfo{ 8877 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8878 }, 8879 }, 8880 }, 8881 { 8882 name: "SUBshiftRLreg", 8883 argLen: 3, 8884 asm: arm.ASUB, 8885 reg: regInfo{ 8886 inputs: []inputInfo{ 8887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8888 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8889 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8890 }, 8891 outputs: []outputInfo{ 8892 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8893 }, 8894 }, 8895 }, 8896 { 8897 name: "SUBshiftRAreg", 8898 argLen: 3, 8899 asm: arm.ASUB, 8900 reg: regInfo{ 8901 inputs: []inputInfo{ 8902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8903 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8904 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8905 }, 8906 outputs: []outputInfo{ 8907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8908 }, 8909 }, 8910 }, 8911 { 8912 name: "RSBshiftLLreg", 8913 argLen: 3, 8914 asm: arm.ARSB, 8915 reg: regInfo{ 8916 inputs: []inputInfo{ 8917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8918 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8919 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8920 }, 8921 outputs: []outputInfo{ 8922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8923 }, 8924 }, 8925 }, 8926 { 8927 name: "RSBshiftRLreg", 8928 argLen: 3, 8929 asm: arm.ARSB, 8930 reg: regInfo{ 8931 inputs: []inputInfo{ 8932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8933 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8934 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8935 }, 8936 outputs: []outputInfo{ 8937 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8938 }, 8939 }, 8940 }, 8941 { 8942 name: "RSBshiftRAreg", 8943 argLen: 3, 8944 asm: arm.ARSB, 8945 reg: regInfo{ 8946 inputs: []inputInfo{ 8947 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8948 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8949 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8950 }, 8951 outputs: []outputInfo{ 8952 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8953 }, 8954 }, 8955 }, 8956 { 8957 name: "ANDshiftLLreg", 8958 argLen: 3, 8959 asm: arm.AAND, 8960 reg: regInfo{ 8961 inputs: []inputInfo{ 8962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8963 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8964 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8965 }, 8966 outputs: []outputInfo{ 8967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8968 }, 8969 }, 8970 }, 8971 { 8972 name: "ANDshiftRLreg", 8973 argLen: 3, 8974 asm: arm.AAND, 8975 reg: regInfo{ 8976 inputs: []inputInfo{ 8977 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8978 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8979 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8980 }, 8981 outputs: []outputInfo{ 8982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8983 }, 8984 }, 8985 }, 8986 { 8987 name: "ANDshiftRAreg", 8988 argLen: 3, 8989 asm: arm.AAND, 8990 reg: regInfo{ 8991 inputs: []inputInfo{ 8992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8993 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8994 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8995 }, 8996 outputs: []outputInfo{ 8997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8998 }, 8999 }, 9000 }, 9001 { 9002 name: "ORshiftLLreg", 9003 argLen: 3, 9004 asm: arm.AORR, 9005 reg: regInfo{ 9006 inputs: []inputInfo{ 9007 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9008 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9009 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9010 }, 9011 outputs: []outputInfo{ 9012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9013 }, 9014 }, 9015 }, 9016 { 9017 name: "ORshiftRLreg", 9018 argLen: 3, 9019 asm: arm.AORR, 9020 reg: regInfo{ 9021 inputs: []inputInfo{ 9022 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9023 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9024 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9025 }, 9026 outputs: []outputInfo{ 9027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9028 }, 9029 }, 9030 }, 9031 { 9032 name: "ORshiftRAreg", 9033 argLen: 3, 9034 asm: arm.AORR, 9035 reg: regInfo{ 9036 inputs: []inputInfo{ 9037 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9038 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9039 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9040 }, 9041 outputs: []outputInfo{ 9042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9043 }, 9044 }, 9045 }, 9046 { 9047 name: "XORshiftLLreg", 9048 argLen: 3, 9049 asm: arm.AEOR, 9050 reg: regInfo{ 9051 inputs: []inputInfo{ 9052 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9053 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9054 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9055 }, 9056 outputs: []outputInfo{ 9057 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9058 }, 9059 }, 9060 }, 9061 { 9062 name: "XORshiftRLreg", 9063 argLen: 3, 9064 asm: arm.AEOR, 9065 reg: regInfo{ 9066 inputs: []inputInfo{ 9067 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9068 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9069 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9070 }, 9071 outputs: []outputInfo{ 9072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9073 }, 9074 }, 9075 }, 9076 { 9077 name: "XORshiftRAreg", 9078 argLen: 3, 9079 asm: arm.AEOR, 9080 reg: regInfo{ 9081 inputs: []inputInfo{ 9082 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9083 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9084 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9085 }, 9086 outputs: []outputInfo{ 9087 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9088 }, 9089 }, 9090 }, 9091 { 9092 name: "BICshiftLLreg", 9093 argLen: 3, 9094 asm: arm.ABIC, 9095 reg: regInfo{ 9096 inputs: []inputInfo{ 9097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9098 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9099 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9100 }, 9101 outputs: []outputInfo{ 9102 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9103 }, 9104 }, 9105 }, 9106 { 9107 name: "BICshiftRLreg", 9108 argLen: 3, 9109 asm: arm.ABIC, 9110 reg: regInfo{ 9111 inputs: []inputInfo{ 9112 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9113 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9114 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9115 }, 9116 outputs: []outputInfo{ 9117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9118 }, 9119 }, 9120 }, 9121 { 9122 name: "BICshiftRAreg", 9123 argLen: 3, 9124 asm: arm.ABIC, 9125 reg: regInfo{ 9126 inputs: []inputInfo{ 9127 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9128 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9129 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9130 }, 9131 outputs: []outputInfo{ 9132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9133 }, 9134 }, 9135 }, 9136 { 9137 name: "MVNshiftLLreg", 9138 argLen: 2, 9139 asm: arm.AMVN, 9140 reg: regInfo{ 9141 inputs: []inputInfo{ 9142 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9143 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9144 }, 9145 outputs: []outputInfo{ 9146 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9147 }, 9148 }, 9149 }, 9150 { 9151 name: "MVNshiftRLreg", 9152 argLen: 2, 9153 asm: arm.AMVN, 9154 reg: regInfo{ 9155 inputs: []inputInfo{ 9156 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9157 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9158 }, 9159 outputs: []outputInfo{ 9160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9161 }, 9162 }, 9163 }, 9164 { 9165 name: "MVNshiftRAreg", 9166 argLen: 2, 9167 asm: arm.AMVN, 9168 reg: regInfo{ 9169 inputs: []inputInfo{ 9170 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9171 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9172 }, 9173 outputs: []outputInfo{ 9174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9175 }, 9176 }, 9177 }, 9178 { 9179 name: "ADCshiftLLreg", 9180 argLen: 4, 9181 asm: arm.AADC, 9182 reg: regInfo{ 9183 inputs: []inputInfo{ 9184 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9185 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9186 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9187 }, 9188 outputs: []outputInfo{ 9189 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9190 }, 9191 }, 9192 }, 9193 { 9194 name: "ADCshiftRLreg", 9195 argLen: 4, 9196 asm: arm.AADC, 9197 reg: regInfo{ 9198 inputs: []inputInfo{ 9199 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9200 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9201 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9202 }, 9203 outputs: []outputInfo{ 9204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9205 }, 9206 }, 9207 }, 9208 { 9209 name: "ADCshiftRAreg", 9210 argLen: 4, 9211 asm: arm.AADC, 9212 reg: regInfo{ 9213 inputs: []inputInfo{ 9214 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9215 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9216 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9217 }, 9218 outputs: []outputInfo{ 9219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9220 }, 9221 }, 9222 }, 9223 { 9224 name: "SBCshiftLLreg", 9225 argLen: 4, 9226 asm: arm.ASBC, 9227 reg: regInfo{ 9228 inputs: []inputInfo{ 9229 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9230 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9231 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9232 }, 9233 outputs: []outputInfo{ 9234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9235 }, 9236 }, 9237 }, 9238 { 9239 name: "SBCshiftRLreg", 9240 argLen: 4, 9241 asm: arm.ASBC, 9242 reg: regInfo{ 9243 inputs: []inputInfo{ 9244 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9245 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9246 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9247 }, 9248 outputs: []outputInfo{ 9249 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9250 }, 9251 }, 9252 }, 9253 { 9254 name: "SBCshiftRAreg", 9255 argLen: 4, 9256 asm: arm.ASBC, 9257 reg: regInfo{ 9258 inputs: []inputInfo{ 9259 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9260 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9261 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9262 }, 9263 outputs: []outputInfo{ 9264 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9265 }, 9266 }, 9267 }, 9268 { 9269 name: "RSCshiftLLreg", 9270 argLen: 4, 9271 asm: arm.ARSC, 9272 reg: regInfo{ 9273 inputs: []inputInfo{ 9274 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9275 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9276 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9277 }, 9278 outputs: []outputInfo{ 9279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9280 }, 9281 }, 9282 }, 9283 { 9284 name: "RSCshiftRLreg", 9285 argLen: 4, 9286 asm: arm.ARSC, 9287 reg: regInfo{ 9288 inputs: []inputInfo{ 9289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9290 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9291 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9292 }, 9293 outputs: []outputInfo{ 9294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9295 }, 9296 }, 9297 }, 9298 { 9299 name: "RSCshiftRAreg", 9300 argLen: 4, 9301 asm: arm.ARSC, 9302 reg: regInfo{ 9303 inputs: []inputInfo{ 9304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9305 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9306 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9307 }, 9308 outputs: []outputInfo{ 9309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9310 }, 9311 }, 9312 }, 9313 { 9314 name: "ADDSshiftLLreg", 9315 argLen: 3, 9316 asm: arm.AADD, 9317 reg: regInfo{ 9318 inputs: []inputInfo{ 9319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9320 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9321 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9322 }, 9323 outputs: []outputInfo{ 9324 {1, 0}, 9325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9326 }, 9327 }, 9328 }, 9329 { 9330 name: "ADDSshiftRLreg", 9331 argLen: 3, 9332 asm: arm.AADD, 9333 reg: regInfo{ 9334 inputs: []inputInfo{ 9335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9336 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9337 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9338 }, 9339 outputs: []outputInfo{ 9340 {1, 0}, 9341 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9342 }, 9343 }, 9344 }, 9345 { 9346 name: "ADDSshiftRAreg", 9347 argLen: 3, 9348 asm: arm.AADD, 9349 reg: regInfo{ 9350 inputs: []inputInfo{ 9351 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9352 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9353 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9354 }, 9355 outputs: []outputInfo{ 9356 {1, 0}, 9357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9358 }, 9359 }, 9360 }, 9361 { 9362 name: "SUBSshiftLLreg", 9363 argLen: 3, 9364 asm: arm.ASUB, 9365 reg: regInfo{ 9366 inputs: []inputInfo{ 9367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9368 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9369 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9370 }, 9371 outputs: []outputInfo{ 9372 {1, 0}, 9373 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9374 }, 9375 }, 9376 }, 9377 { 9378 name: "SUBSshiftRLreg", 9379 argLen: 3, 9380 asm: arm.ASUB, 9381 reg: regInfo{ 9382 inputs: []inputInfo{ 9383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9384 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9385 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9386 }, 9387 outputs: []outputInfo{ 9388 {1, 0}, 9389 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9390 }, 9391 }, 9392 }, 9393 { 9394 name: "SUBSshiftRAreg", 9395 argLen: 3, 9396 asm: arm.ASUB, 9397 reg: regInfo{ 9398 inputs: []inputInfo{ 9399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9400 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9401 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9402 }, 9403 outputs: []outputInfo{ 9404 {1, 0}, 9405 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9406 }, 9407 }, 9408 }, 9409 { 9410 name: "RSBSshiftLLreg", 9411 argLen: 3, 9412 asm: arm.ARSB, 9413 reg: regInfo{ 9414 inputs: []inputInfo{ 9415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9416 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9417 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9418 }, 9419 outputs: []outputInfo{ 9420 {1, 0}, 9421 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9422 }, 9423 }, 9424 }, 9425 { 9426 name: "RSBSshiftRLreg", 9427 argLen: 3, 9428 asm: arm.ARSB, 9429 reg: regInfo{ 9430 inputs: []inputInfo{ 9431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9432 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9433 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9434 }, 9435 outputs: []outputInfo{ 9436 {1, 0}, 9437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9438 }, 9439 }, 9440 }, 9441 { 9442 name: "RSBSshiftRAreg", 9443 argLen: 3, 9444 asm: arm.ARSB, 9445 reg: regInfo{ 9446 inputs: []inputInfo{ 9447 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9448 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9449 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9450 }, 9451 outputs: []outputInfo{ 9452 {1, 0}, 9453 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9454 }, 9455 }, 9456 }, 9457 { 9458 name: "CMP", 9459 argLen: 2, 9460 asm: arm.ACMP, 9461 reg: regInfo{ 9462 inputs: []inputInfo{ 9463 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9464 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9465 }, 9466 }, 9467 }, 9468 { 9469 name: "CMPconst", 9470 auxType: auxInt32, 9471 argLen: 1, 9472 asm: arm.ACMP, 9473 reg: regInfo{ 9474 inputs: []inputInfo{ 9475 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9476 }, 9477 }, 9478 }, 9479 { 9480 name: "CMN", 9481 argLen: 2, 9482 asm: arm.ACMN, 9483 reg: regInfo{ 9484 inputs: []inputInfo{ 9485 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9486 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9487 }, 9488 }, 9489 }, 9490 { 9491 name: "CMNconst", 9492 auxType: auxInt32, 9493 argLen: 1, 9494 asm: arm.ACMN, 9495 reg: regInfo{ 9496 inputs: []inputInfo{ 9497 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9498 }, 9499 }, 9500 }, 9501 { 9502 name: "TST", 9503 argLen: 2, 9504 commutative: true, 9505 asm: arm.ATST, 9506 reg: regInfo{ 9507 inputs: []inputInfo{ 9508 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9509 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9510 }, 9511 }, 9512 }, 9513 { 9514 name: "TSTconst", 9515 auxType: auxInt32, 9516 argLen: 1, 9517 asm: arm.ATST, 9518 reg: regInfo{ 9519 inputs: []inputInfo{ 9520 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9521 }, 9522 }, 9523 }, 9524 { 9525 name: "TEQ", 9526 argLen: 2, 9527 commutative: true, 9528 asm: arm.ATEQ, 9529 reg: regInfo{ 9530 inputs: []inputInfo{ 9531 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9532 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9533 }, 9534 }, 9535 }, 9536 { 9537 name: "TEQconst", 9538 auxType: auxInt32, 9539 argLen: 1, 9540 asm: arm.ATEQ, 9541 reg: regInfo{ 9542 inputs: []inputInfo{ 9543 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9544 }, 9545 }, 9546 }, 9547 { 9548 name: "CMPF", 9549 argLen: 2, 9550 asm: arm.ACMPF, 9551 reg: regInfo{ 9552 inputs: []inputInfo{ 9553 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9554 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9555 }, 9556 }, 9557 }, 9558 { 9559 name: "CMPD", 9560 argLen: 2, 9561 asm: arm.ACMPD, 9562 reg: regInfo{ 9563 inputs: []inputInfo{ 9564 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9565 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9566 }, 9567 }, 9568 }, 9569 { 9570 name: "CMPshiftLL", 9571 auxType: auxInt32, 9572 argLen: 2, 9573 asm: arm.ACMP, 9574 reg: regInfo{ 9575 inputs: []inputInfo{ 9576 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9577 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9578 }, 9579 }, 9580 }, 9581 { 9582 name: "CMPshiftRL", 9583 auxType: auxInt32, 9584 argLen: 2, 9585 asm: arm.ACMP, 9586 reg: regInfo{ 9587 inputs: []inputInfo{ 9588 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9589 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9590 }, 9591 }, 9592 }, 9593 { 9594 name: "CMPshiftRA", 9595 auxType: auxInt32, 9596 argLen: 2, 9597 asm: arm.ACMP, 9598 reg: regInfo{ 9599 inputs: []inputInfo{ 9600 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9601 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9602 }, 9603 }, 9604 }, 9605 { 9606 name: "CMPshiftLLreg", 9607 argLen: 3, 9608 asm: arm.ACMP, 9609 reg: regInfo{ 9610 inputs: []inputInfo{ 9611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9612 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9613 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9614 }, 9615 }, 9616 }, 9617 { 9618 name: "CMPshiftRLreg", 9619 argLen: 3, 9620 asm: arm.ACMP, 9621 reg: regInfo{ 9622 inputs: []inputInfo{ 9623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9624 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9625 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9626 }, 9627 }, 9628 }, 9629 { 9630 name: "CMPshiftRAreg", 9631 argLen: 3, 9632 asm: arm.ACMP, 9633 reg: regInfo{ 9634 inputs: []inputInfo{ 9635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9636 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9637 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9638 }, 9639 }, 9640 }, 9641 { 9642 name: "CMPF0", 9643 argLen: 1, 9644 asm: arm.ACMPF, 9645 reg: regInfo{ 9646 inputs: []inputInfo{ 9647 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9648 }, 9649 }, 9650 }, 9651 { 9652 name: "CMPD0", 9653 argLen: 1, 9654 asm: arm.ACMPD, 9655 reg: regInfo{ 9656 inputs: []inputInfo{ 9657 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9658 }, 9659 }, 9660 }, 9661 { 9662 name: "MOVWconst", 9663 auxType: auxInt32, 9664 argLen: 0, 9665 rematerializeable: true, 9666 asm: arm.AMOVW, 9667 reg: regInfo{ 9668 outputs: []outputInfo{ 9669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9670 }, 9671 }, 9672 }, 9673 { 9674 name: "MOVFconst", 9675 auxType: auxFloat64, 9676 argLen: 0, 9677 rematerializeable: true, 9678 asm: arm.AMOVF, 9679 reg: regInfo{ 9680 outputs: []outputInfo{ 9681 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9682 }, 9683 }, 9684 }, 9685 { 9686 name: "MOVDconst", 9687 auxType: auxFloat64, 9688 argLen: 0, 9689 rematerializeable: true, 9690 asm: arm.AMOVD, 9691 reg: regInfo{ 9692 outputs: []outputInfo{ 9693 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9694 }, 9695 }, 9696 }, 9697 { 9698 name: "MOVWaddr", 9699 auxType: auxSymOff, 9700 argLen: 1, 9701 rematerializeable: true, 9702 asm: arm.AMOVW, 9703 reg: regInfo{ 9704 inputs: []inputInfo{ 9705 {0, 4294975488}, // SP SB 9706 }, 9707 outputs: []outputInfo{ 9708 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9709 }, 9710 }, 9711 }, 9712 { 9713 name: "MOVBload", 9714 auxType: auxSymOff, 9715 argLen: 2, 9716 faultOnNilArg0: true, 9717 asm: arm.AMOVB, 9718 reg: regInfo{ 9719 inputs: []inputInfo{ 9720 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9721 }, 9722 outputs: []outputInfo{ 9723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9724 }, 9725 }, 9726 }, 9727 { 9728 name: "MOVBUload", 9729 auxType: auxSymOff, 9730 argLen: 2, 9731 faultOnNilArg0: true, 9732 asm: arm.AMOVBU, 9733 reg: regInfo{ 9734 inputs: []inputInfo{ 9735 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9736 }, 9737 outputs: []outputInfo{ 9738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9739 }, 9740 }, 9741 }, 9742 { 9743 name: "MOVHload", 9744 auxType: auxSymOff, 9745 argLen: 2, 9746 faultOnNilArg0: true, 9747 asm: arm.AMOVH, 9748 reg: regInfo{ 9749 inputs: []inputInfo{ 9750 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9751 }, 9752 outputs: []outputInfo{ 9753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9754 }, 9755 }, 9756 }, 9757 { 9758 name: "MOVHUload", 9759 auxType: auxSymOff, 9760 argLen: 2, 9761 faultOnNilArg0: true, 9762 asm: arm.AMOVHU, 9763 reg: regInfo{ 9764 inputs: []inputInfo{ 9765 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9766 }, 9767 outputs: []outputInfo{ 9768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9769 }, 9770 }, 9771 }, 9772 { 9773 name: "MOVWload", 9774 auxType: auxSymOff, 9775 argLen: 2, 9776 faultOnNilArg0: true, 9777 asm: arm.AMOVW, 9778 reg: regInfo{ 9779 inputs: []inputInfo{ 9780 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9781 }, 9782 outputs: []outputInfo{ 9783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9784 }, 9785 }, 9786 }, 9787 { 9788 name: "MOVFload", 9789 auxType: auxSymOff, 9790 argLen: 2, 9791 faultOnNilArg0: true, 9792 asm: arm.AMOVF, 9793 reg: regInfo{ 9794 inputs: []inputInfo{ 9795 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9796 }, 9797 outputs: []outputInfo{ 9798 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9799 }, 9800 }, 9801 }, 9802 { 9803 name: "MOVDload", 9804 auxType: auxSymOff, 9805 argLen: 2, 9806 faultOnNilArg0: true, 9807 asm: arm.AMOVD, 9808 reg: regInfo{ 9809 inputs: []inputInfo{ 9810 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9811 }, 9812 outputs: []outputInfo{ 9813 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9814 }, 9815 }, 9816 }, 9817 { 9818 name: "MOVBstore", 9819 auxType: auxSymOff, 9820 argLen: 3, 9821 faultOnNilArg0: true, 9822 asm: arm.AMOVB, 9823 reg: regInfo{ 9824 inputs: []inputInfo{ 9825 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9826 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9827 }, 9828 }, 9829 }, 9830 { 9831 name: "MOVHstore", 9832 auxType: auxSymOff, 9833 argLen: 3, 9834 faultOnNilArg0: true, 9835 asm: arm.AMOVH, 9836 reg: regInfo{ 9837 inputs: []inputInfo{ 9838 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9839 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9840 }, 9841 }, 9842 }, 9843 { 9844 name: "MOVWstore", 9845 auxType: auxSymOff, 9846 argLen: 3, 9847 faultOnNilArg0: true, 9848 asm: arm.AMOVW, 9849 reg: regInfo{ 9850 inputs: []inputInfo{ 9851 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9852 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9853 }, 9854 }, 9855 }, 9856 { 9857 name: "MOVFstore", 9858 auxType: auxSymOff, 9859 argLen: 3, 9860 faultOnNilArg0: true, 9861 asm: arm.AMOVF, 9862 reg: regInfo{ 9863 inputs: []inputInfo{ 9864 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9865 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9866 }, 9867 }, 9868 }, 9869 { 9870 name: "MOVDstore", 9871 auxType: auxSymOff, 9872 argLen: 3, 9873 faultOnNilArg0: true, 9874 asm: arm.AMOVD, 9875 reg: regInfo{ 9876 inputs: []inputInfo{ 9877 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9878 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9879 }, 9880 }, 9881 }, 9882 { 9883 name: "MOVWloadidx", 9884 argLen: 3, 9885 asm: arm.AMOVW, 9886 reg: regInfo{ 9887 inputs: []inputInfo{ 9888 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9889 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9890 }, 9891 outputs: []outputInfo{ 9892 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9893 }, 9894 }, 9895 }, 9896 { 9897 name: "MOVWloadshiftLL", 9898 auxType: auxInt32, 9899 argLen: 3, 9900 asm: arm.AMOVW, 9901 reg: regInfo{ 9902 inputs: []inputInfo{ 9903 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9904 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9905 }, 9906 outputs: []outputInfo{ 9907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9908 }, 9909 }, 9910 }, 9911 { 9912 name: "MOVWloadshiftRL", 9913 auxType: auxInt32, 9914 argLen: 3, 9915 asm: arm.AMOVW, 9916 reg: regInfo{ 9917 inputs: []inputInfo{ 9918 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9919 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9920 }, 9921 outputs: []outputInfo{ 9922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9923 }, 9924 }, 9925 }, 9926 { 9927 name: "MOVWloadshiftRA", 9928 auxType: auxInt32, 9929 argLen: 3, 9930 asm: arm.AMOVW, 9931 reg: regInfo{ 9932 inputs: []inputInfo{ 9933 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9934 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9935 }, 9936 outputs: []outputInfo{ 9937 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9938 }, 9939 }, 9940 }, 9941 { 9942 name: "MOVWstoreidx", 9943 argLen: 4, 9944 asm: arm.AMOVW, 9945 reg: regInfo{ 9946 inputs: []inputInfo{ 9947 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9948 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9949 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9950 }, 9951 }, 9952 }, 9953 { 9954 name: "MOVWstoreshiftLL", 9955 auxType: auxInt32, 9956 argLen: 4, 9957 asm: arm.AMOVW, 9958 reg: regInfo{ 9959 inputs: []inputInfo{ 9960 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9961 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9962 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9963 }, 9964 }, 9965 }, 9966 { 9967 name: "MOVWstoreshiftRL", 9968 auxType: auxInt32, 9969 argLen: 4, 9970 asm: arm.AMOVW, 9971 reg: regInfo{ 9972 inputs: []inputInfo{ 9973 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9974 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9975 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9976 }, 9977 }, 9978 }, 9979 { 9980 name: "MOVWstoreshiftRA", 9981 auxType: auxInt32, 9982 argLen: 4, 9983 asm: arm.AMOVW, 9984 reg: regInfo{ 9985 inputs: []inputInfo{ 9986 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9987 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9988 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9989 }, 9990 }, 9991 }, 9992 { 9993 name: "MOVBreg", 9994 argLen: 1, 9995 asm: arm.AMOVBS, 9996 reg: regInfo{ 9997 inputs: []inputInfo{ 9998 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9999 }, 10000 outputs: []outputInfo{ 10001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10002 }, 10003 }, 10004 }, 10005 { 10006 name: "MOVBUreg", 10007 argLen: 1, 10008 asm: arm.AMOVBU, 10009 reg: regInfo{ 10010 inputs: []inputInfo{ 10011 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10012 }, 10013 outputs: []outputInfo{ 10014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10015 }, 10016 }, 10017 }, 10018 { 10019 name: "MOVHreg", 10020 argLen: 1, 10021 asm: arm.AMOVHS, 10022 reg: regInfo{ 10023 inputs: []inputInfo{ 10024 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10025 }, 10026 outputs: []outputInfo{ 10027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10028 }, 10029 }, 10030 }, 10031 { 10032 name: "MOVHUreg", 10033 argLen: 1, 10034 asm: arm.AMOVHU, 10035 reg: regInfo{ 10036 inputs: []inputInfo{ 10037 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10038 }, 10039 outputs: []outputInfo{ 10040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10041 }, 10042 }, 10043 }, 10044 { 10045 name: "MOVWreg", 10046 argLen: 1, 10047 asm: arm.AMOVW, 10048 reg: regInfo{ 10049 inputs: []inputInfo{ 10050 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10051 }, 10052 outputs: []outputInfo{ 10053 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10054 }, 10055 }, 10056 }, 10057 { 10058 name: "MOVWnop", 10059 argLen: 1, 10060 resultInArg0: true, 10061 reg: regInfo{ 10062 inputs: []inputInfo{ 10063 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10064 }, 10065 outputs: []outputInfo{ 10066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10067 }, 10068 }, 10069 }, 10070 { 10071 name: "MOVWF", 10072 argLen: 1, 10073 asm: arm.AMOVWF, 10074 reg: regInfo{ 10075 inputs: []inputInfo{ 10076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10077 }, 10078 outputs: []outputInfo{ 10079 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10080 }, 10081 }, 10082 }, 10083 { 10084 name: "MOVWD", 10085 argLen: 1, 10086 asm: arm.AMOVWD, 10087 reg: regInfo{ 10088 inputs: []inputInfo{ 10089 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10090 }, 10091 outputs: []outputInfo{ 10092 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10093 }, 10094 }, 10095 }, 10096 { 10097 name: "MOVWUF", 10098 argLen: 1, 10099 asm: arm.AMOVWF, 10100 reg: regInfo{ 10101 inputs: []inputInfo{ 10102 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10103 }, 10104 outputs: []outputInfo{ 10105 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10106 }, 10107 }, 10108 }, 10109 { 10110 name: "MOVWUD", 10111 argLen: 1, 10112 asm: arm.AMOVWD, 10113 reg: regInfo{ 10114 inputs: []inputInfo{ 10115 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10116 }, 10117 outputs: []outputInfo{ 10118 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10119 }, 10120 }, 10121 }, 10122 { 10123 name: "MOVFW", 10124 argLen: 1, 10125 asm: arm.AMOVFW, 10126 reg: regInfo{ 10127 inputs: []inputInfo{ 10128 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10129 }, 10130 outputs: []outputInfo{ 10131 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10132 }, 10133 }, 10134 }, 10135 { 10136 name: "MOVDW", 10137 argLen: 1, 10138 asm: arm.AMOVDW, 10139 reg: regInfo{ 10140 inputs: []inputInfo{ 10141 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10142 }, 10143 outputs: []outputInfo{ 10144 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10145 }, 10146 }, 10147 }, 10148 { 10149 name: "MOVFWU", 10150 argLen: 1, 10151 asm: arm.AMOVFW, 10152 reg: regInfo{ 10153 inputs: []inputInfo{ 10154 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10155 }, 10156 outputs: []outputInfo{ 10157 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10158 }, 10159 }, 10160 }, 10161 { 10162 name: "MOVDWU", 10163 argLen: 1, 10164 asm: arm.AMOVDW, 10165 reg: regInfo{ 10166 inputs: []inputInfo{ 10167 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10168 }, 10169 outputs: []outputInfo{ 10170 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10171 }, 10172 }, 10173 }, 10174 { 10175 name: "MOVFD", 10176 argLen: 1, 10177 asm: arm.AMOVFD, 10178 reg: regInfo{ 10179 inputs: []inputInfo{ 10180 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10181 }, 10182 outputs: []outputInfo{ 10183 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10184 }, 10185 }, 10186 }, 10187 { 10188 name: "MOVDF", 10189 argLen: 1, 10190 asm: arm.AMOVDF, 10191 reg: regInfo{ 10192 inputs: []inputInfo{ 10193 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10194 }, 10195 outputs: []outputInfo{ 10196 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10197 }, 10198 }, 10199 }, 10200 { 10201 name: "CMOVWHSconst", 10202 auxType: auxInt32, 10203 argLen: 2, 10204 resultInArg0: true, 10205 asm: arm.AMOVW, 10206 reg: regInfo{ 10207 inputs: []inputInfo{ 10208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10209 }, 10210 outputs: []outputInfo{ 10211 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10212 }, 10213 }, 10214 }, 10215 { 10216 name: "CMOVWLSconst", 10217 auxType: auxInt32, 10218 argLen: 2, 10219 resultInArg0: true, 10220 asm: arm.AMOVW, 10221 reg: regInfo{ 10222 inputs: []inputInfo{ 10223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10224 }, 10225 outputs: []outputInfo{ 10226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10227 }, 10228 }, 10229 }, 10230 { 10231 name: "SRAcond", 10232 argLen: 3, 10233 asm: arm.ASRA, 10234 reg: regInfo{ 10235 inputs: []inputInfo{ 10236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10237 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10238 }, 10239 outputs: []outputInfo{ 10240 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10241 }, 10242 }, 10243 }, 10244 { 10245 name: "CALLstatic", 10246 auxType: auxSymOff, 10247 argLen: 1, 10248 clobberFlags: true, 10249 call: true, 10250 reg: regInfo{ 10251 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10252 }, 10253 }, 10254 { 10255 name: "CALLclosure", 10256 auxType: auxInt64, 10257 argLen: 3, 10258 clobberFlags: true, 10259 call: true, 10260 reg: regInfo{ 10261 inputs: []inputInfo{ 10262 {1, 128}, // R7 10263 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10264 }, 10265 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10266 }, 10267 }, 10268 { 10269 name: "CALLdefer", 10270 auxType: auxInt64, 10271 argLen: 1, 10272 clobberFlags: true, 10273 call: true, 10274 reg: regInfo{ 10275 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10276 }, 10277 }, 10278 { 10279 name: "CALLgo", 10280 auxType: auxInt64, 10281 argLen: 1, 10282 clobberFlags: true, 10283 call: true, 10284 reg: regInfo{ 10285 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10286 }, 10287 }, 10288 { 10289 name: "CALLinter", 10290 auxType: auxInt64, 10291 argLen: 2, 10292 clobberFlags: true, 10293 call: true, 10294 reg: regInfo{ 10295 inputs: []inputInfo{ 10296 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10297 }, 10298 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10299 }, 10300 }, 10301 { 10302 name: "LoweredNilCheck", 10303 argLen: 2, 10304 nilCheck: true, 10305 faultOnNilArg0: true, 10306 reg: regInfo{ 10307 inputs: []inputInfo{ 10308 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10309 }, 10310 }, 10311 }, 10312 { 10313 name: "Equal", 10314 argLen: 1, 10315 reg: regInfo{ 10316 outputs: []outputInfo{ 10317 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10318 }, 10319 }, 10320 }, 10321 { 10322 name: "NotEqual", 10323 argLen: 1, 10324 reg: regInfo{ 10325 outputs: []outputInfo{ 10326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10327 }, 10328 }, 10329 }, 10330 { 10331 name: "LessThan", 10332 argLen: 1, 10333 reg: regInfo{ 10334 outputs: []outputInfo{ 10335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10336 }, 10337 }, 10338 }, 10339 { 10340 name: "LessEqual", 10341 argLen: 1, 10342 reg: regInfo{ 10343 outputs: []outputInfo{ 10344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10345 }, 10346 }, 10347 }, 10348 { 10349 name: "GreaterThan", 10350 argLen: 1, 10351 reg: regInfo{ 10352 outputs: []outputInfo{ 10353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10354 }, 10355 }, 10356 }, 10357 { 10358 name: "GreaterEqual", 10359 argLen: 1, 10360 reg: regInfo{ 10361 outputs: []outputInfo{ 10362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10363 }, 10364 }, 10365 }, 10366 { 10367 name: "LessThanU", 10368 argLen: 1, 10369 reg: regInfo{ 10370 outputs: []outputInfo{ 10371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10372 }, 10373 }, 10374 }, 10375 { 10376 name: "LessEqualU", 10377 argLen: 1, 10378 reg: regInfo{ 10379 outputs: []outputInfo{ 10380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10381 }, 10382 }, 10383 }, 10384 { 10385 name: "GreaterThanU", 10386 argLen: 1, 10387 reg: regInfo{ 10388 outputs: []outputInfo{ 10389 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10390 }, 10391 }, 10392 }, 10393 { 10394 name: "GreaterEqualU", 10395 argLen: 1, 10396 reg: regInfo{ 10397 outputs: []outputInfo{ 10398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10399 }, 10400 }, 10401 }, 10402 { 10403 name: "DUFFZERO", 10404 auxType: auxInt64, 10405 argLen: 3, 10406 faultOnNilArg0: true, 10407 reg: regInfo{ 10408 inputs: []inputInfo{ 10409 {0, 2}, // R1 10410 {1, 1}, // R0 10411 }, 10412 clobbers: 16386, // R1 R14 10413 }, 10414 }, 10415 { 10416 name: "DUFFCOPY", 10417 auxType: auxInt64, 10418 argLen: 3, 10419 faultOnNilArg0: true, 10420 faultOnNilArg1: true, 10421 reg: regInfo{ 10422 inputs: []inputInfo{ 10423 {0, 4}, // R2 10424 {1, 2}, // R1 10425 }, 10426 clobbers: 16391, // R0 R1 R2 R14 10427 }, 10428 }, 10429 { 10430 name: "LoweredZero", 10431 auxType: auxInt64, 10432 argLen: 4, 10433 clobberFlags: true, 10434 faultOnNilArg0: true, 10435 reg: regInfo{ 10436 inputs: []inputInfo{ 10437 {0, 2}, // R1 10438 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10439 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10440 }, 10441 clobbers: 2, // R1 10442 }, 10443 }, 10444 { 10445 name: "LoweredMove", 10446 auxType: auxInt64, 10447 argLen: 4, 10448 clobberFlags: true, 10449 faultOnNilArg0: true, 10450 faultOnNilArg1: true, 10451 reg: regInfo{ 10452 inputs: []inputInfo{ 10453 {0, 4}, // R2 10454 {1, 2}, // R1 10455 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10456 }, 10457 clobbers: 6, // R1 R2 10458 }, 10459 }, 10460 { 10461 name: "LoweredGetClosurePtr", 10462 argLen: 0, 10463 reg: regInfo{ 10464 outputs: []outputInfo{ 10465 {0, 128}, // R7 10466 }, 10467 }, 10468 }, 10469 { 10470 name: "MOVWconvert", 10471 argLen: 2, 10472 asm: arm.AMOVW, 10473 reg: regInfo{ 10474 inputs: []inputInfo{ 10475 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10476 }, 10477 outputs: []outputInfo{ 10478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10479 }, 10480 }, 10481 }, 10482 { 10483 name: "FlagEQ", 10484 argLen: 0, 10485 reg: regInfo{}, 10486 }, 10487 { 10488 name: "FlagLT_ULT", 10489 argLen: 0, 10490 reg: regInfo{}, 10491 }, 10492 { 10493 name: "FlagLT_UGT", 10494 argLen: 0, 10495 reg: regInfo{}, 10496 }, 10497 { 10498 name: "FlagGT_UGT", 10499 argLen: 0, 10500 reg: regInfo{}, 10501 }, 10502 { 10503 name: "FlagGT_ULT", 10504 argLen: 0, 10505 reg: regInfo{}, 10506 }, 10507 { 10508 name: "InvertFlags", 10509 argLen: 1, 10510 reg: regInfo{}, 10511 }, 10512 10513 { 10514 name: "ADD", 10515 argLen: 2, 10516 commutative: true, 10517 asm: arm64.AADD, 10518 reg: regInfo{ 10519 inputs: []inputInfo{ 10520 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10521 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10522 }, 10523 outputs: []outputInfo{ 10524 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10525 }, 10526 }, 10527 }, 10528 { 10529 name: "ADDconst", 10530 auxType: auxInt64, 10531 argLen: 1, 10532 asm: arm64.AADD, 10533 reg: regInfo{ 10534 inputs: []inputInfo{ 10535 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10536 }, 10537 outputs: []outputInfo{ 10538 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10539 }, 10540 }, 10541 }, 10542 { 10543 name: "SUB", 10544 argLen: 2, 10545 asm: arm64.ASUB, 10546 reg: regInfo{ 10547 inputs: []inputInfo{ 10548 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10549 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10550 }, 10551 outputs: []outputInfo{ 10552 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10553 }, 10554 }, 10555 }, 10556 { 10557 name: "SUBconst", 10558 auxType: auxInt64, 10559 argLen: 1, 10560 asm: arm64.ASUB, 10561 reg: regInfo{ 10562 inputs: []inputInfo{ 10563 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10564 }, 10565 outputs: []outputInfo{ 10566 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10567 }, 10568 }, 10569 }, 10570 { 10571 name: "MUL", 10572 argLen: 2, 10573 commutative: true, 10574 asm: arm64.AMUL, 10575 reg: regInfo{ 10576 inputs: []inputInfo{ 10577 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10578 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10579 }, 10580 outputs: []outputInfo{ 10581 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10582 }, 10583 }, 10584 }, 10585 { 10586 name: "MULW", 10587 argLen: 2, 10588 commutative: true, 10589 asm: arm64.AMULW, 10590 reg: regInfo{ 10591 inputs: []inputInfo{ 10592 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10593 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10594 }, 10595 outputs: []outputInfo{ 10596 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10597 }, 10598 }, 10599 }, 10600 { 10601 name: "MULH", 10602 argLen: 2, 10603 commutative: true, 10604 asm: arm64.ASMULH, 10605 reg: regInfo{ 10606 inputs: []inputInfo{ 10607 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10608 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10609 }, 10610 outputs: []outputInfo{ 10611 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10612 }, 10613 }, 10614 }, 10615 { 10616 name: "UMULH", 10617 argLen: 2, 10618 commutative: true, 10619 asm: arm64.AUMULH, 10620 reg: regInfo{ 10621 inputs: []inputInfo{ 10622 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10623 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10624 }, 10625 outputs: []outputInfo{ 10626 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10627 }, 10628 }, 10629 }, 10630 { 10631 name: "MULL", 10632 argLen: 2, 10633 commutative: true, 10634 asm: arm64.ASMULL, 10635 reg: regInfo{ 10636 inputs: []inputInfo{ 10637 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10638 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10639 }, 10640 outputs: []outputInfo{ 10641 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10642 }, 10643 }, 10644 }, 10645 { 10646 name: "UMULL", 10647 argLen: 2, 10648 commutative: true, 10649 asm: arm64.AUMULL, 10650 reg: regInfo{ 10651 inputs: []inputInfo{ 10652 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10653 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10654 }, 10655 outputs: []outputInfo{ 10656 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10657 }, 10658 }, 10659 }, 10660 { 10661 name: "DIV", 10662 argLen: 2, 10663 asm: arm64.ASDIV, 10664 reg: regInfo{ 10665 inputs: []inputInfo{ 10666 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10667 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10668 }, 10669 outputs: []outputInfo{ 10670 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10671 }, 10672 }, 10673 }, 10674 { 10675 name: "UDIV", 10676 argLen: 2, 10677 asm: arm64.AUDIV, 10678 reg: regInfo{ 10679 inputs: []inputInfo{ 10680 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10681 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10682 }, 10683 outputs: []outputInfo{ 10684 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10685 }, 10686 }, 10687 }, 10688 { 10689 name: "DIVW", 10690 argLen: 2, 10691 asm: arm64.ASDIVW, 10692 reg: regInfo{ 10693 inputs: []inputInfo{ 10694 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10695 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10696 }, 10697 outputs: []outputInfo{ 10698 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10699 }, 10700 }, 10701 }, 10702 { 10703 name: "UDIVW", 10704 argLen: 2, 10705 asm: arm64.AUDIVW, 10706 reg: regInfo{ 10707 inputs: []inputInfo{ 10708 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10709 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10710 }, 10711 outputs: []outputInfo{ 10712 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10713 }, 10714 }, 10715 }, 10716 { 10717 name: "MOD", 10718 argLen: 2, 10719 asm: arm64.AREM, 10720 reg: regInfo{ 10721 inputs: []inputInfo{ 10722 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10723 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10724 }, 10725 outputs: []outputInfo{ 10726 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10727 }, 10728 }, 10729 }, 10730 { 10731 name: "UMOD", 10732 argLen: 2, 10733 asm: arm64.AUREM, 10734 reg: regInfo{ 10735 inputs: []inputInfo{ 10736 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10737 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10738 }, 10739 outputs: []outputInfo{ 10740 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10741 }, 10742 }, 10743 }, 10744 { 10745 name: "MODW", 10746 argLen: 2, 10747 asm: arm64.AREMW, 10748 reg: regInfo{ 10749 inputs: []inputInfo{ 10750 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10751 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10752 }, 10753 outputs: []outputInfo{ 10754 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10755 }, 10756 }, 10757 }, 10758 { 10759 name: "UMODW", 10760 argLen: 2, 10761 asm: arm64.AUREMW, 10762 reg: regInfo{ 10763 inputs: []inputInfo{ 10764 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10765 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10766 }, 10767 outputs: []outputInfo{ 10768 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10769 }, 10770 }, 10771 }, 10772 { 10773 name: "FADDS", 10774 argLen: 2, 10775 commutative: true, 10776 asm: arm64.AFADDS, 10777 reg: regInfo{ 10778 inputs: []inputInfo{ 10779 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10780 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10781 }, 10782 outputs: []outputInfo{ 10783 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10784 }, 10785 }, 10786 }, 10787 { 10788 name: "FADDD", 10789 argLen: 2, 10790 commutative: true, 10791 asm: arm64.AFADDD, 10792 reg: regInfo{ 10793 inputs: []inputInfo{ 10794 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10795 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10796 }, 10797 outputs: []outputInfo{ 10798 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10799 }, 10800 }, 10801 }, 10802 { 10803 name: "FSUBS", 10804 argLen: 2, 10805 asm: arm64.AFSUBS, 10806 reg: regInfo{ 10807 inputs: []inputInfo{ 10808 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10809 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10810 }, 10811 outputs: []outputInfo{ 10812 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10813 }, 10814 }, 10815 }, 10816 { 10817 name: "FSUBD", 10818 argLen: 2, 10819 asm: arm64.AFSUBD, 10820 reg: regInfo{ 10821 inputs: []inputInfo{ 10822 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10823 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10824 }, 10825 outputs: []outputInfo{ 10826 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10827 }, 10828 }, 10829 }, 10830 { 10831 name: "FMULS", 10832 argLen: 2, 10833 commutative: true, 10834 asm: arm64.AFMULS, 10835 reg: regInfo{ 10836 inputs: []inputInfo{ 10837 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10838 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10839 }, 10840 outputs: []outputInfo{ 10841 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10842 }, 10843 }, 10844 }, 10845 { 10846 name: "FMULD", 10847 argLen: 2, 10848 commutative: true, 10849 asm: arm64.AFMULD, 10850 reg: regInfo{ 10851 inputs: []inputInfo{ 10852 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10853 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10854 }, 10855 outputs: []outputInfo{ 10856 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10857 }, 10858 }, 10859 }, 10860 { 10861 name: "FDIVS", 10862 argLen: 2, 10863 asm: arm64.AFDIVS, 10864 reg: regInfo{ 10865 inputs: []inputInfo{ 10866 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10867 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10868 }, 10869 outputs: []outputInfo{ 10870 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10871 }, 10872 }, 10873 }, 10874 { 10875 name: "FDIVD", 10876 argLen: 2, 10877 asm: arm64.AFDIVD, 10878 reg: regInfo{ 10879 inputs: []inputInfo{ 10880 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10881 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10882 }, 10883 outputs: []outputInfo{ 10884 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10885 }, 10886 }, 10887 }, 10888 { 10889 name: "AND", 10890 argLen: 2, 10891 commutative: true, 10892 asm: arm64.AAND, 10893 reg: regInfo{ 10894 inputs: []inputInfo{ 10895 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10896 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10897 }, 10898 outputs: []outputInfo{ 10899 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10900 }, 10901 }, 10902 }, 10903 { 10904 name: "ANDconst", 10905 auxType: auxInt64, 10906 argLen: 1, 10907 asm: arm64.AAND, 10908 reg: regInfo{ 10909 inputs: []inputInfo{ 10910 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10911 }, 10912 outputs: []outputInfo{ 10913 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10914 }, 10915 }, 10916 }, 10917 { 10918 name: "OR", 10919 argLen: 2, 10920 commutative: true, 10921 asm: arm64.AORR, 10922 reg: regInfo{ 10923 inputs: []inputInfo{ 10924 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10925 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10926 }, 10927 outputs: []outputInfo{ 10928 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10929 }, 10930 }, 10931 }, 10932 { 10933 name: "ORconst", 10934 auxType: auxInt64, 10935 argLen: 1, 10936 asm: arm64.AORR, 10937 reg: regInfo{ 10938 inputs: []inputInfo{ 10939 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10940 }, 10941 outputs: []outputInfo{ 10942 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10943 }, 10944 }, 10945 }, 10946 { 10947 name: "XOR", 10948 argLen: 2, 10949 commutative: true, 10950 asm: arm64.AEOR, 10951 reg: regInfo{ 10952 inputs: []inputInfo{ 10953 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10954 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10955 }, 10956 outputs: []outputInfo{ 10957 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10958 }, 10959 }, 10960 }, 10961 { 10962 name: "XORconst", 10963 auxType: auxInt64, 10964 argLen: 1, 10965 asm: arm64.AEOR, 10966 reg: regInfo{ 10967 inputs: []inputInfo{ 10968 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10969 }, 10970 outputs: []outputInfo{ 10971 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10972 }, 10973 }, 10974 }, 10975 { 10976 name: "BIC", 10977 argLen: 2, 10978 asm: arm64.ABIC, 10979 reg: regInfo{ 10980 inputs: []inputInfo{ 10981 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10982 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10983 }, 10984 outputs: []outputInfo{ 10985 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10986 }, 10987 }, 10988 }, 10989 { 10990 name: "BICconst", 10991 auxType: auxInt64, 10992 argLen: 1, 10993 asm: arm64.ABIC, 10994 reg: regInfo{ 10995 inputs: []inputInfo{ 10996 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10997 }, 10998 outputs: []outputInfo{ 10999 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11000 }, 11001 }, 11002 }, 11003 { 11004 name: "MVN", 11005 argLen: 1, 11006 asm: arm64.AMVN, 11007 reg: regInfo{ 11008 inputs: []inputInfo{ 11009 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11010 }, 11011 outputs: []outputInfo{ 11012 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11013 }, 11014 }, 11015 }, 11016 { 11017 name: "NEG", 11018 argLen: 1, 11019 asm: arm64.ANEG, 11020 reg: regInfo{ 11021 inputs: []inputInfo{ 11022 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11023 }, 11024 outputs: []outputInfo{ 11025 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11026 }, 11027 }, 11028 }, 11029 { 11030 name: "FNEGS", 11031 argLen: 1, 11032 asm: arm64.AFNEGS, 11033 reg: regInfo{ 11034 inputs: []inputInfo{ 11035 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11036 }, 11037 outputs: []outputInfo{ 11038 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11039 }, 11040 }, 11041 }, 11042 { 11043 name: "FNEGD", 11044 argLen: 1, 11045 asm: arm64.AFNEGD, 11046 reg: regInfo{ 11047 inputs: []inputInfo{ 11048 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11049 }, 11050 outputs: []outputInfo{ 11051 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11052 }, 11053 }, 11054 }, 11055 { 11056 name: "FSQRTD", 11057 argLen: 1, 11058 asm: arm64.AFSQRTD, 11059 reg: regInfo{ 11060 inputs: []inputInfo{ 11061 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11062 }, 11063 outputs: []outputInfo{ 11064 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11065 }, 11066 }, 11067 }, 11068 { 11069 name: "REV", 11070 argLen: 1, 11071 asm: arm64.AREV, 11072 reg: regInfo{ 11073 inputs: []inputInfo{ 11074 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11075 }, 11076 outputs: []outputInfo{ 11077 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11078 }, 11079 }, 11080 }, 11081 { 11082 name: "REVW", 11083 argLen: 1, 11084 asm: arm64.AREVW, 11085 reg: regInfo{ 11086 inputs: []inputInfo{ 11087 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11088 }, 11089 outputs: []outputInfo{ 11090 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11091 }, 11092 }, 11093 }, 11094 { 11095 name: "REV16W", 11096 argLen: 1, 11097 asm: arm64.AREV16W, 11098 reg: regInfo{ 11099 inputs: []inputInfo{ 11100 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11101 }, 11102 outputs: []outputInfo{ 11103 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11104 }, 11105 }, 11106 }, 11107 { 11108 name: "RBIT", 11109 argLen: 1, 11110 asm: arm64.ARBIT, 11111 reg: regInfo{ 11112 inputs: []inputInfo{ 11113 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11114 }, 11115 outputs: []outputInfo{ 11116 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11117 }, 11118 }, 11119 }, 11120 { 11121 name: "RBITW", 11122 argLen: 1, 11123 asm: arm64.ARBITW, 11124 reg: regInfo{ 11125 inputs: []inputInfo{ 11126 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11127 }, 11128 outputs: []outputInfo{ 11129 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11130 }, 11131 }, 11132 }, 11133 { 11134 name: "CLZ", 11135 argLen: 1, 11136 asm: arm64.ACLZ, 11137 reg: regInfo{ 11138 inputs: []inputInfo{ 11139 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11140 }, 11141 outputs: []outputInfo{ 11142 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11143 }, 11144 }, 11145 }, 11146 { 11147 name: "CLZW", 11148 argLen: 1, 11149 asm: arm64.ACLZW, 11150 reg: regInfo{ 11151 inputs: []inputInfo{ 11152 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11153 }, 11154 outputs: []outputInfo{ 11155 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11156 }, 11157 }, 11158 }, 11159 { 11160 name: "SLL", 11161 argLen: 2, 11162 asm: arm64.ALSL, 11163 reg: regInfo{ 11164 inputs: []inputInfo{ 11165 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11166 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11167 }, 11168 outputs: []outputInfo{ 11169 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11170 }, 11171 }, 11172 }, 11173 { 11174 name: "SLLconst", 11175 auxType: auxInt64, 11176 argLen: 1, 11177 asm: arm64.ALSL, 11178 reg: regInfo{ 11179 inputs: []inputInfo{ 11180 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11181 }, 11182 outputs: []outputInfo{ 11183 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11184 }, 11185 }, 11186 }, 11187 { 11188 name: "SRL", 11189 argLen: 2, 11190 asm: arm64.ALSR, 11191 reg: regInfo{ 11192 inputs: []inputInfo{ 11193 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11194 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11195 }, 11196 outputs: []outputInfo{ 11197 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11198 }, 11199 }, 11200 }, 11201 { 11202 name: "SRLconst", 11203 auxType: auxInt64, 11204 argLen: 1, 11205 asm: arm64.ALSR, 11206 reg: regInfo{ 11207 inputs: []inputInfo{ 11208 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11209 }, 11210 outputs: []outputInfo{ 11211 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11212 }, 11213 }, 11214 }, 11215 { 11216 name: "SRA", 11217 argLen: 2, 11218 asm: arm64.AASR, 11219 reg: regInfo{ 11220 inputs: []inputInfo{ 11221 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11222 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11223 }, 11224 outputs: []outputInfo{ 11225 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11226 }, 11227 }, 11228 }, 11229 { 11230 name: "SRAconst", 11231 auxType: auxInt64, 11232 argLen: 1, 11233 asm: arm64.AASR, 11234 reg: regInfo{ 11235 inputs: []inputInfo{ 11236 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11237 }, 11238 outputs: []outputInfo{ 11239 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11240 }, 11241 }, 11242 }, 11243 { 11244 name: "RORconst", 11245 auxType: auxInt64, 11246 argLen: 1, 11247 asm: arm64.AROR, 11248 reg: regInfo{ 11249 inputs: []inputInfo{ 11250 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11251 }, 11252 outputs: []outputInfo{ 11253 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11254 }, 11255 }, 11256 }, 11257 { 11258 name: "RORWconst", 11259 auxType: auxInt64, 11260 argLen: 1, 11261 asm: arm64.ARORW, 11262 reg: regInfo{ 11263 inputs: []inputInfo{ 11264 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11265 }, 11266 outputs: []outputInfo{ 11267 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11268 }, 11269 }, 11270 }, 11271 { 11272 name: "CMP", 11273 argLen: 2, 11274 asm: arm64.ACMP, 11275 reg: regInfo{ 11276 inputs: []inputInfo{ 11277 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11278 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11279 }, 11280 }, 11281 }, 11282 { 11283 name: "CMPconst", 11284 auxType: auxInt64, 11285 argLen: 1, 11286 asm: arm64.ACMP, 11287 reg: regInfo{ 11288 inputs: []inputInfo{ 11289 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11290 }, 11291 }, 11292 }, 11293 { 11294 name: "CMPW", 11295 argLen: 2, 11296 asm: arm64.ACMPW, 11297 reg: regInfo{ 11298 inputs: []inputInfo{ 11299 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11300 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11301 }, 11302 }, 11303 }, 11304 { 11305 name: "CMPWconst", 11306 auxType: auxInt32, 11307 argLen: 1, 11308 asm: arm64.ACMPW, 11309 reg: regInfo{ 11310 inputs: []inputInfo{ 11311 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11312 }, 11313 }, 11314 }, 11315 { 11316 name: "CMN", 11317 argLen: 2, 11318 asm: arm64.ACMN, 11319 reg: regInfo{ 11320 inputs: []inputInfo{ 11321 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11322 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11323 }, 11324 }, 11325 }, 11326 { 11327 name: "CMNconst", 11328 auxType: auxInt64, 11329 argLen: 1, 11330 asm: arm64.ACMN, 11331 reg: regInfo{ 11332 inputs: []inputInfo{ 11333 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11334 }, 11335 }, 11336 }, 11337 { 11338 name: "CMNW", 11339 argLen: 2, 11340 asm: arm64.ACMNW, 11341 reg: regInfo{ 11342 inputs: []inputInfo{ 11343 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11344 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11345 }, 11346 }, 11347 }, 11348 { 11349 name: "CMNWconst", 11350 auxType: auxInt32, 11351 argLen: 1, 11352 asm: arm64.ACMNW, 11353 reg: regInfo{ 11354 inputs: []inputInfo{ 11355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11356 }, 11357 }, 11358 }, 11359 { 11360 name: "FCMPS", 11361 argLen: 2, 11362 asm: arm64.AFCMPS, 11363 reg: regInfo{ 11364 inputs: []inputInfo{ 11365 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11366 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11367 }, 11368 }, 11369 }, 11370 { 11371 name: "FCMPD", 11372 argLen: 2, 11373 asm: arm64.AFCMPD, 11374 reg: regInfo{ 11375 inputs: []inputInfo{ 11376 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11377 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11378 }, 11379 }, 11380 }, 11381 { 11382 name: "ADDshiftLL", 11383 auxType: auxInt64, 11384 argLen: 2, 11385 asm: arm64.AADD, 11386 reg: regInfo{ 11387 inputs: []inputInfo{ 11388 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11389 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11390 }, 11391 outputs: []outputInfo{ 11392 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11393 }, 11394 }, 11395 }, 11396 { 11397 name: "ADDshiftRL", 11398 auxType: auxInt64, 11399 argLen: 2, 11400 asm: arm64.AADD, 11401 reg: regInfo{ 11402 inputs: []inputInfo{ 11403 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11404 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11405 }, 11406 outputs: []outputInfo{ 11407 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11408 }, 11409 }, 11410 }, 11411 { 11412 name: "ADDshiftRA", 11413 auxType: auxInt64, 11414 argLen: 2, 11415 asm: arm64.AADD, 11416 reg: regInfo{ 11417 inputs: []inputInfo{ 11418 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11419 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11420 }, 11421 outputs: []outputInfo{ 11422 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11423 }, 11424 }, 11425 }, 11426 { 11427 name: "SUBshiftLL", 11428 auxType: auxInt64, 11429 argLen: 2, 11430 asm: arm64.ASUB, 11431 reg: regInfo{ 11432 inputs: []inputInfo{ 11433 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11434 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11435 }, 11436 outputs: []outputInfo{ 11437 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11438 }, 11439 }, 11440 }, 11441 { 11442 name: "SUBshiftRL", 11443 auxType: auxInt64, 11444 argLen: 2, 11445 asm: arm64.ASUB, 11446 reg: regInfo{ 11447 inputs: []inputInfo{ 11448 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11449 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11450 }, 11451 outputs: []outputInfo{ 11452 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11453 }, 11454 }, 11455 }, 11456 { 11457 name: "SUBshiftRA", 11458 auxType: auxInt64, 11459 argLen: 2, 11460 asm: arm64.ASUB, 11461 reg: regInfo{ 11462 inputs: []inputInfo{ 11463 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11464 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11465 }, 11466 outputs: []outputInfo{ 11467 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11468 }, 11469 }, 11470 }, 11471 { 11472 name: "ANDshiftLL", 11473 auxType: auxInt64, 11474 argLen: 2, 11475 asm: arm64.AAND, 11476 reg: regInfo{ 11477 inputs: []inputInfo{ 11478 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11479 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11480 }, 11481 outputs: []outputInfo{ 11482 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11483 }, 11484 }, 11485 }, 11486 { 11487 name: "ANDshiftRL", 11488 auxType: auxInt64, 11489 argLen: 2, 11490 asm: arm64.AAND, 11491 reg: regInfo{ 11492 inputs: []inputInfo{ 11493 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11494 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11495 }, 11496 outputs: []outputInfo{ 11497 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11498 }, 11499 }, 11500 }, 11501 { 11502 name: "ANDshiftRA", 11503 auxType: auxInt64, 11504 argLen: 2, 11505 asm: arm64.AAND, 11506 reg: regInfo{ 11507 inputs: []inputInfo{ 11508 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11509 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11510 }, 11511 outputs: []outputInfo{ 11512 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11513 }, 11514 }, 11515 }, 11516 { 11517 name: "ORshiftLL", 11518 auxType: auxInt64, 11519 argLen: 2, 11520 asm: arm64.AORR, 11521 reg: regInfo{ 11522 inputs: []inputInfo{ 11523 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11524 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11525 }, 11526 outputs: []outputInfo{ 11527 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11528 }, 11529 }, 11530 }, 11531 { 11532 name: "ORshiftRL", 11533 auxType: auxInt64, 11534 argLen: 2, 11535 asm: arm64.AORR, 11536 reg: regInfo{ 11537 inputs: []inputInfo{ 11538 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11539 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11540 }, 11541 outputs: []outputInfo{ 11542 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11543 }, 11544 }, 11545 }, 11546 { 11547 name: "ORshiftRA", 11548 auxType: auxInt64, 11549 argLen: 2, 11550 asm: arm64.AORR, 11551 reg: regInfo{ 11552 inputs: []inputInfo{ 11553 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11554 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11555 }, 11556 outputs: []outputInfo{ 11557 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11558 }, 11559 }, 11560 }, 11561 { 11562 name: "XORshiftLL", 11563 auxType: auxInt64, 11564 argLen: 2, 11565 asm: arm64.AEOR, 11566 reg: regInfo{ 11567 inputs: []inputInfo{ 11568 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11569 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11570 }, 11571 outputs: []outputInfo{ 11572 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11573 }, 11574 }, 11575 }, 11576 { 11577 name: "XORshiftRL", 11578 auxType: auxInt64, 11579 argLen: 2, 11580 asm: arm64.AEOR, 11581 reg: regInfo{ 11582 inputs: []inputInfo{ 11583 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11584 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11585 }, 11586 outputs: []outputInfo{ 11587 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11588 }, 11589 }, 11590 }, 11591 { 11592 name: "XORshiftRA", 11593 auxType: auxInt64, 11594 argLen: 2, 11595 asm: arm64.AEOR, 11596 reg: regInfo{ 11597 inputs: []inputInfo{ 11598 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11599 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11600 }, 11601 outputs: []outputInfo{ 11602 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11603 }, 11604 }, 11605 }, 11606 { 11607 name: "BICshiftLL", 11608 auxType: auxInt64, 11609 argLen: 2, 11610 asm: arm64.ABIC, 11611 reg: regInfo{ 11612 inputs: []inputInfo{ 11613 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11614 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11615 }, 11616 outputs: []outputInfo{ 11617 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11618 }, 11619 }, 11620 }, 11621 { 11622 name: "BICshiftRL", 11623 auxType: auxInt64, 11624 argLen: 2, 11625 asm: arm64.ABIC, 11626 reg: regInfo{ 11627 inputs: []inputInfo{ 11628 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11629 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11630 }, 11631 outputs: []outputInfo{ 11632 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11633 }, 11634 }, 11635 }, 11636 { 11637 name: "BICshiftRA", 11638 auxType: auxInt64, 11639 argLen: 2, 11640 asm: arm64.ABIC, 11641 reg: regInfo{ 11642 inputs: []inputInfo{ 11643 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11644 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11645 }, 11646 outputs: []outputInfo{ 11647 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11648 }, 11649 }, 11650 }, 11651 { 11652 name: "CMPshiftLL", 11653 auxType: auxInt64, 11654 argLen: 2, 11655 asm: arm64.ACMP, 11656 reg: regInfo{ 11657 inputs: []inputInfo{ 11658 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11659 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11660 }, 11661 }, 11662 }, 11663 { 11664 name: "CMPshiftRL", 11665 auxType: auxInt64, 11666 argLen: 2, 11667 asm: arm64.ACMP, 11668 reg: regInfo{ 11669 inputs: []inputInfo{ 11670 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11671 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11672 }, 11673 }, 11674 }, 11675 { 11676 name: "CMPshiftRA", 11677 auxType: auxInt64, 11678 argLen: 2, 11679 asm: arm64.ACMP, 11680 reg: regInfo{ 11681 inputs: []inputInfo{ 11682 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11683 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11684 }, 11685 }, 11686 }, 11687 { 11688 name: "MOVDconst", 11689 auxType: auxInt64, 11690 argLen: 0, 11691 rematerializeable: true, 11692 asm: arm64.AMOVD, 11693 reg: regInfo{ 11694 outputs: []outputInfo{ 11695 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11696 }, 11697 }, 11698 }, 11699 { 11700 name: "FMOVSconst", 11701 auxType: auxFloat64, 11702 argLen: 0, 11703 rematerializeable: true, 11704 asm: arm64.AFMOVS, 11705 reg: regInfo{ 11706 outputs: []outputInfo{ 11707 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11708 }, 11709 }, 11710 }, 11711 { 11712 name: "FMOVDconst", 11713 auxType: auxFloat64, 11714 argLen: 0, 11715 rematerializeable: true, 11716 asm: arm64.AFMOVD, 11717 reg: regInfo{ 11718 outputs: []outputInfo{ 11719 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11720 }, 11721 }, 11722 }, 11723 { 11724 name: "MOVDaddr", 11725 auxType: auxSymOff, 11726 argLen: 1, 11727 rematerializeable: true, 11728 asm: arm64.AMOVD, 11729 reg: regInfo{ 11730 inputs: []inputInfo{ 11731 {0, 9223372037928517632}, // SP SB 11732 }, 11733 outputs: []outputInfo{ 11734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11735 }, 11736 }, 11737 }, 11738 { 11739 name: "MOVBload", 11740 auxType: auxSymOff, 11741 argLen: 2, 11742 faultOnNilArg0: true, 11743 asm: arm64.AMOVB, 11744 reg: regInfo{ 11745 inputs: []inputInfo{ 11746 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11747 }, 11748 outputs: []outputInfo{ 11749 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11750 }, 11751 }, 11752 }, 11753 { 11754 name: "MOVBUload", 11755 auxType: auxSymOff, 11756 argLen: 2, 11757 faultOnNilArg0: true, 11758 asm: arm64.AMOVBU, 11759 reg: regInfo{ 11760 inputs: []inputInfo{ 11761 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11762 }, 11763 outputs: []outputInfo{ 11764 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11765 }, 11766 }, 11767 }, 11768 { 11769 name: "MOVHload", 11770 auxType: auxSymOff, 11771 argLen: 2, 11772 faultOnNilArg0: true, 11773 asm: arm64.AMOVH, 11774 reg: regInfo{ 11775 inputs: []inputInfo{ 11776 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11777 }, 11778 outputs: []outputInfo{ 11779 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11780 }, 11781 }, 11782 }, 11783 { 11784 name: "MOVHUload", 11785 auxType: auxSymOff, 11786 argLen: 2, 11787 faultOnNilArg0: true, 11788 asm: arm64.AMOVHU, 11789 reg: regInfo{ 11790 inputs: []inputInfo{ 11791 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11792 }, 11793 outputs: []outputInfo{ 11794 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11795 }, 11796 }, 11797 }, 11798 { 11799 name: "MOVWload", 11800 auxType: auxSymOff, 11801 argLen: 2, 11802 faultOnNilArg0: true, 11803 asm: arm64.AMOVW, 11804 reg: regInfo{ 11805 inputs: []inputInfo{ 11806 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11807 }, 11808 outputs: []outputInfo{ 11809 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11810 }, 11811 }, 11812 }, 11813 { 11814 name: "MOVWUload", 11815 auxType: auxSymOff, 11816 argLen: 2, 11817 faultOnNilArg0: true, 11818 asm: arm64.AMOVWU, 11819 reg: regInfo{ 11820 inputs: []inputInfo{ 11821 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11822 }, 11823 outputs: []outputInfo{ 11824 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11825 }, 11826 }, 11827 }, 11828 { 11829 name: "MOVDload", 11830 auxType: auxSymOff, 11831 argLen: 2, 11832 faultOnNilArg0: true, 11833 asm: arm64.AMOVD, 11834 reg: regInfo{ 11835 inputs: []inputInfo{ 11836 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11837 }, 11838 outputs: []outputInfo{ 11839 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11840 }, 11841 }, 11842 }, 11843 { 11844 name: "FMOVSload", 11845 auxType: auxSymOff, 11846 argLen: 2, 11847 faultOnNilArg0: true, 11848 asm: arm64.AFMOVS, 11849 reg: regInfo{ 11850 inputs: []inputInfo{ 11851 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11852 }, 11853 outputs: []outputInfo{ 11854 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11855 }, 11856 }, 11857 }, 11858 { 11859 name: "FMOVDload", 11860 auxType: auxSymOff, 11861 argLen: 2, 11862 faultOnNilArg0: true, 11863 asm: arm64.AFMOVD, 11864 reg: regInfo{ 11865 inputs: []inputInfo{ 11866 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11867 }, 11868 outputs: []outputInfo{ 11869 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11870 }, 11871 }, 11872 }, 11873 { 11874 name: "MOVBstore", 11875 auxType: auxSymOff, 11876 argLen: 3, 11877 faultOnNilArg0: true, 11878 asm: arm64.AMOVB, 11879 reg: regInfo{ 11880 inputs: []inputInfo{ 11881 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11882 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11883 }, 11884 }, 11885 }, 11886 { 11887 name: "MOVHstore", 11888 auxType: auxSymOff, 11889 argLen: 3, 11890 faultOnNilArg0: true, 11891 asm: arm64.AMOVH, 11892 reg: regInfo{ 11893 inputs: []inputInfo{ 11894 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11895 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11896 }, 11897 }, 11898 }, 11899 { 11900 name: "MOVWstore", 11901 auxType: auxSymOff, 11902 argLen: 3, 11903 faultOnNilArg0: true, 11904 asm: arm64.AMOVW, 11905 reg: regInfo{ 11906 inputs: []inputInfo{ 11907 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11908 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11909 }, 11910 }, 11911 }, 11912 { 11913 name: "MOVDstore", 11914 auxType: auxSymOff, 11915 argLen: 3, 11916 faultOnNilArg0: true, 11917 asm: arm64.AMOVD, 11918 reg: regInfo{ 11919 inputs: []inputInfo{ 11920 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11921 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11922 }, 11923 }, 11924 }, 11925 { 11926 name: "FMOVSstore", 11927 auxType: auxSymOff, 11928 argLen: 3, 11929 faultOnNilArg0: true, 11930 asm: arm64.AFMOVS, 11931 reg: regInfo{ 11932 inputs: []inputInfo{ 11933 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11934 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11935 }, 11936 }, 11937 }, 11938 { 11939 name: "FMOVDstore", 11940 auxType: auxSymOff, 11941 argLen: 3, 11942 faultOnNilArg0: true, 11943 asm: arm64.AFMOVD, 11944 reg: regInfo{ 11945 inputs: []inputInfo{ 11946 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11947 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11948 }, 11949 }, 11950 }, 11951 { 11952 name: "MOVBstorezero", 11953 auxType: auxSymOff, 11954 argLen: 2, 11955 faultOnNilArg0: true, 11956 asm: arm64.AMOVB, 11957 reg: regInfo{ 11958 inputs: []inputInfo{ 11959 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11960 }, 11961 }, 11962 }, 11963 { 11964 name: "MOVHstorezero", 11965 auxType: auxSymOff, 11966 argLen: 2, 11967 faultOnNilArg0: true, 11968 asm: arm64.AMOVH, 11969 reg: regInfo{ 11970 inputs: []inputInfo{ 11971 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11972 }, 11973 }, 11974 }, 11975 { 11976 name: "MOVWstorezero", 11977 auxType: auxSymOff, 11978 argLen: 2, 11979 faultOnNilArg0: true, 11980 asm: arm64.AMOVW, 11981 reg: regInfo{ 11982 inputs: []inputInfo{ 11983 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11984 }, 11985 }, 11986 }, 11987 { 11988 name: "MOVDstorezero", 11989 auxType: auxSymOff, 11990 argLen: 2, 11991 faultOnNilArg0: true, 11992 asm: arm64.AMOVD, 11993 reg: regInfo{ 11994 inputs: []inputInfo{ 11995 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11996 }, 11997 }, 11998 }, 11999 { 12000 name: "MOVBreg", 12001 argLen: 1, 12002 asm: arm64.AMOVB, 12003 reg: regInfo{ 12004 inputs: []inputInfo{ 12005 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12006 }, 12007 outputs: []outputInfo{ 12008 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12009 }, 12010 }, 12011 }, 12012 { 12013 name: "MOVBUreg", 12014 argLen: 1, 12015 asm: arm64.AMOVBU, 12016 reg: regInfo{ 12017 inputs: []inputInfo{ 12018 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12019 }, 12020 outputs: []outputInfo{ 12021 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12022 }, 12023 }, 12024 }, 12025 { 12026 name: "MOVHreg", 12027 argLen: 1, 12028 asm: arm64.AMOVH, 12029 reg: regInfo{ 12030 inputs: []inputInfo{ 12031 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12032 }, 12033 outputs: []outputInfo{ 12034 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12035 }, 12036 }, 12037 }, 12038 { 12039 name: "MOVHUreg", 12040 argLen: 1, 12041 asm: arm64.AMOVHU, 12042 reg: regInfo{ 12043 inputs: []inputInfo{ 12044 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12045 }, 12046 outputs: []outputInfo{ 12047 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12048 }, 12049 }, 12050 }, 12051 { 12052 name: "MOVWreg", 12053 argLen: 1, 12054 asm: arm64.AMOVW, 12055 reg: regInfo{ 12056 inputs: []inputInfo{ 12057 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12058 }, 12059 outputs: []outputInfo{ 12060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12061 }, 12062 }, 12063 }, 12064 { 12065 name: "MOVWUreg", 12066 argLen: 1, 12067 asm: arm64.AMOVWU, 12068 reg: regInfo{ 12069 inputs: []inputInfo{ 12070 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12071 }, 12072 outputs: []outputInfo{ 12073 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12074 }, 12075 }, 12076 }, 12077 { 12078 name: "MOVDreg", 12079 argLen: 1, 12080 asm: arm64.AMOVD, 12081 reg: regInfo{ 12082 inputs: []inputInfo{ 12083 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12084 }, 12085 outputs: []outputInfo{ 12086 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12087 }, 12088 }, 12089 }, 12090 { 12091 name: "MOVDnop", 12092 argLen: 1, 12093 resultInArg0: true, 12094 reg: regInfo{ 12095 inputs: []inputInfo{ 12096 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12097 }, 12098 outputs: []outputInfo{ 12099 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12100 }, 12101 }, 12102 }, 12103 { 12104 name: "SCVTFWS", 12105 argLen: 1, 12106 asm: arm64.ASCVTFWS, 12107 reg: regInfo{ 12108 inputs: []inputInfo{ 12109 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12110 }, 12111 outputs: []outputInfo{ 12112 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12113 }, 12114 }, 12115 }, 12116 { 12117 name: "SCVTFWD", 12118 argLen: 1, 12119 asm: arm64.ASCVTFWD, 12120 reg: regInfo{ 12121 inputs: []inputInfo{ 12122 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12123 }, 12124 outputs: []outputInfo{ 12125 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12126 }, 12127 }, 12128 }, 12129 { 12130 name: "UCVTFWS", 12131 argLen: 1, 12132 asm: arm64.AUCVTFWS, 12133 reg: regInfo{ 12134 inputs: []inputInfo{ 12135 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12136 }, 12137 outputs: []outputInfo{ 12138 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12139 }, 12140 }, 12141 }, 12142 { 12143 name: "UCVTFWD", 12144 argLen: 1, 12145 asm: arm64.AUCVTFWD, 12146 reg: regInfo{ 12147 inputs: []inputInfo{ 12148 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12149 }, 12150 outputs: []outputInfo{ 12151 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12152 }, 12153 }, 12154 }, 12155 { 12156 name: "SCVTFS", 12157 argLen: 1, 12158 asm: arm64.ASCVTFS, 12159 reg: regInfo{ 12160 inputs: []inputInfo{ 12161 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12162 }, 12163 outputs: []outputInfo{ 12164 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12165 }, 12166 }, 12167 }, 12168 { 12169 name: "SCVTFD", 12170 argLen: 1, 12171 asm: arm64.ASCVTFD, 12172 reg: regInfo{ 12173 inputs: []inputInfo{ 12174 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12175 }, 12176 outputs: []outputInfo{ 12177 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12178 }, 12179 }, 12180 }, 12181 { 12182 name: "UCVTFS", 12183 argLen: 1, 12184 asm: arm64.AUCVTFS, 12185 reg: regInfo{ 12186 inputs: []inputInfo{ 12187 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12188 }, 12189 outputs: []outputInfo{ 12190 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12191 }, 12192 }, 12193 }, 12194 { 12195 name: "UCVTFD", 12196 argLen: 1, 12197 asm: arm64.AUCVTFD, 12198 reg: regInfo{ 12199 inputs: []inputInfo{ 12200 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12201 }, 12202 outputs: []outputInfo{ 12203 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12204 }, 12205 }, 12206 }, 12207 { 12208 name: "FCVTZSSW", 12209 argLen: 1, 12210 asm: arm64.AFCVTZSSW, 12211 reg: regInfo{ 12212 inputs: []inputInfo{ 12213 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12214 }, 12215 outputs: []outputInfo{ 12216 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12217 }, 12218 }, 12219 }, 12220 { 12221 name: "FCVTZSDW", 12222 argLen: 1, 12223 asm: arm64.AFCVTZSDW, 12224 reg: regInfo{ 12225 inputs: []inputInfo{ 12226 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12227 }, 12228 outputs: []outputInfo{ 12229 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12230 }, 12231 }, 12232 }, 12233 { 12234 name: "FCVTZUSW", 12235 argLen: 1, 12236 asm: arm64.AFCVTZUSW, 12237 reg: regInfo{ 12238 inputs: []inputInfo{ 12239 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12240 }, 12241 outputs: []outputInfo{ 12242 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12243 }, 12244 }, 12245 }, 12246 { 12247 name: "FCVTZUDW", 12248 argLen: 1, 12249 asm: arm64.AFCVTZUDW, 12250 reg: regInfo{ 12251 inputs: []inputInfo{ 12252 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12253 }, 12254 outputs: []outputInfo{ 12255 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12256 }, 12257 }, 12258 }, 12259 { 12260 name: "FCVTZSS", 12261 argLen: 1, 12262 asm: arm64.AFCVTZSS, 12263 reg: regInfo{ 12264 inputs: []inputInfo{ 12265 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12266 }, 12267 outputs: []outputInfo{ 12268 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12269 }, 12270 }, 12271 }, 12272 { 12273 name: "FCVTZSD", 12274 argLen: 1, 12275 asm: arm64.AFCVTZSD, 12276 reg: regInfo{ 12277 inputs: []inputInfo{ 12278 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12279 }, 12280 outputs: []outputInfo{ 12281 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12282 }, 12283 }, 12284 }, 12285 { 12286 name: "FCVTZUS", 12287 argLen: 1, 12288 asm: arm64.AFCVTZUS, 12289 reg: regInfo{ 12290 inputs: []inputInfo{ 12291 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12292 }, 12293 outputs: []outputInfo{ 12294 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12295 }, 12296 }, 12297 }, 12298 { 12299 name: "FCVTZUD", 12300 argLen: 1, 12301 asm: arm64.AFCVTZUD, 12302 reg: regInfo{ 12303 inputs: []inputInfo{ 12304 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12305 }, 12306 outputs: []outputInfo{ 12307 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12308 }, 12309 }, 12310 }, 12311 { 12312 name: "FCVTSD", 12313 argLen: 1, 12314 asm: arm64.AFCVTSD, 12315 reg: regInfo{ 12316 inputs: []inputInfo{ 12317 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12318 }, 12319 outputs: []outputInfo{ 12320 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12321 }, 12322 }, 12323 }, 12324 { 12325 name: "FCVTDS", 12326 argLen: 1, 12327 asm: arm64.AFCVTDS, 12328 reg: regInfo{ 12329 inputs: []inputInfo{ 12330 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12331 }, 12332 outputs: []outputInfo{ 12333 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12334 }, 12335 }, 12336 }, 12337 { 12338 name: "CSELULT", 12339 argLen: 3, 12340 asm: arm64.ACSEL, 12341 reg: regInfo{ 12342 inputs: []inputInfo{ 12343 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12344 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12345 }, 12346 outputs: []outputInfo{ 12347 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12348 }, 12349 }, 12350 }, 12351 { 12352 name: "CSELULT0", 12353 argLen: 2, 12354 asm: arm64.ACSEL, 12355 reg: regInfo{ 12356 inputs: []inputInfo{ 12357 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12358 }, 12359 outputs: []outputInfo{ 12360 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12361 }, 12362 }, 12363 }, 12364 { 12365 name: "CALLstatic", 12366 auxType: auxSymOff, 12367 argLen: 1, 12368 clobberFlags: true, 12369 call: true, 12370 reg: regInfo{ 12371 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12372 }, 12373 }, 12374 { 12375 name: "CALLclosure", 12376 auxType: auxInt64, 12377 argLen: 3, 12378 clobberFlags: true, 12379 call: true, 12380 reg: regInfo{ 12381 inputs: []inputInfo{ 12382 {1, 67108864}, // R26 12383 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12384 }, 12385 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12386 }, 12387 }, 12388 { 12389 name: "CALLdefer", 12390 auxType: auxInt64, 12391 argLen: 1, 12392 clobberFlags: true, 12393 call: true, 12394 reg: regInfo{ 12395 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12396 }, 12397 }, 12398 { 12399 name: "CALLgo", 12400 auxType: auxInt64, 12401 argLen: 1, 12402 clobberFlags: true, 12403 call: true, 12404 reg: regInfo{ 12405 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12406 }, 12407 }, 12408 { 12409 name: "CALLinter", 12410 auxType: auxInt64, 12411 argLen: 2, 12412 clobberFlags: true, 12413 call: true, 12414 reg: regInfo{ 12415 inputs: []inputInfo{ 12416 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12417 }, 12418 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12419 }, 12420 }, 12421 { 12422 name: "LoweredNilCheck", 12423 argLen: 2, 12424 nilCheck: true, 12425 faultOnNilArg0: true, 12426 reg: regInfo{ 12427 inputs: []inputInfo{ 12428 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12429 }, 12430 }, 12431 }, 12432 { 12433 name: "Equal", 12434 argLen: 1, 12435 reg: regInfo{ 12436 outputs: []outputInfo{ 12437 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12438 }, 12439 }, 12440 }, 12441 { 12442 name: "NotEqual", 12443 argLen: 1, 12444 reg: regInfo{ 12445 outputs: []outputInfo{ 12446 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12447 }, 12448 }, 12449 }, 12450 { 12451 name: "LessThan", 12452 argLen: 1, 12453 reg: regInfo{ 12454 outputs: []outputInfo{ 12455 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12456 }, 12457 }, 12458 }, 12459 { 12460 name: "LessEqual", 12461 argLen: 1, 12462 reg: regInfo{ 12463 outputs: []outputInfo{ 12464 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12465 }, 12466 }, 12467 }, 12468 { 12469 name: "GreaterThan", 12470 argLen: 1, 12471 reg: regInfo{ 12472 outputs: []outputInfo{ 12473 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12474 }, 12475 }, 12476 }, 12477 { 12478 name: "GreaterEqual", 12479 argLen: 1, 12480 reg: regInfo{ 12481 outputs: []outputInfo{ 12482 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12483 }, 12484 }, 12485 }, 12486 { 12487 name: "LessThanU", 12488 argLen: 1, 12489 reg: regInfo{ 12490 outputs: []outputInfo{ 12491 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12492 }, 12493 }, 12494 }, 12495 { 12496 name: "LessEqualU", 12497 argLen: 1, 12498 reg: regInfo{ 12499 outputs: []outputInfo{ 12500 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12501 }, 12502 }, 12503 }, 12504 { 12505 name: "GreaterThanU", 12506 argLen: 1, 12507 reg: regInfo{ 12508 outputs: []outputInfo{ 12509 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12510 }, 12511 }, 12512 }, 12513 { 12514 name: "GreaterEqualU", 12515 argLen: 1, 12516 reg: regInfo{ 12517 outputs: []outputInfo{ 12518 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12519 }, 12520 }, 12521 }, 12522 { 12523 name: "DUFFZERO", 12524 auxType: auxInt64, 12525 argLen: 2, 12526 faultOnNilArg0: true, 12527 reg: regInfo{ 12528 inputs: []inputInfo{ 12529 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12530 }, 12531 clobbers: 536936448, // R16 R30 12532 }, 12533 }, 12534 { 12535 name: "LoweredZero", 12536 argLen: 3, 12537 clobberFlags: true, 12538 faultOnNilArg0: true, 12539 reg: regInfo{ 12540 inputs: []inputInfo{ 12541 {0, 65536}, // R16 12542 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12543 }, 12544 clobbers: 65536, // R16 12545 }, 12546 }, 12547 { 12548 name: "DUFFCOPY", 12549 auxType: auxInt64, 12550 argLen: 3, 12551 faultOnNilArg0: true, 12552 faultOnNilArg1: true, 12553 reg: regInfo{ 12554 inputs: []inputInfo{ 12555 {0, 131072}, // R17 12556 {1, 65536}, // R16 12557 }, 12558 clobbers: 537067520, // R16 R17 R30 12559 }, 12560 }, 12561 { 12562 name: "LoweredMove", 12563 argLen: 4, 12564 clobberFlags: true, 12565 faultOnNilArg0: true, 12566 faultOnNilArg1: true, 12567 reg: regInfo{ 12568 inputs: []inputInfo{ 12569 {0, 131072}, // R17 12570 {1, 65536}, // R16 12571 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12572 }, 12573 clobbers: 196608, // R16 R17 12574 }, 12575 }, 12576 { 12577 name: "LoweredGetClosurePtr", 12578 argLen: 0, 12579 reg: regInfo{ 12580 outputs: []outputInfo{ 12581 {0, 67108864}, // R26 12582 }, 12583 }, 12584 }, 12585 { 12586 name: "MOVDconvert", 12587 argLen: 2, 12588 asm: arm64.AMOVD, 12589 reg: regInfo{ 12590 inputs: []inputInfo{ 12591 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12592 }, 12593 outputs: []outputInfo{ 12594 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12595 }, 12596 }, 12597 }, 12598 { 12599 name: "FlagEQ", 12600 argLen: 0, 12601 reg: regInfo{}, 12602 }, 12603 { 12604 name: "FlagLT_ULT", 12605 argLen: 0, 12606 reg: regInfo{}, 12607 }, 12608 { 12609 name: "FlagLT_UGT", 12610 argLen: 0, 12611 reg: regInfo{}, 12612 }, 12613 { 12614 name: "FlagGT_UGT", 12615 argLen: 0, 12616 reg: regInfo{}, 12617 }, 12618 { 12619 name: "FlagGT_ULT", 12620 argLen: 0, 12621 reg: regInfo{}, 12622 }, 12623 { 12624 name: "InvertFlags", 12625 argLen: 1, 12626 reg: regInfo{}, 12627 }, 12628 { 12629 name: "LDAR", 12630 argLen: 2, 12631 faultOnNilArg0: true, 12632 asm: arm64.ALDAR, 12633 reg: regInfo{ 12634 inputs: []inputInfo{ 12635 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12636 }, 12637 outputs: []outputInfo{ 12638 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12639 }, 12640 }, 12641 }, 12642 { 12643 name: "LDARW", 12644 argLen: 2, 12645 faultOnNilArg0: true, 12646 asm: arm64.ALDARW, 12647 reg: regInfo{ 12648 inputs: []inputInfo{ 12649 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12650 }, 12651 outputs: []outputInfo{ 12652 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12653 }, 12654 }, 12655 }, 12656 { 12657 name: "STLR", 12658 argLen: 3, 12659 faultOnNilArg0: true, 12660 asm: arm64.ASTLR, 12661 reg: regInfo{ 12662 inputs: []inputInfo{ 12663 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12664 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12665 }, 12666 }, 12667 }, 12668 { 12669 name: "STLRW", 12670 argLen: 3, 12671 faultOnNilArg0: true, 12672 asm: arm64.ASTLRW, 12673 reg: regInfo{ 12674 inputs: []inputInfo{ 12675 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12676 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12677 }, 12678 }, 12679 }, 12680 { 12681 name: "LoweredAtomicExchange64", 12682 argLen: 3, 12683 resultNotInArgs: true, 12684 faultOnNilArg0: true, 12685 reg: regInfo{ 12686 inputs: []inputInfo{ 12687 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12688 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12689 }, 12690 outputs: []outputInfo{ 12691 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12692 }, 12693 }, 12694 }, 12695 { 12696 name: "LoweredAtomicExchange32", 12697 argLen: 3, 12698 resultNotInArgs: true, 12699 faultOnNilArg0: true, 12700 reg: regInfo{ 12701 inputs: []inputInfo{ 12702 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12703 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12704 }, 12705 outputs: []outputInfo{ 12706 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12707 }, 12708 }, 12709 }, 12710 { 12711 name: "LoweredAtomicAdd64", 12712 argLen: 3, 12713 resultNotInArgs: true, 12714 faultOnNilArg0: true, 12715 reg: regInfo{ 12716 inputs: []inputInfo{ 12717 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12718 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12719 }, 12720 outputs: []outputInfo{ 12721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12722 }, 12723 }, 12724 }, 12725 { 12726 name: "LoweredAtomicAdd32", 12727 argLen: 3, 12728 resultNotInArgs: true, 12729 faultOnNilArg0: true, 12730 reg: regInfo{ 12731 inputs: []inputInfo{ 12732 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12733 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12734 }, 12735 outputs: []outputInfo{ 12736 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12737 }, 12738 }, 12739 }, 12740 { 12741 name: "LoweredAtomicCas64", 12742 argLen: 4, 12743 resultNotInArgs: true, 12744 clobberFlags: true, 12745 faultOnNilArg0: true, 12746 reg: regInfo{ 12747 inputs: []inputInfo{ 12748 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12749 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12750 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12751 }, 12752 outputs: []outputInfo{ 12753 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12754 }, 12755 }, 12756 }, 12757 { 12758 name: "LoweredAtomicCas32", 12759 argLen: 4, 12760 resultNotInArgs: true, 12761 clobberFlags: true, 12762 faultOnNilArg0: true, 12763 reg: regInfo{ 12764 inputs: []inputInfo{ 12765 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12766 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12767 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12768 }, 12769 outputs: []outputInfo{ 12770 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12771 }, 12772 }, 12773 }, 12774 { 12775 name: "LoweredAtomicAnd8", 12776 argLen: 3, 12777 faultOnNilArg0: true, 12778 asm: arm64.AAND, 12779 reg: regInfo{ 12780 inputs: []inputInfo{ 12781 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12782 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12783 }, 12784 }, 12785 }, 12786 { 12787 name: "LoweredAtomicOr8", 12788 argLen: 3, 12789 faultOnNilArg0: true, 12790 asm: arm64.AORR, 12791 reg: regInfo{ 12792 inputs: []inputInfo{ 12793 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12794 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12795 }, 12796 }, 12797 }, 12798 12799 { 12800 name: "ADD", 12801 argLen: 2, 12802 commutative: true, 12803 asm: mips.AADDU, 12804 reg: regInfo{ 12805 inputs: []inputInfo{ 12806 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12807 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12808 }, 12809 outputs: []outputInfo{ 12810 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12811 }, 12812 }, 12813 }, 12814 { 12815 name: "ADDconst", 12816 auxType: auxInt32, 12817 argLen: 1, 12818 asm: mips.AADDU, 12819 reg: regInfo{ 12820 inputs: []inputInfo{ 12821 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 12822 }, 12823 outputs: []outputInfo{ 12824 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12825 }, 12826 }, 12827 }, 12828 { 12829 name: "SUB", 12830 argLen: 2, 12831 asm: mips.ASUBU, 12832 reg: regInfo{ 12833 inputs: []inputInfo{ 12834 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12835 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12836 }, 12837 outputs: []outputInfo{ 12838 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12839 }, 12840 }, 12841 }, 12842 { 12843 name: "SUBconst", 12844 auxType: auxInt32, 12845 argLen: 1, 12846 asm: mips.ASUBU, 12847 reg: regInfo{ 12848 inputs: []inputInfo{ 12849 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12850 }, 12851 outputs: []outputInfo{ 12852 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12853 }, 12854 }, 12855 }, 12856 { 12857 name: "MUL", 12858 argLen: 2, 12859 commutative: true, 12860 asm: mips.AMUL, 12861 reg: regInfo{ 12862 inputs: []inputInfo{ 12863 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12864 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12865 }, 12866 clobbers: 105553116266496, // HI LO 12867 outputs: []outputInfo{ 12868 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12869 }, 12870 }, 12871 }, 12872 { 12873 name: "MULT", 12874 argLen: 2, 12875 commutative: true, 12876 asm: mips.AMUL, 12877 reg: regInfo{ 12878 inputs: []inputInfo{ 12879 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12880 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12881 }, 12882 outputs: []outputInfo{ 12883 {0, 35184372088832}, // HI 12884 {1, 70368744177664}, // LO 12885 }, 12886 }, 12887 }, 12888 { 12889 name: "MULTU", 12890 argLen: 2, 12891 commutative: true, 12892 asm: mips.AMULU, 12893 reg: regInfo{ 12894 inputs: []inputInfo{ 12895 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12896 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12897 }, 12898 outputs: []outputInfo{ 12899 {0, 35184372088832}, // HI 12900 {1, 70368744177664}, // LO 12901 }, 12902 }, 12903 }, 12904 { 12905 name: "DIV", 12906 argLen: 2, 12907 asm: mips.ADIV, 12908 reg: regInfo{ 12909 inputs: []inputInfo{ 12910 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12911 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12912 }, 12913 outputs: []outputInfo{ 12914 {0, 35184372088832}, // HI 12915 {1, 70368744177664}, // LO 12916 }, 12917 }, 12918 }, 12919 { 12920 name: "DIVU", 12921 argLen: 2, 12922 asm: mips.ADIVU, 12923 reg: regInfo{ 12924 inputs: []inputInfo{ 12925 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12926 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12927 }, 12928 outputs: []outputInfo{ 12929 {0, 35184372088832}, // HI 12930 {1, 70368744177664}, // LO 12931 }, 12932 }, 12933 }, 12934 { 12935 name: "ADDF", 12936 argLen: 2, 12937 commutative: true, 12938 asm: mips.AADDF, 12939 reg: regInfo{ 12940 inputs: []inputInfo{ 12941 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12942 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12943 }, 12944 outputs: []outputInfo{ 12945 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12946 }, 12947 }, 12948 }, 12949 { 12950 name: "ADDD", 12951 argLen: 2, 12952 commutative: true, 12953 asm: mips.AADDD, 12954 reg: regInfo{ 12955 inputs: []inputInfo{ 12956 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12957 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12958 }, 12959 outputs: []outputInfo{ 12960 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12961 }, 12962 }, 12963 }, 12964 { 12965 name: "SUBF", 12966 argLen: 2, 12967 asm: mips.ASUBF, 12968 reg: regInfo{ 12969 inputs: []inputInfo{ 12970 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12971 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12972 }, 12973 outputs: []outputInfo{ 12974 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12975 }, 12976 }, 12977 }, 12978 { 12979 name: "SUBD", 12980 argLen: 2, 12981 asm: mips.ASUBD, 12982 reg: regInfo{ 12983 inputs: []inputInfo{ 12984 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12985 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12986 }, 12987 outputs: []outputInfo{ 12988 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12989 }, 12990 }, 12991 }, 12992 { 12993 name: "MULF", 12994 argLen: 2, 12995 commutative: true, 12996 asm: mips.AMULF, 12997 reg: regInfo{ 12998 inputs: []inputInfo{ 12999 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13000 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13001 }, 13002 outputs: []outputInfo{ 13003 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13004 }, 13005 }, 13006 }, 13007 { 13008 name: "MULD", 13009 argLen: 2, 13010 commutative: true, 13011 asm: mips.AMULD, 13012 reg: regInfo{ 13013 inputs: []inputInfo{ 13014 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13015 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13016 }, 13017 outputs: []outputInfo{ 13018 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13019 }, 13020 }, 13021 }, 13022 { 13023 name: "DIVF", 13024 argLen: 2, 13025 asm: mips.ADIVF, 13026 reg: regInfo{ 13027 inputs: []inputInfo{ 13028 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13029 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13030 }, 13031 outputs: []outputInfo{ 13032 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13033 }, 13034 }, 13035 }, 13036 { 13037 name: "DIVD", 13038 argLen: 2, 13039 asm: mips.ADIVD, 13040 reg: regInfo{ 13041 inputs: []inputInfo{ 13042 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13043 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13044 }, 13045 outputs: []outputInfo{ 13046 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13047 }, 13048 }, 13049 }, 13050 { 13051 name: "AND", 13052 argLen: 2, 13053 commutative: true, 13054 asm: mips.AAND, 13055 reg: regInfo{ 13056 inputs: []inputInfo{ 13057 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13058 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13059 }, 13060 outputs: []outputInfo{ 13061 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13062 }, 13063 }, 13064 }, 13065 { 13066 name: "ANDconst", 13067 auxType: auxInt32, 13068 argLen: 1, 13069 asm: mips.AAND, 13070 reg: regInfo{ 13071 inputs: []inputInfo{ 13072 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13073 }, 13074 outputs: []outputInfo{ 13075 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13076 }, 13077 }, 13078 }, 13079 { 13080 name: "OR", 13081 argLen: 2, 13082 commutative: true, 13083 asm: mips.AOR, 13084 reg: regInfo{ 13085 inputs: []inputInfo{ 13086 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13087 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13088 }, 13089 outputs: []outputInfo{ 13090 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13091 }, 13092 }, 13093 }, 13094 { 13095 name: "ORconst", 13096 auxType: auxInt32, 13097 argLen: 1, 13098 asm: mips.AOR, 13099 reg: regInfo{ 13100 inputs: []inputInfo{ 13101 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13102 }, 13103 outputs: []outputInfo{ 13104 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13105 }, 13106 }, 13107 }, 13108 { 13109 name: "XOR", 13110 argLen: 2, 13111 commutative: true, 13112 asm: mips.AXOR, 13113 reg: regInfo{ 13114 inputs: []inputInfo{ 13115 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13116 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13117 }, 13118 outputs: []outputInfo{ 13119 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13120 }, 13121 }, 13122 }, 13123 { 13124 name: "XORconst", 13125 auxType: auxInt32, 13126 argLen: 1, 13127 asm: mips.AXOR, 13128 reg: regInfo{ 13129 inputs: []inputInfo{ 13130 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13131 }, 13132 outputs: []outputInfo{ 13133 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13134 }, 13135 }, 13136 }, 13137 { 13138 name: "NOR", 13139 argLen: 2, 13140 commutative: true, 13141 asm: mips.ANOR, 13142 reg: regInfo{ 13143 inputs: []inputInfo{ 13144 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13145 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13146 }, 13147 outputs: []outputInfo{ 13148 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13149 }, 13150 }, 13151 }, 13152 { 13153 name: "NORconst", 13154 auxType: auxInt32, 13155 argLen: 1, 13156 asm: mips.ANOR, 13157 reg: regInfo{ 13158 inputs: []inputInfo{ 13159 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13160 }, 13161 outputs: []outputInfo{ 13162 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13163 }, 13164 }, 13165 }, 13166 { 13167 name: "NEG", 13168 argLen: 1, 13169 reg: regInfo{ 13170 inputs: []inputInfo{ 13171 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13172 }, 13173 outputs: []outputInfo{ 13174 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13175 }, 13176 }, 13177 }, 13178 { 13179 name: "NEGF", 13180 argLen: 1, 13181 asm: mips.ANEGF, 13182 reg: regInfo{ 13183 inputs: []inputInfo{ 13184 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13185 }, 13186 outputs: []outputInfo{ 13187 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13188 }, 13189 }, 13190 }, 13191 { 13192 name: "NEGD", 13193 argLen: 1, 13194 asm: mips.ANEGD, 13195 reg: regInfo{ 13196 inputs: []inputInfo{ 13197 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13198 }, 13199 outputs: []outputInfo{ 13200 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13201 }, 13202 }, 13203 }, 13204 { 13205 name: "SQRTD", 13206 argLen: 1, 13207 asm: mips.ASQRTD, 13208 reg: regInfo{ 13209 inputs: []inputInfo{ 13210 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13211 }, 13212 outputs: []outputInfo{ 13213 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13214 }, 13215 }, 13216 }, 13217 { 13218 name: "SLL", 13219 argLen: 2, 13220 asm: mips.ASLL, 13221 reg: regInfo{ 13222 inputs: []inputInfo{ 13223 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13224 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13225 }, 13226 outputs: []outputInfo{ 13227 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13228 }, 13229 }, 13230 }, 13231 { 13232 name: "SLLconst", 13233 auxType: auxInt32, 13234 argLen: 1, 13235 asm: mips.ASLL, 13236 reg: regInfo{ 13237 inputs: []inputInfo{ 13238 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13239 }, 13240 outputs: []outputInfo{ 13241 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13242 }, 13243 }, 13244 }, 13245 { 13246 name: "SRL", 13247 argLen: 2, 13248 asm: mips.ASRL, 13249 reg: regInfo{ 13250 inputs: []inputInfo{ 13251 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13252 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13253 }, 13254 outputs: []outputInfo{ 13255 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13256 }, 13257 }, 13258 }, 13259 { 13260 name: "SRLconst", 13261 auxType: auxInt32, 13262 argLen: 1, 13263 asm: mips.ASRL, 13264 reg: regInfo{ 13265 inputs: []inputInfo{ 13266 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13267 }, 13268 outputs: []outputInfo{ 13269 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13270 }, 13271 }, 13272 }, 13273 { 13274 name: "SRA", 13275 argLen: 2, 13276 asm: mips.ASRA, 13277 reg: regInfo{ 13278 inputs: []inputInfo{ 13279 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13280 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13281 }, 13282 outputs: []outputInfo{ 13283 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13284 }, 13285 }, 13286 }, 13287 { 13288 name: "SRAconst", 13289 auxType: auxInt32, 13290 argLen: 1, 13291 asm: mips.ASRA, 13292 reg: regInfo{ 13293 inputs: []inputInfo{ 13294 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13295 }, 13296 outputs: []outputInfo{ 13297 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13298 }, 13299 }, 13300 }, 13301 { 13302 name: "CLZ", 13303 argLen: 1, 13304 asm: mips.ACLZ, 13305 reg: regInfo{ 13306 inputs: []inputInfo{ 13307 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13308 }, 13309 outputs: []outputInfo{ 13310 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13311 }, 13312 }, 13313 }, 13314 { 13315 name: "SGT", 13316 argLen: 2, 13317 asm: mips.ASGT, 13318 reg: regInfo{ 13319 inputs: []inputInfo{ 13320 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13321 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13322 }, 13323 outputs: []outputInfo{ 13324 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13325 }, 13326 }, 13327 }, 13328 { 13329 name: "SGTconst", 13330 auxType: auxInt32, 13331 argLen: 1, 13332 asm: mips.ASGT, 13333 reg: regInfo{ 13334 inputs: []inputInfo{ 13335 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13336 }, 13337 outputs: []outputInfo{ 13338 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13339 }, 13340 }, 13341 }, 13342 { 13343 name: "SGTzero", 13344 argLen: 1, 13345 asm: mips.ASGT, 13346 reg: regInfo{ 13347 inputs: []inputInfo{ 13348 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13349 }, 13350 outputs: []outputInfo{ 13351 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13352 }, 13353 }, 13354 }, 13355 { 13356 name: "SGTU", 13357 argLen: 2, 13358 asm: mips.ASGTU, 13359 reg: regInfo{ 13360 inputs: []inputInfo{ 13361 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13362 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13363 }, 13364 outputs: []outputInfo{ 13365 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13366 }, 13367 }, 13368 }, 13369 { 13370 name: "SGTUconst", 13371 auxType: auxInt32, 13372 argLen: 1, 13373 asm: mips.ASGTU, 13374 reg: regInfo{ 13375 inputs: []inputInfo{ 13376 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13377 }, 13378 outputs: []outputInfo{ 13379 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13380 }, 13381 }, 13382 }, 13383 { 13384 name: "SGTUzero", 13385 argLen: 1, 13386 asm: mips.ASGTU, 13387 reg: regInfo{ 13388 inputs: []inputInfo{ 13389 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13390 }, 13391 outputs: []outputInfo{ 13392 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13393 }, 13394 }, 13395 }, 13396 { 13397 name: "CMPEQF", 13398 argLen: 2, 13399 asm: mips.ACMPEQF, 13400 reg: regInfo{ 13401 inputs: []inputInfo{ 13402 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13403 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13404 }, 13405 }, 13406 }, 13407 { 13408 name: "CMPEQD", 13409 argLen: 2, 13410 asm: mips.ACMPEQD, 13411 reg: regInfo{ 13412 inputs: []inputInfo{ 13413 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13414 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13415 }, 13416 }, 13417 }, 13418 { 13419 name: "CMPGEF", 13420 argLen: 2, 13421 asm: mips.ACMPGEF, 13422 reg: regInfo{ 13423 inputs: []inputInfo{ 13424 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13425 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13426 }, 13427 }, 13428 }, 13429 { 13430 name: "CMPGED", 13431 argLen: 2, 13432 asm: mips.ACMPGED, 13433 reg: regInfo{ 13434 inputs: []inputInfo{ 13435 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13436 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13437 }, 13438 }, 13439 }, 13440 { 13441 name: "CMPGTF", 13442 argLen: 2, 13443 asm: mips.ACMPGTF, 13444 reg: regInfo{ 13445 inputs: []inputInfo{ 13446 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13447 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13448 }, 13449 }, 13450 }, 13451 { 13452 name: "CMPGTD", 13453 argLen: 2, 13454 asm: mips.ACMPGTD, 13455 reg: regInfo{ 13456 inputs: []inputInfo{ 13457 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13458 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13459 }, 13460 }, 13461 }, 13462 { 13463 name: "MOVWconst", 13464 auxType: auxInt32, 13465 argLen: 0, 13466 rematerializeable: true, 13467 asm: mips.AMOVW, 13468 reg: regInfo{ 13469 outputs: []outputInfo{ 13470 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13471 }, 13472 }, 13473 }, 13474 { 13475 name: "MOVFconst", 13476 auxType: auxFloat32, 13477 argLen: 0, 13478 rematerializeable: true, 13479 asm: mips.AMOVF, 13480 reg: regInfo{ 13481 outputs: []outputInfo{ 13482 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13483 }, 13484 }, 13485 }, 13486 { 13487 name: "MOVDconst", 13488 auxType: auxFloat64, 13489 argLen: 0, 13490 rematerializeable: true, 13491 asm: mips.AMOVD, 13492 reg: regInfo{ 13493 outputs: []outputInfo{ 13494 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13495 }, 13496 }, 13497 }, 13498 { 13499 name: "MOVWaddr", 13500 auxType: auxSymOff, 13501 argLen: 1, 13502 rematerializeable: true, 13503 asm: mips.AMOVW, 13504 reg: regInfo{ 13505 inputs: []inputInfo{ 13506 {0, 140737555464192}, // SP SB 13507 }, 13508 outputs: []outputInfo{ 13509 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13510 }, 13511 }, 13512 }, 13513 { 13514 name: "MOVBload", 13515 auxType: auxSymOff, 13516 argLen: 2, 13517 faultOnNilArg0: true, 13518 asm: mips.AMOVB, 13519 reg: regInfo{ 13520 inputs: []inputInfo{ 13521 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13522 }, 13523 outputs: []outputInfo{ 13524 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13525 }, 13526 }, 13527 }, 13528 { 13529 name: "MOVBUload", 13530 auxType: auxSymOff, 13531 argLen: 2, 13532 faultOnNilArg0: true, 13533 asm: mips.AMOVBU, 13534 reg: regInfo{ 13535 inputs: []inputInfo{ 13536 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13537 }, 13538 outputs: []outputInfo{ 13539 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13540 }, 13541 }, 13542 }, 13543 { 13544 name: "MOVHload", 13545 auxType: auxSymOff, 13546 argLen: 2, 13547 faultOnNilArg0: true, 13548 asm: mips.AMOVH, 13549 reg: regInfo{ 13550 inputs: []inputInfo{ 13551 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13552 }, 13553 outputs: []outputInfo{ 13554 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13555 }, 13556 }, 13557 }, 13558 { 13559 name: "MOVHUload", 13560 auxType: auxSymOff, 13561 argLen: 2, 13562 faultOnNilArg0: true, 13563 asm: mips.AMOVHU, 13564 reg: regInfo{ 13565 inputs: []inputInfo{ 13566 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13567 }, 13568 outputs: []outputInfo{ 13569 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13570 }, 13571 }, 13572 }, 13573 { 13574 name: "MOVWload", 13575 auxType: auxSymOff, 13576 argLen: 2, 13577 faultOnNilArg0: true, 13578 asm: mips.AMOVW, 13579 reg: regInfo{ 13580 inputs: []inputInfo{ 13581 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13582 }, 13583 outputs: []outputInfo{ 13584 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13585 }, 13586 }, 13587 }, 13588 { 13589 name: "MOVFload", 13590 auxType: auxSymOff, 13591 argLen: 2, 13592 faultOnNilArg0: true, 13593 asm: mips.AMOVF, 13594 reg: regInfo{ 13595 inputs: []inputInfo{ 13596 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13597 }, 13598 outputs: []outputInfo{ 13599 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13600 }, 13601 }, 13602 }, 13603 { 13604 name: "MOVDload", 13605 auxType: auxSymOff, 13606 argLen: 2, 13607 faultOnNilArg0: true, 13608 asm: mips.AMOVD, 13609 reg: regInfo{ 13610 inputs: []inputInfo{ 13611 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13612 }, 13613 outputs: []outputInfo{ 13614 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13615 }, 13616 }, 13617 }, 13618 { 13619 name: "MOVBstore", 13620 auxType: auxSymOff, 13621 argLen: 3, 13622 faultOnNilArg0: true, 13623 asm: mips.AMOVB, 13624 reg: regInfo{ 13625 inputs: []inputInfo{ 13626 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13627 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13628 }, 13629 }, 13630 }, 13631 { 13632 name: "MOVHstore", 13633 auxType: auxSymOff, 13634 argLen: 3, 13635 faultOnNilArg0: true, 13636 asm: mips.AMOVH, 13637 reg: regInfo{ 13638 inputs: []inputInfo{ 13639 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13640 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13641 }, 13642 }, 13643 }, 13644 { 13645 name: "MOVWstore", 13646 auxType: auxSymOff, 13647 argLen: 3, 13648 faultOnNilArg0: true, 13649 asm: mips.AMOVW, 13650 reg: regInfo{ 13651 inputs: []inputInfo{ 13652 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13653 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13654 }, 13655 }, 13656 }, 13657 { 13658 name: "MOVFstore", 13659 auxType: auxSymOff, 13660 argLen: 3, 13661 faultOnNilArg0: true, 13662 asm: mips.AMOVF, 13663 reg: regInfo{ 13664 inputs: []inputInfo{ 13665 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13666 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13667 }, 13668 }, 13669 }, 13670 { 13671 name: "MOVDstore", 13672 auxType: auxSymOff, 13673 argLen: 3, 13674 faultOnNilArg0: true, 13675 asm: mips.AMOVD, 13676 reg: regInfo{ 13677 inputs: []inputInfo{ 13678 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13679 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13680 }, 13681 }, 13682 }, 13683 { 13684 name: "MOVBstorezero", 13685 auxType: auxSymOff, 13686 argLen: 2, 13687 faultOnNilArg0: true, 13688 asm: mips.AMOVB, 13689 reg: regInfo{ 13690 inputs: []inputInfo{ 13691 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13692 }, 13693 }, 13694 }, 13695 { 13696 name: "MOVHstorezero", 13697 auxType: auxSymOff, 13698 argLen: 2, 13699 faultOnNilArg0: true, 13700 asm: mips.AMOVH, 13701 reg: regInfo{ 13702 inputs: []inputInfo{ 13703 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13704 }, 13705 }, 13706 }, 13707 { 13708 name: "MOVWstorezero", 13709 auxType: auxSymOff, 13710 argLen: 2, 13711 faultOnNilArg0: true, 13712 asm: mips.AMOVW, 13713 reg: regInfo{ 13714 inputs: []inputInfo{ 13715 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13716 }, 13717 }, 13718 }, 13719 { 13720 name: "MOVBreg", 13721 argLen: 1, 13722 asm: mips.AMOVB, 13723 reg: regInfo{ 13724 inputs: []inputInfo{ 13725 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13726 }, 13727 outputs: []outputInfo{ 13728 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13729 }, 13730 }, 13731 }, 13732 { 13733 name: "MOVBUreg", 13734 argLen: 1, 13735 asm: mips.AMOVBU, 13736 reg: regInfo{ 13737 inputs: []inputInfo{ 13738 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13739 }, 13740 outputs: []outputInfo{ 13741 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13742 }, 13743 }, 13744 }, 13745 { 13746 name: "MOVHreg", 13747 argLen: 1, 13748 asm: mips.AMOVH, 13749 reg: regInfo{ 13750 inputs: []inputInfo{ 13751 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13752 }, 13753 outputs: []outputInfo{ 13754 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13755 }, 13756 }, 13757 }, 13758 { 13759 name: "MOVHUreg", 13760 argLen: 1, 13761 asm: mips.AMOVHU, 13762 reg: regInfo{ 13763 inputs: []inputInfo{ 13764 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13765 }, 13766 outputs: []outputInfo{ 13767 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13768 }, 13769 }, 13770 }, 13771 { 13772 name: "MOVWreg", 13773 argLen: 1, 13774 asm: mips.AMOVW, 13775 reg: regInfo{ 13776 inputs: []inputInfo{ 13777 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13778 }, 13779 outputs: []outputInfo{ 13780 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13781 }, 13782 }, 13783 }, 13784 { 13785 name: "MOVWnop", 13786 argLen: 1, 13787 resultInArg0: true, 13788 reg: regInfo{ 13789 inputs: []inputInfo{ 13790 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13791 }, 13792 outputs: []outputInfo{ 13793 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13794 }, 13795 }, 13796 }, 13797 { 13798 name: "CMOVZ", 13799 argLen: 3, 13800 resultInArg0: true, 13801 asm: mips.ACMOVZ, 13802 reg: regInfo{ 13803 inputs: []inputInfo{ 13804 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13805 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13806 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13807 }, 13808 outputs: []outputInfo{ 13809 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13810 }, 13811 }, 13812 }, 13813 { 13814 name: "CMOVZzero", 13815 argLen: 2, 13816 resultInArg0: true, 13817 asm: mips.ACMOVZ, 13818 reg: regInfo{ 13819 inputs: []inputInfo{ 13820 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13821 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13822 }, 13823 outputs: []outputInfo{ 13824 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13825 }, 13826 }, 13827 }, 13828 { 13829 name: "MOVWF", 13830 argLen: 1, 13831 asm: mips.AMOVWF, 13832 reg: regInfo{ 13833 inputs: []inputInfo{ 13834 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13835 }, 13836 outputs: []outputInfo{ 13837 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13838 }, 13839 }, 13840 }, 13841 { 13842 name: "MOVWD", 13843 argLen: 1, 13844 asm: mips.AMOVWD, 13845 reg: regInfo{ 13846 inputs: []inputInfo{ 13847 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13848 }, 13849 outputs: []outputInfo{ 13850 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13851 }, 13852 }, 13853 }, 13854 { 13855 name: "TRUNCFW", 13856 argLen: 1, 13857 asm: mips.ATRUNCFW, 13858 reg: regInfo{ 13859 inputs: []inputInfo{ 13860 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13861 }, 13862 outputs: []outputInfo{ 13863 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13864 }, 13865 }, 13866 }, 13867 { 13868 name: "TRUNCDW", 13869 argLen: 1, 13870 asm: mips.ATRUNCDW, 13871 reg: regInfo{ 13872 inputs: []inputInfo{ 13873 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13874 }, 13875 outputs: []outputInfo{ 13876 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13877 }, 13878 }, 13879 }, 13880 { 13881 name: "MOVFD", 13882 argLen: 1, 13883 asm: mips.AMOVFD, 13884 reg: regInfo{ 13885 inputs: []inputInfo{ 13886 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13887 }, 13888 outputs: []outputInfo{ 13889 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13890 }, 13891 }, 13892 }, 13893 { 13894 name: "MOVDF", 13895 argLen: 1, 13896 asm: mips.AMOVDF, 13897 reg: regInfo{ 13898 inputs: []inputInfo{ 13899 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13900 }, 13901 outputs: []outputInfo{ 13902 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13903 }, 13904 }, 13905 }, 13906 { 13907 name: "CALLstatic", 13908 auxType: auxSymOff, 13909 argLen: 1, 13910 clobberFlags: true, 13911 call: true, 13912 reg: regInfo{ 13913 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13914 }, 13915 }, 13916 { 13917 name: "CALLclosure", 13918 auxType: auxInt32, 13919 argLen: 3, 13920 clobberFlags: true, 13921 call: true, 13922 reg: regInfo{ 13923 inputs: []inputInfo{ 13924 {1, 4194304}, // R22 13925 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 13926 }, 13927 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13928 }, 13929 }, 13930 { 13931 name: "CALLdefer", 13932 auxType: auxInt32, 13933 argLen: 1, 13934 clobberFlags: true, 13935 call: true, 13936 reg: regInfo{ 13937 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13938 }, 13939 }, 13940 { 13941 name: "CALLgo", 13942 auxType: auxInt32, 13943 argLen: 1, 13944 clobberFlags: true, 13945 call: true, 13946 reg: regInfo{ 13947 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13948 }, 13949 }, 13950 { 13951 name: "CALLinter", 13952 auxType: auxInt32, 13953 argLen: 2, 13954 clobberFlags: true, 13955 call: true, 13956 reg: regInfo{ 13957 inputs: []inputInfo{ 13958 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13959 }, 13960 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13961 }, 13962 }, 13963 { 13964 name: "LoweredAtomicLoad", 13965 argLen: 2, 13966 faultOnNilArg0: true, 13967 reg: regInfo{ 13968 inputs: []inputInfo{ 13969 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13970 }, 13971 outputs: []outputInfo{ 13972 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13973 }, 13974 }, 13975 }, 13976 { 13977 name: "LoweredAtomicStore", 13978 argLen: 3, 13979 faultOnNilArg0: true, 13980 reg: regInfo{ 13981 inputs: []inputInfo{ 13982 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13983 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13984 }, 13985 }, 13986 }, 13987 { 13988 name: "LoweredAtomicStorezero", 13989 argLen: 2, 13990 faultOnNilArg0: true, 13991 reg: regInfo{ 13992 inputs: []inputInfo{ 13993 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13994 }, 13995 }, 13996 }, 13997 { 13998 name: "LoweredAtomicExchange", 13999 argLen: 3, 14000 resultNotInArgs: true, 14001 faultOnNilArg0: true, 14002 reg: regInfo{ 14003 inputs: []inputInfo{ 14004 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14005 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14006 }, 14007 outputs: []outputInfo{ 14008 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14009 }, 14010 }, 14011 }, 14012 { 14013 name: "LoweredAtomicAdd", 14014 argLen: 3, 14015 resultNotInArgs: true, 14016 faultOnNilArg0: true, 14017 reg: regInfo{ 14018 inputs: []inputInfo{ 14019 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14020 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14021 }, 14022 outputs: []outputInfo{ 14023 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14024 }, 14025 }, 14026 }, 14027 { 14028 name: "LoweredAtomicAddconst", 14029 auxType: auxInt32, 14030 argLen: 2, 14031 resultNotInArgs: true, 14032 faultOnNilArg0: true, 14033 reg: regInfo{ 14034 inputs: []inputInfo{ 14035 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14036 }, 14037 outputs: []outputInfo{ 14038 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14039 }, 14040 }, 14041 }, 14042 { 14043 name: "LoweredAtomicCas", 14044 argLen: 4, 14045 resultNotInArgs: true, 14046 faultOnNilArg0: true, 14047 reg: regInfo{ 14048 inputs: []inputInfo{ 14049 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14050 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14051 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14052 }, 14053 outputs: []outputInfo{ 14054 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14055 }, 14056 }, 14057 }, 14058 { 14059 name: "LoweredAtomicAnd", 14060 argLen: 3, 14061 faultOnNilArg0: true, 14062 asm: mips.AAND, 14063 reg: regInfo{ 14064 inputs: []inputInfo{ 14065 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14066 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14067 }, 14068 }, 14069 }, 14070 { 14071 name: "LoweredAtomicOr", 14072 argLen: 3, 14073 faultOnNilArg0: true, 14074 asm: mips.AOR, 14075 reg: regInfo{ 14076 inputs: []inputInfo{ 14077 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14078 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14079 }, 14080 }, 14081 }, 14082 { 14083 name: "LoweredZero", 14084 auxType: auxInt32, 14085 argLen: 3, 14086 faultOnNilArg0: true, 14087 reg: regInfo{ 14088 inputs: []inputInfo{ 14089 {0, 2}, // R1 14090 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14091 }, 14092 clobbers: 2, // R1 14093 }, 14094 }, 14095 { 14096 name: "LoweredMove", 14097 auxType: auxInt32, 14098 argLen: 4, 14099 faultOnNilArg0: true, 14100 faultOnNilArg1: true, 14101 reg: regInfo{ 14102 inputs: []inputInfo{ 14103 {0, 4}, // R2 14104 {1, 2}, // R1 14105 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14106 }, 14107 clobbers: 6, // R1 R2 14108 }, 14109 }, 14110 { 14111 name: "LoweredNilCheck", 14112 argLen: 2, 14113 nilCheck: true, 14114 faultOnNilArg0: true, 14115 reg: regInfo{ 14116 inputs: []inputInfo{ 14117 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14118 }, 14119 }, 14120 }, 14121 { 14122 name: "FPFlagTrue", 14123 argLen: 1, 14124 reg: regInfo{ 14125 outputs: []outputInfo{ 14126 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14127 }, 14128 }, 14129 }, 14130 { 14131 name: "FPFlagFalse", 14132 argLen: 1, 14133 reg: regInfo{ 14134 outputs: []outputInfo{ 14135 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14136 }, 14137 }, 14138 }, 14139 { 14140 name: "LoweredGetClosurePtr", 14141 argLen: 0, 14142 reg: regInfo{ 14143 outputs: []outputInfo{ 14144 {0, 4194304}, // R22 14145 }, 14146 }, 14147 }, 14148 { 14149 name: "MOVWconvert", 14150 argLen: 2, 14151 asm: mips.AMOVW, 14152 reg: regInfo{ 14153 inputs: []inputInfo{ 14154 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14155 }, 14156 outputs: []outputInfo{ 14157 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14158 }, 14159 }, 14160 }, 14161 14162 { 14163 name: "ADDV", 14164 argLen: 2, 14165 commutative: true, 14166 asm: mips.AADDVU, 14167 reg: regInfo{ 14168 inputs: []inputInfo{ 14169 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14170 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14171 }, 14172 outputs: []outputInfo{ 14173 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14174 }, 14175 }, 14176 }, 14177 { 14178 name: "ADDVconst", 14179 auxType: auxInt64, 14180 argLen: 1, 14181 asm: mips.AADDVU, 14182 reg: regInfo{ 14183 inputs: []inputInfo{ 14184 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14185 }, 14186 outputs: []outputInfo{ 14187 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14188 }, 14189 }, 14190 }, 14191 { 14192 name: "SUBV", 14193 argLen: 2, 14194 asm: mips.ASUBVU, 14195 reg: regInfo{ 14196 inputs: []inputInfo{ 14197 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14198 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14199 }, 14200 outputs: []outputInfo{ 14201 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14202 }, 14203 }, 14204 }, 14205 { 14206 name: "SUBVconst", 14207 auxType: auxInt64, 14208 argLen: 1, 14209 asm: mips.ASUBVU, 14210 reg: regInfo{ 14211 inputs: []inputInfo{ 14212 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14213 }, 14214 outputs: []outputInfo{ 14215 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14216 }, 14217 }, 14218 }, 14219 { 14220 name: "MULV", 14221 argLen: 2, 14222 commutative: true, 14223 asm: mips.AMULV, 14224 reg: regInfo{ 14225 inputs: []inputInfo{ 14226 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14227 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14228 }, 14229 outputs: []outputInfo{ 14230 {0, 1152921504606846976}, // HI 14231 {1, 2305843009213693952}, // LO 14232 }, 14233 }, 14234 }, 14235 { 14236 name: "MULVU", 14237 argLen: 2, 14238 commutative: true, 14239 asm: mips.AMULVU, 14240 reg: regInfo{ 14241 inputs: []inputInfo{ 14242 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14243 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14244 }, 14245 outputs: []outputInfo{ 14246 {0, 1152921504606846976}, // HI 14247 {1, 2305843009213693952}, // LO 14248 }, 14249 }, 14250 }, 14251 { 14252 name: "DIVV", 14253 argLen: 2, 14254 asm: mips.ADIVV, 14255 reg: regInfo{ 14256 inputs: []inputInfo{ 14257 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14258 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14259 }, 14260 outputs: []outputInfo{ 14261 {0, 1152921504606846976}, // HI 14262 {1, 2305843009213693952}, // LO 14263 }, 14264 }, 14265 }, 14266 { 14267 name: "DIVVU", 14268 argLen: 2, 14269 asm: mips.ADIVVU, 14270 reg: regInfo{ 14271 inputs: []inputInfo{ 14272 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14273 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14274 }, 14275 outputs: []outputInfo{ 14276 {0, 1152921504606846976}, // HI 14277 {1, 2305843009213693952}, // LO 14278 }, 14279 }, 14280 }, 14281 { 14282 name: "ADDF", 14283 argLen: 2, 14284 commutative: true, 14285 asm: mips.AADDF, 14286 reg: regInfo{ 14287 inputs: []inputInfo{ 14288 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14289 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14290 }, 14291 outputs: []outputInfo{ 14292 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14293 }, 14294 }, 14295 }, 14296 { 14297 name: "ADDD", 14298 argLen: 2, 14299 commutative: true, 14300 asm: mips.AADDD, 14301 reg: regInfo{ 14302 inputs: []inputInfo{ 14303 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14304 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14305 }, 14306 outputs: []outputInfo{ 14307 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14308 }, 14309 }, 14310 }, 14311 { 14312 name: "SUBF", 14313 argLen: 2, 14314 asm: mips.ASUBF, 14315 reg: regInfo{ 14316 inputs: []inputInfo{ 14317 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14318 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14319 }, 14320 outputs: []outputInfo{ 14321 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14322 }, 14323 }, 14324 }, 14325 { 14326 name: "SUBD", 14327 argLen: 2, 14328 asm: mips.ASUBD, 14329 reg: regInfo{ 14330 inputs: []inputInfo{ 14331 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14332 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14333 }, 14334 outputs: []outputInfo{ 14335 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14336 }, 14337 }, 14338 }, 14339 { 14340 name: "MULF", 14341 argLen: 2, 14342 commutative: true, 14343 asm: mips.AMULF, 14344 reg: regInfo{ 14345 inputs: []inputInfo{ 14346 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14347 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14348 }, 14349 outputs: []outputInfo{ 14350 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14351 }, 14352 }, 14353 }, 14354 { 14355 name: "MULD", 14356 argLen: 2, 14357 commutative: true, 14358 asm: mips.AMULD, 14359 reg: regInfo{ 14360 inputs: []inputInfo{ 14361 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14362 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14363 }, 14364 outputs: []outputInfo{ 14365 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14366 }, 14367 }, 14368 }, 14369 { 14370 name: "DIVF", 14371 argLen: 2, 14372 asm: mips.ADIVF, 14373 reg: regInfo{ 14374 inputs: []inputInfo{ 14375 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14376 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14377 }, 14378 outputs: []outputInfo{ 14379 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14380 }, 14381 }, 14382 }, 14383 { 14384 name: "DIVD", 14385 argLen: 2, 14386 asm: mips.ADIVD, 14387 reg: regInfo{ 14388 inputs: []inputInfo{ 14389 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14390 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14391 }, 14392 outputs: []outputInfo{ 14393 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14394 }, 14395 }, 14396 }, 14397 { 14398 name: "AND", 14399 argLen: 2, 14400 commutative: true, 14401 asm: mips.AAND, 14402 reg: regInfo{ 14403 inputs: []inputInfo{ 14404 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14405 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14406 }, 14407 outputs: []outputInfo{ 14408 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14409 }, 14410 }, 14411 }, 14412 { 14413 name: "ANDconst", 14414 auxType: auxInt64, 14415 argLen: 1, 14416 asm: mips.AAND, 14417 reg: regInfo{ 14418 inputs: []inputInfo{ 14419 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14420 }, 14421 outputs: []outputInfo{ 14422 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14423 }, 14424 }, 14425 }, 14426 { 14427 name: "OR", 14428 argLen: 2, 14429 commutative: true, 14430 asm: mips.AOR, 14431 reg: regInfo{ 14432 inputs: []inputInfo{ 14433 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14434 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14435 }, 14436 outputs: []outputInfo{ 14437 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14438 }, 14439 }, 14440 }, 14441 { 14442 name: "ORconst", 14443 auxType: auxInt64, 14444 argLen: 1, 14445 asm: mips.AOR, 14446 reg: regInfo{ 14447 inputs: []inputInfo{ 14448 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14449 }, 14450 outputs: []outputInfo{ 14451 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14452 }, 14453 }, 14454 }, 14455 { 14456 name: "XOR", 14457 argLen: 2, 14458 commutative: true, 14459 asm: mips.AXOR, 14460 reg: regInfo{ 14461 inputs: []inputInfo{ 14462 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14463 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14464 }, 14465 outputs: []outputInfo{ 14466 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14467 }, 14468 }, 14469 }, 14470 { 14471 name: "XORconst", 14472 auxType: auxInt64, 14473 argLen: 1, 14474 asm: mips.AXOR, 14475 reg: regInfo{ 14476 inputs: []inputInfo{ 14477 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14478 }, 14479 outputs: []outputInfo{ 14480 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14481 }, 14482 }, 14483 }, 14484 { 14485 name: "NOR", 14486 argLen: 2, 14487 commutative: true, 14488 asm: mips.ANOR, 14489 reg: regInfo{ 14490 inputs: []inputInfo{ 14491 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14492 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14493 }, 14494 outputs: []outputInfo{ 14495 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14496 }, 14497 }, 14498 }, 14499 { 14500 name: "NORconst", 14501 auxType: auxInt64, 14502 argLen: 1, 14503 asm: mips.ANOR, 14504 reg: regInfo{ 14505 inputs: []inputInfo{ 14506 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14507 }, 14508 outputs: []outputInfo{ 14509 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14510 }, 14511 }, 14512 }, 14513 { 14514 name: "NEGV", 14515 argLen: 1, 14516 reg: regInfo{ 14517 inputs: []inputInfo{ 14518 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14519 }, 14520 outputs: []outputInfo{ 14521 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14522 }, 14523 }, 14524 }, 14525 { 14526 name: "NEGF", 14527 argLen: 1, 14528 asm: mips.ANEGF, 14529 reg: regInfo{ 14530 inputs: []inputInfo{ 14531 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14532 }, 14533 outputs: []outputInfo{ 14534 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14535 }, 14536 }, 14537 }, 14538 { 14539 name: "NEGD", 14540 argLen: 1, 14541 asm: mips.ANEGD, 14542 reg: regInfo{ 14543 inputs: []inputInfo{ 14544 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14545 }, 14546 outputs: []outputInfo{ 14547 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14548 }, 14549 }, 14550 }, 14551 { 14552 name: "SLLV", 14553 argLen: 2, 14554 asm: mips.ASLLV, 14555 reg: regInfo{ 14556 inputs: []inputInfo{ 14557 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14558 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14559 }, 14560 outputs: []outputInfo{ 14561 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14562 }, 14563 }, 14564 }, 14565 { 14566 name: "SLLVconst", 14567 auxType: auxInt64, 14568 argLen: 1, 14569 asm: mips.ASLLV, 14570 reg: regInfo{ 14571 inputs: []inputInfo{ 14572 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14573 }, 14574 outputs: []outputInfo{ 14575 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14576 }, 14577 }, 14578 }, 14579 { 14580 name: "SRLV", 14581 argLen: 2, 14582 asm: mips.ASRLV, 14583 reg: regInfo{ 14584 inputs: []inputInfo{ 14585 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14586 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14587 }, 14588 outputs: []outputInfo{ 14589 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14590 }, 14591 }, 14592 }, 14593 { 14594 name: "SRLVconst", 14595 auxType: auxInt64, 14596 argLen: 1, 14597 asm: mips.ASRLV, 14598 reg: regInfo{ 14599 inputs: []inputInfo{ 14600 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14601 }, 14602 outputs: []outputInfo{ 14603 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14604 }, 14605 }, 14606 }, 14607 { 14608 name: "SRAV", 14609 argLen: 2, 14610 asm: mips.ASRAV, 14611 reg: regInfo{ 14612 inputs: []inputInfo{ 14613 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14614 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14615 }, 14616 outputs: []outputInfo{ 14617 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14618 }, 14619 }, 14620 }, 14621 { 14622 name: "SRAVconst", 14623 auxType: auxInt64, 14624 argLen: 1, 14625 asm: mips.ASRAV, 14626 reg: regInfo{ 14627 inputs: []inputInfo{ 14628 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14629 }, 14630 outputs: []outputInfo{ 14631 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14632 }, 14633 }, 14634 }, 14635 { 14636 name: "SGT", 14637 argLen: 2, 14638 asm: mips.ASGT, 14639 reg: regInfo{ 14640 inputs: []inputInfo{ 14641 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14642 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14643 }, 14644 outputs: []outputInfo{ 14645 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14646 }, 14647 }, 14648 }, 14649 { 14650 name: "SGTconst", 14651 auxType: auxInt64, 14652 argLen: 1, 14653 asm: mips.ASGT, 14654 reg: regInfo{ 14655 inputs: []inputInfo{ 14656 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14657 }, 14658 outputs: []outputInfo{ 14659 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14660 }, 14661 }, 14662 }, 14663 { 14664 name: "SGTU", 14665 argLen: 2, 14666 asm: mips.ASGTU, 14667 reg: regInfo{ 14668 inputs: []inputInfo{ 14669 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14670 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14671 }, 14672 outputs: []outputInfo{ 14673 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14674 }, 14675 }, 14676 }, 14677 { 14678 name: "SGTUconst", 14679 auxType: auxInt64, 14680 argLen: 1, 14681 asm: mips.ASGTU, 14682 reg: regInfo{ 14683 inputs: []inputInfo{ 14684 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14685 }, 14686 outputs: []outputInfo{ 14687 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14688 }, 14689 }, 14690 }, 14691 { 14692 name: "CMPEQF", 14693 argLen: 2, 14694 asm: mips.ACMPEQF, 14695 reg: regInfo{ 14696 inputs: []inputInfo{ 14697 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14698 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14699 }, 14700 }, 14701 }, 14702 { 14703 name: "CMPEQD", 14704 argLen: 2, 14705 asm: mips.ACMPEQD, 14706 reg: regInfo{ 14707 inputs: []inputInfo{ 14708 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14709 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14710 }, 14711 }, 14712 }, 14713 { 14714 name: "CMPGEF", 14715 argLen: 2, 14716 asm: mips.ACMPGEF, 14717 reg: regInfo{ 14718 inputs: []inputInfo{ 14719 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14720 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14721 }, 14722 }, 14723 }, 14724 { 14725 name: "CMPGED", 14726 argLen: 2, 14727 asm: mips.ACMPGED, 14728 reg: regInfo{ 14729 inputs: []inputInfo{ 14730 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14731 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14732 }, 14733 }, 14734 }, 14735 { 14736 name: "CMPGTF", 14737 argLen: 2, 14738 asm: mips.ACMPGTF, 14739 reg: regInfo{ 14740 inputs: []inputInfo{ 14741 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14742 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14743 }, 14744 }, 14745 }, 14746 { 14747 name: "CMPGTD", 14748 argLen: 2, 14749 asm: mips.ACMPGTD, 14750 reg: regInfo{ 14751 inputs: []inputInfo{ 14752 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14753 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14754 }, 14755 }, 14756 }, 14757 { 14758 name: "MOVVconst", 14759 auxType: auxInt64, 14760 argLen: 0, 14761 rematerializeable: true, 14762 asm: mips.AMOVV, 14763 reg: regInfo{ 14764 outputs: []outputInfo{ 14765 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14766 }, 14767 }, 14768 }, 14769 { 14770 name: "MOVFconst", 14771 auxType: auxFloat64, 14772 argLen: 0, 14773 rematerializeable: true, 14774 asm: mips.AMOVF, 14775 reg: regInfo{ 14776 outputs: []outputInfo{ 14777 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14778 }, 14779 }, 14780 }, 14781 { 14782 name: "MOVDconst", 14783 auxType: auxFloat64, 14784 argLen: 0, 14785 rematerializeable: true, 14786 asm: mips.AMOVD, 14787 reg: regInfo{ 14788 outputs: []outputInfo{ 14789 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14790 }, 14791 }, 14792 }, 14793 { 14794 name: "MOVVaddr", 14795 auxType: auxSymOff, 14796 argLen: 1, 14797 rematerializeable: true, 14798 asm: mips.AMOVV, 14799 reg: regInfo{ 14800 inputs: []inputInfo{ 14801 {0, 4611686018460942336}, // SP SB 14802 }, 14803 outputs: []outputInfo{ 14804 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14805 }, 14806 }, 14807 }, 14808 { 14809 name: "MOVBload", 14810 auxType: auxSymOff, 14811 argLen: 2, 14812 faultOnNilArg0: true, 14813 asm: mips.AMOVB, 14814 reg: regInfo{ 14815 inputs: []inputInfo{ 14816 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14817 }, 14818 outputs: []outputInfo{ 14819 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14820 }, 14821 }, 14822 }, 14823 { 14824 name: "MOVBUload", 14825 auxType: auxSymOff, 14826 argLen: 2, 14827 faultOnNilArg0: true, 14828 asm: mips.AMOVBU, 14829 reg: regInfo{ 14830 inputs: []inputInfo{ 14831 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14832 }, 14833 outputs: []outputInfo{ 14834 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14835 }, 14836 }, 14837 }, 14838 { 14839 name: "MOVHload", 14840 auxType: auxSymOff, 14841 argLen: 2, 14842 faultOnNilArg0: true, 14843 asm: mips.AMOVH, 14844 reg: regInfo{ 14845 inputs: []inputInfo{ 14846 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14847 }, 14848 outputs: []outputInfo{ 14849 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14850 }, 14851 }, 14852 }, 14853 { 14854 name: "MOVHUload", 14855 auxType: auxSymOff, 14856 argLen: 2, 14857 faultOnNilArg0: true, 14858 asm: mips.AMOVHU, 14859 reg: regInfo{ 14860 inputs: []inputInfo{ 14861 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14862 }, 14863 outputs: []outputInfo{ 14864 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14865 }, 14866 }, 14867 }, 14868 { 14869 name: "MOVWload", 14870 auxType: auxSymOff, 14871 argLen: 2, 14872 faultOnNilArg0: true, 14873 asm: mips.AMOVW, 14874 reg: regInfo{ 14875 inputs: []inputInfo{ 14876 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14877 }, 14878 outputs: []outputInfo{ 14879 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14880 }, 14881 }, 14882 }, 14883 { 14884 name: "MOVWUload", 14885 auxType: auxSymOff, 14886 argLen: 2, 14887 faultOnNilArg0: true, 14888 asm: mips.AMOVWU, 14889 reg: regInfo{ 14890 inputs: []inputInfo{ 14891 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14892 }, 14893 outputs: []outputInfo{ 14894 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14895 }, 14896 }, 14897 }, 14898 { 14899 name: "MOVVload", 14900 auxType: auxSymOff, 14901 argLen: 2, 14902 faultOnNilArg0: true, 14903 asm: mips.AMOVV, 14904 reg: regInfo{ 14905 inputs: []inputInfo{ 14906 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14907 }, 14908 outputs: []outputInfo{ 14909 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14910 }, 14911 }, 14912 }, 14913 { 14914 name: "MOVFload", 14915 auxType: auxSymOff, 14916 argLen: 2, 14917 faultOnNilArg0: true, 14918 asm: mips.AMOVF, 14919 reg: regInfo{ 14920 inputs: []inputInfo{ 14921 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14922 }, 14923 outputs: []outputInfo{ 14924 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14925 }, 14926 }, 14927 }, 14928 { 14929 name: "MOVDload", 14930 auxType: auxSymOff, 14931 argLen: 2, 14932 faultOnNilArg0: true, 14933 asm: mips.AMOVD, 14934 reg: regInfo{ 14935 inputs: []inputInfo{ 14936 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14937 }, 14938 outputs: []outputInfo{ 14939 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14940 }, 14941 }, 14942 }, 14943 { 14944 name: "MOVBstore", 14945 auxType: auxSymOff, 14946 argLen: 3, 14947 faultOnNilArg0: true, 14948 asm: mips.AMOVB, 14949 reg: regInfo{ 14950 inputs: []inputInfo{ 14951 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14952 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14953 }, 14954 }, 14955 }, 14956 { 14957 name: "MOVHstore", 14958 auxType: auxSymOff, 14959 argLen: 3, 14960 faultOnNilArg0: true, 14961 asm: mips.AMOVH, 14962 reg: regInfo{ 14963 inputs: []inputInfo{ 14964 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14965 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14966 }, 14967 }, 14968 }, 14969 { 14970 name: "MOVWstore", 14971 auxType: auxSymOff, 14972 argLen: 3, 14973 faultOnNilArg0: true, 14974 asm: mips.AMOVW, 14975 reg: regInfo{ 14976 inputs: []inputInfo{ 14977 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14978 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14979 }, 14980 }, 14981 }, 14982 { 14983 name: "MOVVstore", 14984 auxType: auxSymOff, 14985 argLen: 3, 14986 faultOnNilArg0: true, 14987 asm: mips.AMOVV, 14988 reg: regInfo{ 14989 inputs: []inputInfo{ 14990 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14991 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14992 }, 14993 }, 14994 }, 14995 { 14996 name: "MOVFstore", 14997 auxType: auxSymOff, 14998 argLen: 3, 14999 faultOnNilArg0: true, 15000 asm: mips.AMOVF, 15001 reg: regInfo{ 15002 inputs: []inputInfo{ 15003 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15004 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15005 }, 15006 }, 15007 }, 15008 { 15009 name: "MOVDstore", 15010 auxType: auxSymOff, 15011 argLen: 3, 15012 faultOnNilArg0: true, 15013 asm: mips.AMOVD, 15014 reg: regInfo{ 15015 inputs: []inputInfo{ 15016 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15017 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15018 }, 15019 }, 15020 }, 15021 { 15022 name: "MOVBstorezero", 15023 auxType: auxSymOff, 15024 argLen: 2, 15025 faultOnNilArg0: true, 15026 asm: mips.AMOVB, 15027 reg: regInfo{ 15028 inputs: []inputInfo{ 15029 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15030 }, 15031 }, 15032 }, 15033 { 15034 name: "MOVHstorezero", 15035 auxType: auxSymOff, 15036 argLen: 2, 15037 faultOnNilArg0: true, 15038 asm: mips.AMOVH, 15039 reg: regInfo{ 15040 inputs: []inputInfo{ 15041 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15042 }, 15043 }, 15044 }, 15045 { 15046 name: "MOVWstorezero", 15047 auxType: auxSymOff, 15048 argLen: 2, 15049 faultOnNilArg0: true, 15050 asm: mips.AMOVW, 15051 reg: regInfo{ 15052 inputs: []inputInfo{ 15053 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15054 }, 15055 }, 15056 }, 15057 { 15058 name: "MOVVstorezero", 15059 auxType: auxSymOff, 15060 argLen: 2, 15061 faultOnNilArg0: true, 15062 asm: mips.AMOVV, 15063 reg: regInfo{ 15064 inputs: []inputInfo{ 15065 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15066 }, 15067 }, 15068 }, 15069 { 15070 name: "MOVBreg", 15071 argLen: 1, 15072 asm: mips.AMOVB, 15073 reg: regInfo{ 15074 inputs: []inputInfo{ 15075 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15076 }, 15077 outputs: []outputInfo{ 15078 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15079 }, 15080 }, 15081 }, 15082 { 15083 name: "MOVBUreg", 15084 argLen: 1, 15085 asm: mips.AMOVBU, 15086 reg: regInfo{ 15087 inputs: []inputInfo{ 15088 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15089 }, 15090 outputs: []outputInfo{ 15091 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15092 }, 15093 }, 15094 }, 15095 { 15096 name: "MOVHreg", 15097 argLen: 1, 15098 asm: mips.AMOVH, 15099 reg: regInfo{ 15100 inputs: []inputInfo{ 15101 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15102 }, 15103 outputs: []outputInfo{ 15104 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15105 }, 15106 }, 15107 }, 15108 { 15109 name: "MOVHUreg", 15110 argLen: 1, 15111 asm: mips.AMOVHU, 15112 reg: regInfo{ 15113 inputs: []inputInfo{ 15114 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15115 }, 15116 outputs: []outputInfo{ 15117 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15118 }, 15119 }, 15120 }, 15121 { 15122 name: "MOVWreg", 15123 argLen: 1, 15124 asm: mips.AMOVW, 15125 reg: regInfo{ 15126 inputs: []inputInfo{ 15127 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15128 }, 15129 outputs: []outputInfo{ 15130 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15131 }, 15132 }, 15133 }, 15134 { 15135 name: "MOVWUreg", 15136 argLen: 1, 15137 asm: mips.AMOVWU, 15138 reg: regInfo{ 15139 inputs: []inputInfo{ 15140 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15141 }, 15142 outputs: []outputInfo{ 15143 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15144 }, 15145 }, 15146 }, 15147 { 15148 name: "MOVVreg", 15149 argLen: 1, 15150 asm: mips.AMOVV, 15151 reg: regInfo{ 15152 inputs: []inputInfo{ 15153 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15154 }, 15155 outputs: []outputInfo{ 15156 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15157 }, 15158 }, 15159 }, 15160 { 15161 name: "MOVVnop", 15162 argLen: 1, 15163 resultInArg0: true, 15164 reg: regInfo{ 15165 inputs: []inputInfo{ 15166 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15167 }, 15168 outputs: []outputInfo{ 15169 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15170 }, 15171 }, 15172 }, 15173 { 15174 name: "MOVWF", 15175 argLen: 1, 15176 asm: mips.AMOVWF, 15177 reg: regInfo{ 15178 inputs: []inputInfo{ 15179 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15180 }, 15181 outputs: []outputInfo{ 15182 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15183 }, 15184 }, 15185 }, 15186 { 15187 name: "MOVWD", 15188 argLen: 1, 15189 asm: mips.AMOVWD, 15190 reg: regInfo{ 15191 inputs: []inputInfo{ 15192 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15193 }, 15194 outputs: []outputInfo{ 15195 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15196 }, 15197 }, 15198 }, 15199 { 15200 name: "MOVVF", 15201 argLen: 1, 15202 asm: mips.AMOVVF, 15203 reg: regInfo{ 15204 inputs: []inputInfo{ 15205 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15206 }, 15207 outputs: []outputInfo{ 15208 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15209 }, 15210 }, 15211 }, 15212 { 15213 name: "MOVVD", 15214 argLen: 1, 15215 asm: mips.AMOVVD, 15216 reg: regInfo{ 15217 inputs: []inputInfo{ 15218 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15219 }, 15220 outputs: []outputInfo{ 15221 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15222 }, 15223 }, 15224 }, 15225 { 15226 name: "TRUNCFW", 15227 argLen: 1, 15228 asm: mips.ATRUNCFW, 15229 reg: regInfo{ 15230 inputs: []inputInfo{ 15231 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15232 }, 15233 outputs: []outputInfo{ 15234 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15235 }, 15236 }, 15237 }, 15238 { 15239 name: "TRUNCDW", 15240 argLen: 1, 15241 asm: mips.ATRUNCDW, 15242 reg: regInfo{ 15243 inputs: []inputInfo{ 15244 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15245 }, 15246 outputs: []outputInfo{ 15247 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15248 }, 15249 }, 15250 }, 15251 { 15252 name: "TRUNCFV", 15253 argLen: 1, 15254 asm: mips.ATRUNCFV, 15255 reg: regInfo{ 15256 inputs: []inputInfo{ 15257 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15258 }, 15259 outputs: []outputInfo{ 15260 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15261 }, 15262 }, 15263 }, 15264 { 15265 name: "TRUNCDV", 15266 argLen: 1, 15267 asm: mips.ATRUNCDV, 15268 reg: regInfo{ 15269 inputs: []inputInfo{ 15270 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15271 }, 15272 outputs: []outputInfo{ 15273 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15274 }, 15275 }, 15276 }, 15277 { 15278 name: "MOVFD", 15279 argLen: 1, 15280 asm: mips.AMOVFD, 15281 reg: regInfo{ 15282 inputs: []inputInfo{ 15283 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15284 }, 15285 outputs: []outputInfo{ 15286 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15287 }, 15288 }, 15289 }, 15290 { 15291 name: "MOVDF", 15292 argLen: 1, 15293 asm: mips.AMOVDF, 15294 reg: regInfo{ 15295 inputs: []inputInfo{ 15296 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15297 }, 15298 outputs: []outputInfo{ 15299 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15300 }, 15301 }, 15302 }, 15303 { 15304 name: "CALLstatic", 15305 auxType: auxSymOff, 15306 argLen: 1, 15307 clobberFlags: true, 15308 call: true, 15309 reg: regInfo{ 15310 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15311 }, 15312 }, 15313 { 15314 name: "CALLclosure", 15315 auxType: auxInt64, 15316 argLen: 3, 15317 clobberFlags: true, 15318 call: true, 15319 reg: regInfo{ 15320 inputs: []inputInfo{ 15321 {1, 4194304}, // R22 15322 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15323 }, 15324 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15325 }, 15326 }, 15327 { 15328 name: "CALLdefer", 15329 auxType: auxInt64, 15330 argLen: 1, 15331 clobberFlags: true, 15332 call: true, 15333 reg: regInfo{ 15334 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15335 }, 15336 }, 15337 { 15338 name: "CALLgo", 15339 auxType: auxInt64, 15340 argLen: 1, 15341 clobberFlags: true, 15342 call: true, 15343 reg: regInfo{ 15344 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15345 }, 15346 }, 15347 { 15348 name: "CALLinter", 15349 auxType: auxInt64, 15350 argLen: 2, 15351 clobberFlags: true, 15352 call: true, 15353 reg: regInfo{ 15354 inputs: []inputInfo{ 15355 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15356 }, 15357 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15358 }, 15359 }, 15360 { 15361 name: "DUFFZERO", 15362 auxType: auxInt64, 15363 argLen: 2, 15364 faultOnNilArg0: true, 15365 reg: regInfo{ 15366 inputs: []inputInfo{ 15367 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15368 }, 15369 clobbers: 134217730, // R1 R31 15370 }, 15371 }, 15372 { 15373 name: "LoweredZero", 15374 auxType: auxInt64, 15375 argLen: 3, 15376 clobberFlags: true, 15377 faultOnNilArg0: true, 15378 reg: regInfo{ 15379 inputs: []inputInfo{ 15380 {0, 2}, // R1 15381 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15382 }, 15383 clobbers: 2, // R1 15384 }, 15385 }, 15386 { 15387 name: "LoweredMove", 15388 auxType: auxInt64, 15389 argLen: 4, 15390 clobberFlags: true, 15391 faultOnNilArg0: true, 15392 faultOnNilArg1: true, 15393 reg: regInfo{ 15394 inputs: []inputInfo{ 15395 {0, 4}, // R2 15396 {1, 2}, // R1 15397 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15398 }, 15399 clobbers: 6, // R1 R2 15400 }, 15401 }, 15402 { 15403 name: "LoweredNilCheck", 15404 argLen: 2, 15405 nilCheck: true, 15406 faultOnNilArg0: true, 15407 reg: regInfo{ 15408 inputs: []inputInfo{ 15409 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15410 }, 15411 }, 15412 }, 15413 { 15414 name: "FPFlagTrue", 15415 argLen: 1, 15416 reg: regInfo{ 15417 outputs: []outputInfo{ 15418 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15419 }, 15420 }, 15421 }, 15422 { 15423 name: "FPFlagFalse", 15424 argLen: 1, 15425 reg: regInfo{ 15426 outputs: []outputInfo{ 15427 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15428 }, 15429 }, 15430 }, 15431 { 15432 name: "LoweredGetClosurePtr", 15433 argLen: 0, 15434 reg: regInfo{ 15435 outputs: []outputInfo{ 15436 {0, 4194304}, // R22 15437 }, 15438 }, 15439 }, 15440 { 15441 name: "MOVVconvert", 15442 argLen: 2, 15443 asm: mips.AMOVV, 15444 reg: regInfo{ 15445 inputs: []inputInfo{ 15446 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15447 }, 15448 outputs: []outputInfo{ 15449 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15450 }, 15451 }, 15452 }, 15453 15454 { 15455 name: "ADD", 15456 argLen: 2, 15457 commutative: true, 15458 asm: ppc64.AADD, 15459 reg: regInfo{ 15460 inputs: []inputInfo{ 15461 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15462 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15463 }, 15464 outputs: []outputInfo{ 15465 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15466 }, 15467 }, 15468 }, 15469 { 15470 name: "ADDconst", 15471 auxType: auxSymOff, 15472 argLen: 1, 15473 asm: ppc64.AADD, 15474 reg: regInfo{ 15475 inputs: []inputInfo{ 15476 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15477 }, 15478 outputs: []outputInfo{ 15479 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15480 }, 15481 }, 15482 }, 15483 { 15484 name: "FADD", 15485 argLen: 2, 15486 commutative: true, 15487 asm: ppc64.AFADD, 15488 reg: regInfo{ 15489 inputs: []inputInfo{ 15490 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15491 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15492 }, 15493 outputs: []outputInfo{ 15494 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15495 }, 15496 }, 15497 }, 15498 { 15499 name: "FADDS", 15500 argLen: 2, 15501 commutative: true, 15502 asm: ppc64.AFADDS, 15503 reg: regInfo{ 15504 inputs: []inputInfo{ 15505 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15506 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15507 }, 15508 outputs: []outputInfo{ 15509 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15510 }, 15511 }, 15512 }, 15513 { 15514 name: "SUB", 15515 argLen: 2, 15516 asm: ppc64.ASUB, 15517 reg: regInfo{ 15518 inputs: []inputInfo{ 15519 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15520 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15521 }, 15522 outputs: []outputInfo{ 15523 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15524 }, 15525 }, 15526 }, 15527 { 15528 name: "FSUB", 15529 argLen: 2, 15530 asm: ppc64.AFSUB, 15531 reg: regInfo{ 15532 inputs: []inputInfo{ 15533 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15534 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15535 }, 15536 outputs: []outputInfo{ 15537 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15538 }, 15539 }, 15540 }, 15541 { 15542 name: "FSUBS", 15543 argLen: 2, 15544 asm: ppc64.AFSUBS, 15545 reg: regInfo{ 15546 inputs: []inputInfo{ 15547 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15548 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15549 }, 15550 outputs: []outputInfo{ 15551 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15552 }, 15553 }, 15554 }, 15555 { 15556 name: "MULLD", 15557 argLen: 2, 15558 commutative: true, 15559 asm: ppc64.AMULLD, 15560 reg: regInfo{ 15561 inputs: []inputInfo{ 15562 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15563 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15564 }, 15565 outputs: []outputInfo{ 15566 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15567 }, 15568 }, 15569 }, 15570 { 15571 name: "MULLW", 15572 argLen: 2, 15573 commutative: true, 15574 asm: ppc64.AMULLW, 15575 reg: regInfo{ 15576 inputs: []inputInfo{ 15577 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15578 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15579 }, 15580 outputs: []outputInfo{ 15581 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15582 }, 15583 }, 15584 }, 15585 { 15586 name: "MULHD", 15587 argLen: 2, 15588 commutative: true, 15589 asm: ppc64.AMULHD, 15590 reg: regInfo{ 15591 inputs: []inputInfo{ 15592 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15593 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15594 }, 15595 outputs: []outputInfo{ 15596 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15597 }, 15598 }, 15599 }, 15600 { 15601 name: "MULHW", 15602 argLen: 2, 15603 commutative: true, 15604 asm: ppc64.AMULHW, 15605 reg: regInfo{ 15606 inputs: []inputInfo{ 15607 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15608 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15609 }, 15610 outputs: []outputInfo{ 15611 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15612 }, 15613 }, 15614 }, 15615 { 15616 name: "MULHDU", 15617 argLen: 2, 15618 commutative: true, 15619 asm: ppc64.AMULHDU, 15620 reg: regInfo{ 15621 inputs: []inputInfo{ 15622 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15623 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15624 }, 15625 outputs: []outputInfo{ 15626 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15627 }, 15628 }, 15629 }, 15630 { 15631 name: "MULHWU", 15632 argLen: 2, 15633 commutative: true, 15634 asm: ppc64.AMULHWU, 15635 reg: regInfo{ 15636 inputs: []inputInfo{ 15637 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15638 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15639 }, 15640 outputs: []outputInfo{ 15641 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15642 }, 15643 }, 15644 }, 15645 { 15646 name: "FMUL", 15647 argLen: 2, 15648 commutative: true, 15649 asm: ppc64.AFMUL, 15650 reg: regInfo{ 15651 inputs: []inputInfo{ 15652 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15653 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15654 }, 15655 outputs: []outputInfo{ 15656 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15657 }, 15658 }, 15659 }, 15660 { 15661 name: "FMULS", 15662 argLen: 2, 15663 commutative: true, 15664 asm: ppc64.AFMULS, 15665 reg: regInfo{ 15666 inputs: []inputInfo{ 15667 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15668 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15669 }, 15670 outputs: []outputInfo{ 15671 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15672 }, 15673 }, 15674 }, 15675 { 15676 name: "SRAD", 15677 argLen: 2, 15678 asm: ppc64.ASRAD, 15679 reg: regInfo{ 15680 inputs: []inputInfo{ 15681 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15682 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15683 }, 15684 outputs: []outputInfo{ 15685 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15686 }, 15687 }, 15688 }, 15689 { 15690 name: "SRAW", 15691 argLen: 2, 15692 asm: ppc64.ASRAW, 15693 reg: regInfo{ 15694 inputs: []inputInfo{ 15695 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15696 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15697 }, 15698 outputs: []outputInfo{ 15699 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15700 }, 15701 }, 15702 }, 15703 { 15704 name: "SRD", 15705 argLen: 2, 15706 asm: ppc64.ASRD, 15707 reg: regInfo{ 15708 inputs: []inputInfo{ 15709 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15710 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15711 }, 15712 outputs: []outputInfo{ 15713 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15714 }, 15715 }, 15716 }, 15717 { 15718 name: "SRW", 15719 argLen: 2, 15720 asm: ppc64.ASRW, 15721 reg: regInfo{ 15722 inputs: []inputInfo{ 15723 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15724 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15725 }, 15726 outputs: []outputInfo{ 15727 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15728 }, 15729 }, 15730 }, 15731 { 15732 name: "SLD", 15733 argLen: 2, 15734 asm: ppc64.ASLD, 15735 reg: regInfo{ 15736 inputs: []inputInfo{ 15737 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15738 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15739 }, 15740 outputs: []outputInfo{ 15741 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15742 }, 15743 }, 15744 }, 15745 { 15746 name: "SLW", 15747 argLen: 2, 15748 asm: ppc64.ASLW, 15749 reg: regInfo{ 15750 inputs: []inputInfo{ 15751 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15752 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15753 }, 15754 outputs: []outputInfo{ 15755 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15756 }, 15757 }, 15758 }, 15759 { 15760 name: "ADDconstForCarry", 15761 auxType: auxInt16, 15762 argLen: 1, 15763 asm: ppc64.AADDC, 15764 reg: regInfo{ 15765 inputs: []inputInfo{ 15766 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15767 }, 15768 clobbers: 2147483648, // R31 15769 }, 15770 }, 15771 { 15772 name: "MaskIfNotCarry", 15773 argLen: 1, 15774 asm: ppc64.AADDME, 15775 reg: regInfo{ 15776 outputs: []outputInfo{ 15777 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15778 }, 15779 }, 15780 }, 15781 { 15782 name: "SRADconst", 15783 auxType: auxInt64, 15784 argLen: 1, 15785 asm: ppc64.ASRAD, 15786 reg: regInfo{ 15787 inputs: []inputInfo{ 15788 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15789 }, 15790 outputs: []outputInfo{ 15791 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15792 }, 15793 }, 15794 }, 15795 { 15796 name: "SRAWconst", 15797 auxType: auxInt64, 15798 argLen: 1, 15799 asm: ppc64.ASRAW, 15800 reg: regInfo{ 15801 inputs: []inputInfo{ 15802 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15803 }, 15804 outputs: []outputInfo{ 15805 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15806 }, 15807 }, 15808 }, 15809 { 15810 name: "SRDconst", 15811 auxType: auxInt64, 15812 argLen: 1, 15813 asm: ppc64.ASRD, 15814 reg: regInfo{ 15815 inputs: []inputInfo{ 15816 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15817 }, 15818 outputs: []outputInfo{ 15819 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15820 }, 15821 }, 15822 }, 15823 { 15824 name: "SRWconst", 15825 auxType: auxInt64, 15826 argLen: 1, 15827 asm: ppc64.ASRW, 15828 reg: regInfo{ 15829 inputs: []inputInfo{ 15830 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15831 }, 15832 outputs: []outputInfo{ 15833 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15834 }, 15835 }, 15836 }, 15837 { 15838 name: "SLDconst", 15839 auxType: auxInt64, 15840 argLen: 1, 15841 asm: ppc64.ASLD, 15842 reg: regInfo{ 15843 inputs: []inputInfo{ 15844 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15845 }, 15846 outputs: []outputInfo{ 15847 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15848 }, 15849 }, 15850 }, 15851 { 15852 name: "SLWconst", 15853 auxType: auxInt64, 15854 argLen: 1, 15855 asm: ppc64.ASLW, 15856 reg: regInfo{ 15857 inputs: []inputInfo{ 15858 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15859 }, 15860 outputs: []outputInfo{ 15861 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15862 }, 15863 }, 15864 }, 15865 { 15866 name: "FDIV", 15867 argLen: 2, 15868 asm: ppc64.AFDIV, 15869 reg: regInfo{ 15870 inputs: []inputInfo{ 15871 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15872 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15873 }, 15874 outputs: []outputInfo{ 15875 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15876 }, 15877 }, 15878 }, 15879 { 15880 name: "FDIVS", 15881 argLen: 2, 15882 asm: ppc64.AFDIVS, 15883 reg: regInfo{ 15884 inputs: []inputInfo{ 15885 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15886 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15887 }, 15888 outputs: []outputInfo{ 15889 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15890 }, 15891 }, 15892 }, 15893 { 15894 name: "DIVD", 15895 argLen: 2, 15896 asm: ppc64.ADIVD, 15897 reg: regInfo{ 15898 inputs: []inputInfo{ 15899 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15900 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15901 }, 15902 outputs: []outputInfo{ 15903 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15904 }, 15905 }, 15906 }, 15907 { 15908 name: "DIVW", 15909 argLen: 2, 15910 asm: ppc64.ADIVW, 15911 reg: regInfo{ 15912 inputs: []inputInfo{ 15913 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15914 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15915 }, 15916 outputs: []outputInfo{ 15917 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15918 }, 15919 }, 15920 }, 15921 { 15922 name: "DIVDU", 15923 argLen: 2, 15924 asm: ppc64.ADIVDU, 15925 reg: regInfo{ 15926 inputs: []inputInfo{ 15927 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15928 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15929 }, 15930 outputs: []outputInfo{ 15931 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15932 }, 15933 }, 15934 }, 15935 { 15936 name: "DIVWU", 15937 argLen: 2, 15938 asm: ppc64.ADIVWU, 15939 reg: regInfo{ 15940 inputs: []inputInfo{ 15941 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15942 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15943 }, 15944 outputs: []outputInfo{ 15945 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15946 }, 15947 }, 15948 }, 15949 { 15950 name: "FCTIDZ", 15951 argLen: 1, 15952 asm: ppc64.AFCTIDZ, 15953 reg: regInfo{ 15954 inputs: []inputInfo{ 15955 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15956 }, 15957 outputs: []outputInfo{ 15958 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15959 }, 15960 }, 15961 }, 15962 { 15963 name: "FCTIWZ", 15964 argLen: 1, 15965 asm: ppc64.AFCTIWZ, 15966 reg: regInfo{ 15967 inputs: []inputInfo{ 15968 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15969 }, 15970 outputs: []outputInfo{ 15971 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15972 }, 15973 }, 15974 }, 15975 { 15976 name: "FCFID", 15977 argLen: 1, 15978 asm: ppc64.AFCFID, 15979 reg: regInfo{ 15980 inputs: []inputInfo{ 15981 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15982 }, 15983 outputs: []outputInfo{ 15984 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15985 }, 15986 }, 15987 }, 15988 { 15989 name: "FRSP", 15990 argLen: 1, 15991 asm: ppc64.AFRSP, 15992 reg: regInfo{ 15993 inputs: []inputInfo{ 15994 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15995 }, 15996 outputs: []outputInfo{ 15997 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15998 }, 15999 }, 16000 }, 16001 { 16002 name: "Xf2i64", 16003 argLen: 1, 16004 usesScratch: true, 16005 reg: regInfo{ 16006 inputs: []inputInfo{ 16007 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16008 }, 16009 outputs: []outputInfo{ 16010 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16011 }, 16012 }, 16013 }, 16014 { 16015 name: "Xi2f64", 16016 argLen: 1, 16017 usesScratch: true, 16018 reg: regInfo{ 16019 inputs: []inputInfo{ 16020 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16021 }, 16022 outputs: []outputInfo{ 16023 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16024 }, 16025 }, 16026 }, 16027 { 16028 name: "AND", 16029 argLen: 2, 16030 commutative: true, 16031 asm: ppc64.AAND, 16032 reg: regInfo{ 16033 inputs: []inputInfo{ 16034 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16035 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16036 }, 16037 outputs: []outputInfo{ 16038 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16039 }, 16040 }, 16041 }, 16042 { 16043 name: "ANDN", 16044 argLen: 2, 16045 asm: ppc64.AANDN, 16046 reg: regInfo{ 16047 inputs: []inputInfo{ 16048 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16049 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16050 }, 16051 outputs: []outputInfo{ 16052 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16053 }, 16054 }, 16055 }, 16056 { 16057 name: "OR", 16058 argLen: 2, 16059 commutative: true, 16060 asm: ppc64.AOR, 16061 reg: regInfo{ 16062 inputs: []inputInfo{ 16063 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16064 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16065 }, 16066 outputs: []outputInfo{ 16067 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16068 }, 16069 }, 16070 }, 16071 { 16072 name: "ORN", 16073 argLen: 2, 16074 asm: ppc64.AORN, 16075 reg: regInfo{ 16076 inputs: []inputInfo{ 16077 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16078 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16079 }, 16080 outputs: []outputInfo{ 16081 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16082 }, 16083 }, 16084 }, 16085 { 16086 name: "XOR", 16087 argLen: 2, 16088 commutative: true, 16089 asm: ppc64.AXOR, 16090 reg: regInfo{ 16091 inputs: []inputInfo{ 16092 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16093 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16094 }, 16095 outputs: []outputInfo{ 16096 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16097 }, 16098 }, 16099 }, 16100 { 16101 name: "EQV", 16102 argLen: 2, 16103 commutative: true, 16104 asm: ppc64.AEQV, 16105 reg: regInfo{ 16106 inputs: []inputInfo{ 16107 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16108 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16109 }, 16110 outputs: []outputInfo{ 16111 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16112 }, 16113 }, 16114 }, 16115 { 16116 name: "NEG", 16117 argLen: 1, 16118 asm: ppc64.ANEG, 16119 reg: regInfo{ 16120 inputs: []inputInfo{ 16121 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16122 }, 16123 outputs: []outputInfo{ 16124 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16125 }, 16126 }, 16127 }, 16128 { 16129 name: "FNEG", 16130 argLen: 1, 16131 asm: ppc64.AFNEG, 16132 reg: regInfo{ 16133 inputs: []inputInfo{ 16134 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16135 }, 16136 outputs: []outputInfo{ 16137 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16138 }, 16139 }, 16140 }, 16141 { 16142 name: "FSQRT", 16143 argLen: 1, 16144 asm: ppc64.AFSQRT, 16145 reg: regInfo{ 16146 inputs: []inputInfo{ 16147 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16148 }, 16149 outputs: []outputInfo{ 16150 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16151 }, 16152 }, 16153 }, 16154 { 16155 name: "FSQRTS", 16156 argLen: 1, 16157 asm: ppc64.AFSQRTS, 16158 reg: regInfo{ 16159 inputs: []inputInfo{ 16160 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16161 }, 16162 outputs: []outputInfo{ 16163 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16164 }, 16165 }, 16166 }, 16167 { 16168 name: "ORconst", 16169 auxType: auxInt64, 16170 argLen: 1, 16171 asm: ppc64.AOR, 16172 reg: regInfo{ 16173 inputs: []inputInfo{ 16174 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16175 }, 16176 outputs: []outputInfo{ 16177 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16178 }, 16179 }, 16180 }, 16181 { 16182 name: "XORconst", 16183 auxType: auxInt64, 16184 argLen: 1, 16185 asm: ppc64.AXOR, 16186 reg: regInfo{ 16187 inputs: []inputInfo{ 16188 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16189 }, 16190 outputs: []outputInfo{ 16191 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16192 }, 16193 }, 16194 }, 16195 { 16196 name: "ANDconst", 16197 auxType: auxInt64, 16198 argLen: 1, 16199 clobberFlags: true, 16200 asm: ppc64.AANDCC, 16201 reg: regInfo{ 16202 inputs: []inputInfo{ 16203 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16204 }, 16205 outputs: []outputInfo{ 16206 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16207 }, 16208 }, 16209 }, 16210 { 16211 name: "ANDCCconst", 16212 auxType: auxInt64, 16213 argLen: 1, 16214 asm: ppc64.AANDCC, 16215 reg: regInfo{ 16216 inputs: []inputInfo{ 16217 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16218 }, 16219 }, 16220 }, 16221 { 16222 name: "MOVBreg", 16223 argLen: 1, 16224 asm: ppc64.AMOVB, 16225 reg: regInfo{ 16226 inputs: []inputInfo{ 16227 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16228 }, 16229 outputs: []outputInfo{ 16230 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16231 }, 16232 }, 16233 }, 16234 { 16235 name: "MOVBZreg", 16236 argLen: 1, 16237 asm: ppc64.AMOVBZ, 16238 reg: regInfo{ 16239 inputs: []inputInfo{ 16240 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16241 }, 16242 outputs: []outputInfo{ 16243 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16244 }, 16245 }, 16246 }, 16247 { 16248 name: "MOVHreg", 16249 argLen: 1, 16250 asm: ppc64.AMOVH, 16251 reg: regInfo{ 16252 inputs: []inputInfo{ 16253 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16254 }, 16255 outputs: []outputInfo{ 16256 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16257 }, 16258 }, 16259 }, 16260 { 16261 name: "MOVHZreg", 16262 argLen: 1, 16263 asm: ppc64.AMOVHZ, 16264 reg: regInfo{ 16265 inputs: []inputInfo{ 16266 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16267 }, 16268 outputs: []outputInfo{ 16269 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16270 }, 16271 }, 16272 }, 16273 { 16274 name: "MOVWreg", 16275 argLen: 1, 16276 asm: ppc64.AMOVW, 16277 reg: regInfo{ 16278 inputs: []inputInfo{ 16279 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16280 }, 16281 outputs: []outputInfo{ 16282 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16283 }, 16284 }, 16285 }, 16286 { 16287 name: "MOVWZreg", 16288 argLen: 1, 16289 asm: ppc64.AMOVWZ, 16290 reg: regInfo{ 16291 inputs: []inputInfo{ 16292 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16293 }, 16294 outputs: []outputInfo{ 16295 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16296 }, 16297 }, 16298 }, 16299 { 16300 name: "MOVBZload", 16301 auxType: auxSymOff, 16302 argLen: 2, 16303 faultOnNilArg0: true, 16304 asm: ppc64.AMOVBZ, 16305 reg: regInfo{ 16306 inputs: []inputInfo{ 16307 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16308 }, 16309 outputs: []outputInfo{ 16310 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16311 }, 16312 }, 16313 }, 16314 { 16315 name: "MOVHload", 16316 auxType: auxSymOff, 16317 argLen: 2, 16318 faultOnNilArg0: true, 16319 asm: ppc64.AMOVH, 16320 reg: regInfo{ 16321 inputs: []inputInfo{ 16322 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16323 }, 16324 outputs: []outputInfo{ 16325 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16326 }, 16327 }, 16328 }, 16329 { 16330 name: "MOVHZload", 16331 auxType: auxSymOff, 16332 argLen: 2, 16333 faultOnNilArg0: true, 16334 asm: ppc64.AMOVHZ, 16335 reg: regInfo{ 16336 inputs: []inputInfo{ 16337 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16338 }, 16339 outputs: []outputInfo{ 16340 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16341 }, 16342 }, 16343 }, 16344 { 16345 name: "MOVWload", 16346 auxType: auxSymOff, 16347 argLen: 2, 16348 faultOnNilArg0: true, 16349 asm: ppc64.AMOVW, 16350 reg: regInfo{ 16351 inputs: []inputInfo{ 16352 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16353 }, 16354 outputs: []outputInfo{ 16355 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16356 }, 16357 }, 16358 }, 16359 { 16360 name: "MOVWZload", 16361 auxType: auxSymOff, 16362 argLen: 2, 16363 faultOnNilArg0: true, 16364 asm: ppc64.AMOVWZ, 16365 reg: regInfo{ 16366 inputs: []inputInfo{ 16367 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16368 }, 16369 outputs: []outputInfo{ 16370 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16371 }, 16372 }, 16373 }, 16374 { 16375 name: "MOVDload", 16376 auxType: auxSymOff, 16377 argLen: 2, 16378 faultOnNilArg0: true, 16379 asm: ppc64.AMOVD, 16380 reg: regInfo{ 16381 inputs: []inputInfo{ 16382 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16383 }, 16384 outputs: []outputInfo{ 16385 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16386 }, 16387 }, 16388 }, 16389 { 16390 name: "FMOVDload", 16391 auxType: auxSymOff, 16392 argLen: 2, 16393 faultOnNilArg0: true, 16394 asm: ppc64.AFMOVD, 16395 reg: regInfo{ 16396 inputs: []inputInfo{ 16397 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16398 }, 16399 outputs: []outputInfo{ 16400 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16401 }, 16402 }, 16403 }, 16404 { 16405 name: "FMOVSload", 16406 auxType: auxSymOff, 16407 argLen: 2, 16408 faultOnNilArg0: true, 16409 asm: ppc64.AFMOVS, 16410 reg: regInfo{ 16411 inputs: []inputInfo{ 16412 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16413 }, 16414 outputs: []outputInfo{ 16415 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16416 }, 16417 }, 16418 }, 16419 { 16420 name: "MOVBstore", 16421 auxType: auxSymOff, 16422 argLen: 3, 16423 faultOnNilArg0: true, 16424 asm: ppc64.AMOVB, 16425 reg: regInfo{ 16426 inputs: []inputInfo{ 16427 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16428 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16429 }, 16430 }, 16431 }, 16432 { 16433 name: "MOVHstore", 16434 auxType: auxSymOff, 16435 argLen: 3, 16436 faultOnNilArg0: true, 16437 asm: ppc64.AMOVH, 16438 reg: regInfo{ 16439 inputs: []inputInfo{ 16440 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16441 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16442 }, 16443 }, 16444 }, 16445 { 16446 name: "MOVWstore", 16447 auxType: auxSymOff, 16448 argLen: 3, 16449 faultOnNilArg0: true, 16450 asm: ppc64.AMOVW, 16451 reg: regInfo{ 16452 inputs: []inputInfo{ 16453 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16454 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16455 }, 16456 }, 16457 }, 16458 { 16459 name: "MOVDstore", 16460 auxType: auxSymOff, 16461 argLen: 3, 16462 faultOnNilArg0: true, 16463 asm: ppc64.AMOVD, 16464 reg: regInfo{ 16465 inputs: []inputInfo{ 16466 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16467 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16468 }, 16469 }, 16470 }, 16471 { 16472 name: "FMOVDstore", 16473 auxType: auxSymOff, 16474 argLen: 3, 16475 faultOnNilArg0: true, 16476 asm: ppc64.AFMOVD, 16477 reg: regInfo{ 16478 inputs: []inputInfo{ 16479 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16480 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16481 }, 16482 }, 16483 }, 16484 { 16485 name: "FMOVSstore", 16486 auxType: auxSymOff, 16487 argLen: 3, 16488 faultOnNilArg0: true, 16489 asm: ppc64.AFMOVS, 16490 reg: regInfo{ 16491 inputs: []inputInfo{ 16492 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16493 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16494 }, 16495 }, 16496 }, 16497 { 16498 name: "MOVBstorezero", 16499 auxType: auxSymOff, 16500 argLen: 2, 16501 faultOnNilArg0: true, 16502 asm: ppc64.AMOVB, 16503 reg: regInfo{ 16504 inputs: []inputInfo{ 16505 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16506 }, 16507 }, 16508 }, 16509 { 16510 name: "MOVHstorezero", 16511 auxType: auxSymOff, 16512 argLen: 2, 16513 faultOnNilArg0: true, 16514 asm: ppc64.AMOVH, 16515 reg: regInfo{ 16516 inputs: []inputInfo{ 16517 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16518 }, 16519 }, 16520 }, 16521 { 16522 name: "MOVWstorezero", 16523 auxType: auxSymOff, 16524 argLen: 2, 16525 faultOnNilArg0: true, 16526 asm: ppc64.AMOVW, 16527 reg: regInfo{ 16528 inputs: []inputInfo{ 16529 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16530 }, 16531 }, 16532 }, 16533 { 16534 name: "MOVDstorezero", 16535 auxType: auxSymOff, 16536 argLen: 2, 16537 faultOnNilArg0: true, 16538 asm: ppc64.AMOVD, 16539 reg: regInfo{ 16540 inputs: []inputInfo{ 16541 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16542 }, 16543 }, 16544 }, 16545 { 16546 name: "MOVDaddr", 16547 auxType: auxSymOff, 16548 argLen: 1, 16549 rematerializeable: true, 16550 asm: ppc64.AMOVD, 16551 reg: regInfo{ 16552 inputs: []inputInfo{ 16553 {0, 6}, // SP SB 16554 }, 16555 outputs: []outputInfo{ 16556 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16557 }, 16558 }, 16559 }, 16560 { 16561 name: "MOVDconst", 16562 auxType: auxInt64, 16563 argLen: 0, 16564 rematerializeable: true, 16565 asm: ppc64.AMOVD, 16566 reg: regInfo{ 16567 outputs: []outputInfo{ 16568 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16569 }, 16570 }, 16571 }, 16572 { 16573 name: "FMOVDconst", 16574 auxType: auxFloat64, 16575 argLen: 0, 16576 rematerializeable: true, 16577 asm: ppc64.AFMOVD, 16578 reg: regInfo{ 16579 outputs: []outputInfo{ 16580 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16581 }, 16582 }, 16583 }, 16584 { 16585 name: "FMOVSconst", 16586 auxType: auxFloat32, 16587 argLen: 0, 16588 rematerializeable: true, 16589 asm: ppc64.AFMOVS, 16590 reg: regInfo{ 16591 outputs: []outputInfo{ 16592 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16593 }, 16594 }, 16595 }, 16596 { 16597 name: "FCMPU", 16598 argLen: 2, 16599 asm: ppc64.AFCMPU, 16600 reg: regInfo{ 16601 inputs: []inputInfo{ 16602 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16603 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16604 }, 16605 }, 16606 }, 16607 { 16608 name: "CMP", 16609 argLen: 2, 16610 asm: ppc64.ACMP, 16611 reg: regInfo{ 16612 inputs: []inputInfo{ 16613 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16614 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16615 }, 16616 }, 16617 }, 16618 { 16619 name: "CMPU", 16620 argLen: 2, 16621 asm: ppc64.ACMPU, 16622 reg: regInfo{ 16623 inputs: []inputInfo{ 16624 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16625 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16626 }, 16627 }, 16628 }, 16629 { 16630 name: "CMPW", 16631 argLen: 2, 16632 asm: ppc64.ACMPW, 16633 reg: regInfo{ 16634 inputs: []inputInfo{ 16635 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16636 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16637 }, 16638 }, 16639 }, 16640 { 16641 name: "CMPWU", 16642 argLen: 2, 16643 asm: ppc64.ACMPWU, 16644 reg: regInfo{ 16645 inputs: []inputInfo{ 16646 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16647 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16648 }, 16649 }, 16650 }, 16651 { 16652 name: "CMPconst", 16653 auxType: auxInt64, 16654 argLen: 1, 16655 asm: ppc64.ACMP, 16656 reg: regInfo{ 16657 inputs: []inputInfo{ 16658 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16659 }, 16660 }, 16661 }, 16662 { 16663 name: "CMPUconst", 16664 auxType: auxInt64, 16665 argLen: 1, 16666 asm: ppc64.ACMPU, 16667 reg: regInfo{ 16668 inputs: []inputInfo{ 16669 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16670 }, 16671 }, 16672 }, 16673 { 16674 name: "CMPWconst", 16675 auxType: auxInt32, 16676 argLen: 1, 16677 asm: ppc64.ACMPW, 16678 reg: regInfo{ 16679 inputs: []inputInfo{ 16680 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16681 }, 16682 }, 16683 }, 16684 { 16685 name: "CMPWUconst", 16686 auxType: auxInt32, 16687 argLen: 1, 16688 asm: ppc64.ACMPWU, 16689 reg: regInfo{ 16690 inputs: []inputInfo{ 16691 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16692 }, 16693 }, 16694 }, 16695 { 16696 name: "Equal", 16697 argLen: 1, 16698 reg: regInfo{ 16699 outputs: []outputInfo{ 16700 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16701 }, 16702 }, 16703 }, 16704 { 16705 name: "NotEqual", 16706 argLen: 1, 16707 reg: regInfo{ 16708 outputs: []outputInfo{ 16709 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16710 }, 16711 }, 16712 }, 16713 { 16714 name: "LessThan", 16715 argLen: 1, 16716 reg: regInfo{ 16717 outputs: []outputInfo{ 16718 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16719 }, 16720 }, 16721 }, 16722 { 16723 name: "FLessThan", 16724 argLen: 1, 16725 reg: regInfo{ 16726 outputs: []outputInfo{ 16727 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16728 }, 16729 }, 16730 }, 16731 { 16732 name: "LessEqual", 16733 argLen: 1, 16734 reg: regInfo{ 16735 outputs: []outputInfo{ 16736 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16737 }, 16738 }, 16739 }, 16740 { 16741 name: "FLessEqual", 16742 argLen: 1, 16743 reg: regInfo{ 16744 outputs: []outputInfo{ 16745 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16746 }, 16747 }, 16748 }, 16749 { 16750 name: "GreaterThan", 16751 argLen: 1, 16752 reg: regInfo{ 16753 outputs: []outputInfo{ 16754 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16755 }, 16756 }, 16757 }, 16758 { 16759 name: "FGreaterThan", 16760 argLen: 1, 16761 reg: regInfo{ 16762 outputs: []outputInfo{ 16763 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16764 }, 16765 }, 16766 }, 16767 { 16768 name: "GreaterEqual", 16769 argLen: 1, 16770 reg: regInfo{ 16771 outputs: []outputInfo{ 16772 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16773 }, 16774 }, 16775 }, 16776 { 16777 name: "FGreaterEqual", 16778 argLen: 1, 16779 reg: regInfo{ 16780 outputs: []outputInfo{ 16781 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16782 }, 16783 }, 16784 }, 16785 { 16786 name: "LoweredGetClosurePtr", 16787 argLen: 0, 16788 reg: regInfo{ 16789 outputs: []outputInfo{ 16790 {0, 2048}, // R11 16791 }, 16792 }, 16793 }, 16794 { 16795 name: "LoweredNilCheck", 16796 argLen: 2, 16797 clobberFlags: true, 16798 nilCheck: true, 16799 faultOnNilArg0: true, 16800 reg: regInfo{ 16801 inputs: []inputInfo{ 16802 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16803 }, 16804 clobbers: 2147483648, // R31 16805 }, 16806 }, 16807 { 16808 name: "MOVDconvert", 16809 argLen: 2, 16810 asm: ppc64.AMOVD, 16811 reg: regInfo{ 16812 inputs: []inputInfo{ 16813 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16814 }, 16815 outputs: []outputInfo{ 16816 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16817 }, 16818 }, 16819 }, 16820 { 16821 name: "CALLstatic", 16822 auxType: auxSymOff, 16823 argLen: 1, 16824 clobberFlags: true, 16825 call: true, 16826 reg: regInfo{ 16827 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16828 }, 16829 }, 16830 { 16831 name: "CALLclosure", 16832 auxType: auxInt64, 16833 argLen: 3, 16834 clobberFlags: true, 16835 call: true, 16836 reg: regInfo{ 16837 inputs: []inputInfo{ 16838 {1, 2048}, // R11 16839 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16840 }, 16841 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16842 }, 16843 }, 16844 { 16845 name: "CALLdefer", 16846 auxType: auxInt64, 16847 argLen: 1, 16848 clobberFlags: true, 16849 call: true, 16850 reg: regInfo{ 16851 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16852 }, 16853 }, 16854 { 16855 name: "CALLgo", 16856 auxType: auxInt64, 16857 argLen: 1, 16858 clobberFlags: true, 16859 call: true, 16860 reg: regInfo{ 16861 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16862 }, 16863 }, 16864 { 16865 name: "CALLinter", 16866 auxType: auxInt64, 16867 argLen: 2, 16868 clobberFlags: true, 16869 call: true, 16870 reg: regInfo{ 16871 inputs: []inputInfo{ 16872 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16873 }, 16874 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16875 }, 16876 }, 16877 { 16878 name: "LoweredZero", 16879 auxType: auxInt64, 16880 argLen: 3, 16881 clobberFlags: true, 16882 faultOnNilArg0: true, 16883 reg: regInfo{ 16884 inputs: []inputInfo{ 16885 {0, 8}, // R3 16886 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16887 }, 16888 clobbers: 8, // R3 16889 }, 16890 }, 16891 { 16892 name: "LoweredMove", 16893 auxType: auxInt64, 16894 argLen: 4, 16895 clobberFlags: true, 16896 faultOnNilArg0: true, 16897 faultOnNilArg1: true, 16898 reg: regInfo{ 16899 inputs: []inputInfo{ 16900 {0, 8}, // R3 16901 {1, 16}, // R4 16902 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16903 }, 16904 clobbers: 24, // R3 R4 16905 }, 16906 }, 16907 { 16908 name: "InvertFlags", 16909 argLen: 1, 16910 reg: regInfo{}, 16911 }, 16912 { 16913 name: "FlagEQ", 16914 argLen: 0, 16915 reg: regInfo{}, 16916 }, 16917 { 16918 name: "FlagLT", 16919 argLen: 0, 16920 reg: regInfo{}, 16921 }, 16922 { 16923 name: "FlagGT", 16924 argLen: 0, 16925 reg: regInfo{}, 16926 }, 16927 16928 { 16929 name: "FADDS", 16930 argLen: 2, 16931 commutative: true, 16932 resultInArg0: true, 16933 clobberFlags: true, 16934 asm: s390x.AFADDS, 16935 reg: regInfo{ 16936 inputs: []inputInfo{ 16937 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16938 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16939 }, 16940 outputs: []outputInfo{ 16941 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16942 }, 16943 }, 16944 }, 16945 { 16946 name: "FADD", 16947 argLen: 2, 16948 commutative: true, 16949 resultInArg0: true, 16950 clobberFlags: true, 16951 asm: s390x.AFADD, 16952 reg: regInfo{ 16953 inputs: []inputInfo{ 16954 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16955 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16956 }, 16957 outputs: []outputInfo{ 16958 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16959 }, 16960 }, 16961 }, 16962 { 16963 name: "FSUBS", 16964 argLen: 2, 16965 resultInArg0: true, 16966 clobberFlags: true, 16967 asm: s390x.AFSUBS, 16968 reg: regInfo{ 16969 inputs: []inputInfo{ 16970 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16971 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16972 }, 16973 outputs: []outputInfo{ 16974 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16975 }, 16976 }, 16977 }, 16978 { 16979 name: "FSUB", 16980 argLen: 2, 16981 resultInArg0: true, 16982 clobberFlags: true, 16983 asm: s390x.AFSUB, 16984 reg: regInfo{ 16985 inputs: []inputInfo{ 16986 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16987 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16988 }, 16989 outputs: []outputInfo{ 16990 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16991 }, 16992 }, 16993 }, 16994 { 16995 name: "FMULS", 16996 argLen: 2, 16997 commutative: true, 16998 resultInArg0: true, 16999 asm: s390x.AFMULS, 17000 reg: regInfo{ 17001 inputs: []inputInfo{ 17002 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17003 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17004 }, 17005 outputs: []outputInfo{ 17006 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17007 }, 17008 }, 17009 }, 17010 { 17011 name: "FMUL", 17012 argLen: 2, 17013 commutative: true, 17014 resultInArg0: true, 17015 asm: s390x.AFMUL, 17016 reg: regInfo{ 17017 inputs: []inputInfo{ 17018 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17019 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17020 }, 17021 outputs: []outputInfo{ 17022 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17023 }, 17024 }, 17025 }, 17026 { 17027 name: "FDIVS", 17028 argLen: 2, 17029 resultInArg0: true, 17030 asm: s390x.AFDIVS, 17031 reg: regInfo{ 17032 inputs: []inputInfo{ 17033 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17034 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17035 }, 17036 outputs: []outputInfo{ 17037 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17038 }, 17039 }, 17040 }, 17041 { 17042 name: "FDIV", 17043 argLen: 2, 17044 resultInArg0: true, 17045 asm: s390x.AFDIV, 17046 reg: regInfo{ 17047 inputs: []inputInfo{ 17048 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17049 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17050 }, 17051 outputs: []outputInfo{ 17052 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17053 }, 17054 }, 17055 }, 17056 { 17057 name: "FNEGS", 17058 argLen: 1, 17059 clobberFlags: true, 17060 asm: s390x.AFNEGS, 17061 reg: regInfo{ 17062 inputs: []inputInfo{ 17063 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17064 }, 17065 outputs: []outputInfo{ 17066 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17067 }, 17068 }, 17069 }, 17070 { 17071 name: "FNEG", 17072 argLen: 1, 17073 clobberFlags: true, 17074 asm: s390x.AFNEG, 17075 reg: regInfo{ 17076 inputs: []inputInfo{ 17077 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17078 }, 17079 outputs: []outputInfo{ 17080 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17081 }, 17082 }, 17083 }, 17084 { 17085 name: "FMOVSload", 17086 auxType: auxSymOff, 17087 argLen: 2, 17088 faultOnNilArg0: true, 17089 asm: s390x.AFMOVS, 17090 reg: regInfo{ 17091 inputs: []inputInfo{ 17092 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17093 }, 17094 outputs: []outputInfo{ 17095 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17096 }, 17097 }, 17098 }, 17099 { 17100 name: "FMOVDload", 17101 auxType: auxSymOff, 17102 argLen: 2, 17103 faultOnNilArg0: true, 17104 asm: s390x.AFMOVD, 17105 reg: regInfo{ 17106 inputs: []inputInfo{ 17107 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17108 }, 17109 outputs: []outputInfo{ 17110 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17111 }, 17112 }, 17113 }, 17114 { 17115 name: "FMOVSconst", 17116 auxType: auxFloat32, 17117 argLen: 0, 17118 rematerializeable: true, 17119 asm: s390x.AFMOVS, 17120 reg: regInfo{ 17121 outputs: []outputInfo{ 17122 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17123 }, 17124 }, 17125 }, 17126 { 17127 name: "FMOVDconst", 17128 auxType: auxFloat64, 17129 argLen: 0, 17130 rematerializeable: true, 17131 asm: s390x.AFMOVD, 17132 reg: regInfo{ 17133 outputs: []outputInfo{ 17134 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17135 }, 17136 }, 17137 }, 17138 { 17139 name: "FMOVSloadidx", 17140 auxType: auxSymOff, 17141 argLen: 3, 17142 asm: s390x.AFMOVS, 17143 reg: regInfo{ 17144 inputs: []inputInfo{ 17145 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17146 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17147 }, 17148 outputs: []outputInfo{ 17149 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17150 }, 17151 }, 17152 }, 17153 { 17154 name: "FMOVDloadidx", 17155 auxType: auxSymOff, 17156 argLen: 3, 17157 asm: s390x.AFMOVD, 17158 reg: regInfo{ 17159 inputs: []inputInfo{ 17160 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17161 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17162 }, 17163 outputs: []outputInfo{ 17164 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17165 }, 17166 }, 17167 }, 17168 { 17169 name: "FMOVSstore", 17170 auxType: auxSymOff, 17171 argLen: 3, 17172 faultOnNilArg0: true, 17173 asm: s390x.AFMOVS, 17174 reg: regInfo{ 17175 inputs: []inputInfo{ 17176 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17177 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17178 }, 17179 }, 17180 }, 17181 { 17182 name: "FMOVDstore", 17183 auxType: auxSymOff, 17184 argLen: 3, 17185 faultOnNilArg0: true, 17186 asm: s390x.AFMOVD, 17187 reg: regInfo{ 17188 inputs: []inputInfo{ 17189 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17190 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17191 }, 17192 }, 17193 }, 17194 { 17195 name: "FMOVSstoreidx", 17196 auxType: auxSymOff, 17197 argLen: 4, 17198 asm: s390x.AFMOVS, 17199 reg: regInfo{ 17200 inputs: []inputInfo{ 17201 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17202 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17203 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17204 }, 17205 }, 17206 }, 17207 { 17208 name: "FMOVDstoreidx", 17209 auxType: auxSymOff, 17210 argLen: 4, 17211 asm: s390x.AFMOVD, 17212 reg: regInfo{ 17213 inputs: []inputInfo{ 17214 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17215 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17216 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17217 }, 17218 }, 17219 }, 17220 { 17221 name: "ADD", 17222 argLen: 2, 17223 commutative: true, 17224 clobberFlags: true, 17225 asm: s390x.AADD, 17226 reg: regInfo{ 17227 inputs: []inputInfo{ 17228 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17229 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17230 }, 17231 outputs: []outputInfo{ 17232 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17233 }, 17234 }, 17235 }, 17236 { 17237 name: "ADDW", 17238 argLen: 2, 17239 commutative: true, 17240 clobberFlags: true, 17241 asm: s390x.AADDW, 17242 reg: regInfo{ 17243 inputs: []inputInfo{ 17244 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17245 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17246 }, 17247 outputs: []outputInfo{ 17248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17249 }, 17250 }, 17251 }, 17252 { 17253 name: "ADDconst", 17254 auxType: auxInt64, 17255 argLen: 1, 17256 clobberFlags: true, 17257 asm: s390x.AADD, 17258 reg: regInfo{ 17259 inputs: []inputInfo{ 17260 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17261 }, 17262 outputs: []outputInfo{ 17263 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17264 }, 17265 }, 17266 }, 17267 { 17268 name: "ADDWconst", 17269 auxType: auxInt32, 17270 argLen: 1, 17271 clobberFlags: true, 17272 asm: s390x.AADDW, 17273 reg: regInfo{ 17274 inputs: []inputInfo{ 17275 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17276 }, 17277 outputs: []outputInfo{ 17278 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17279 }, 17280 }, 17281 }, 17282 { 17283 name: "ADDload", 17284 auxType: auxSymOff, 17285 argLen: 3, 17286 resultInArg0: true, 17287 clobberFlags: true, 17288 faultOnNilArg1: true, 17289 asm: s390x.AADD, 17290 reg: regInfo{ 17291 inputs: []inputInfo{ 17292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17293 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17294 }, 17295 outputs: []outputInfo{ 17296 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17297 }, 17298 }, 17299 }, 17300 { 17301 name: "ADDWload", 17302 auxType: auxSymOff, 17303 argLen: 3, 17304 resultInArg0: true, 17305 clobberFlags: true, 17306 faultOnNilArg1: true, 17307 asm: s390x.AADDW, 17308 reg: regInfo{ 17309 inputs: []inputInfo{ 17310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17311 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17312 }, 17313 outputs: []outputInfo{ 17314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17315 }, 17316 }, 17317 }, 17318 { 17319 name: "SUB", 17320 argLen: 2, 17321 clobberFlags: true, 17322 asm: s390x.ASUB, 17323 reg: regInfo{ 17324 inputs: []inputInfo{ 17325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17326 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17327 }, 17328 outputs: []outputInfo{ 17329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17330 }, 17331 }, 17332 }, 17333 { 17334 name: "SUBW", 17335 argLen: 2, 17336 clobberFlags: true, 17337 asm: s390x.ASUBW, 17338 reg: regInfo{ 17339 inputs: []inputInfo{ 17340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17341 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17342 }, 17343 outputs: []outputInfo{ 17344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17345 }, 17346 }, 17347 }, 17348 { 17349 name: "SUBconst", 17350 auxType: auxInt64, 17351 argLen: 1, 17352 resultInArg0: true, 17353 clobberFlags: true, 17354 asm: s390x.ASUB, 17355 reg: regInfo{ 17356 inputs: []inputInfo{ 17357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17358 }, 17359 outputs: []outputInfo{ 17360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17361 }, 17362 }, 17363 }, 17364 { 17365 name: "SUBWconst", 17366 auxType: auxInt32, 17367 argLen: 1, 17368 resultInArg0: true, 17369 clobberFlags: true, 17370 asm: s390x.ASUBW, 17371 reg: regInfo{ 17372 inputs: []inputInfo{ 17373 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17374 }, 17375 outputs: []outputInfo{ 17376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17377 }, 17378 }, 17379 }, 17380 { 17381 name: "SUBload", 17382 auxType: auxSymOff, 17383 argLen: 3, 17384 resultInArg0: true, 17385 clobberFlags: true, 17386 faultOnNilArg1: true, 17387 asm: s390x.ASUB, 17388 reg: regInfo{ 17389 inputs: []inputInfo{ 17390 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17391 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17392 }, 17393 outputs: []outputInfo{ 17394 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17395 }, 17396 }, 17397 }, 17398 { 17399 name: "SUBWload", 17400 auxType: auxSymOff, 17401 argLen: 3, 17402 resultInArg0: true, 17403 clobberFlags: true, 17404 faultOnNilArg1: true, 17405 asm: s390x.ASUBW, 17406 reg: regInfo{ 17407 inputs: []inputInfo{ 17408 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17409 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17410 }, 17411 outputs: []outputInfo{ 17412 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17413 }, 17414 }, 17415 }, 17416 { 17417 name: "MULLD", 17418 argLen: 2, 17419 commutative: true, 17420 resultInArg0: true, 17421 clobberFlags: true, 17422 asm: s390x.AMULLD, 17423 reg: regInfo{ 17424 inputs: []inputInfo{ 17425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17426 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17427 }, 17428 outputs: []outputInfo{ 17429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17430 }, 17431 }, 17432 }, 17433 { 17434 name: "MULLW", 17435 argLen: 2, 17436 commutative: true, 17437 resultInArg0: true, 17438 clobberFlags: true, 17439 asm: s390x.AMULLW, 17440 reg: regInfo{ 17441 inputs: []inputInfo{ 17442 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17443 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17444 }, 17445 outputs: []outputInfo{ 17446 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17447 }, 17448 }, 17449 }, 17450 { 17451 name: "MULLDconst", 17452 auxType: auxInt64, 17453 argLen: 1, 17454 resultInArg0: true, 17455 clobberFlags: true, 17456 asm: s390x.AMULLD, 17457 reg: regInfo{ 17458 inputs: []inputInfo{ 17459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17460 }, 17461 outputs: []outputInfo{ 17462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17463 }, 17464 }, 17465 }, 17466 { 17467 name: "MULLWconst", 17468 auxType: auxInt32, 17469 argLen: 1, 17470 resultInArg0: true, 17471 clobberFlags: true, 17472 asm: s390x.AMULLW, 17473 reg: regInfo{ 17474 inputs: []inputInfo{ 17475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17476 }, 17477 outputs: []outputInfo{ 17478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17479 }, 17480 }, 17481 }, 17482 { 17483 name: "MULLDload", 17484 auxType: auxSymOff, 17485 argLen: 3, 17486 resultInArg0: true, 17487 clobberFlags: true, 17488 faultOnNilArg1: true, 17489 asm: s390x.AMULLD, 17490 reg: regInfo{ 17491 inputs: []inputInfo{ 17492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17493 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17494 }, 17495 outputs: []outputInfo{ 17496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17497 }, 17498 }, 17499 }, 17500 { 17501 name: "MULLWload", 17502 auxType: auxSymOff, 17503 argLen: 3, 17504 resultInArg0: true, 17505 clobberFlags: true, 17506 faultOnNilArg1: true, 17507 asm: s390x.AMULLW, 17508 reg: regInfo{ 17509 inputs: []inputInfo{ 17510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17511 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17512 }, 17513 outputs: []outputInfo{ 17514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17515 }, 17516 }, 17517 }, 17518 { 17519 name: "MULHD", 17520 argLen: 2, 17521 resultInArg0: true, 17522 clobberFlags: true, 17523 asm: s390x.AMULHD, 17524 reg: regInfo{ 17525 inputs: []inputInfo{ 17526 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17527 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17528 }, 17529 outputs: []outputInfo{ 17530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17531 }, 17532 }, 17533 }, 17534 { 17535 name: "MULHDU", 17536 argLen: 2, 17537 resultInArg0: true, 17538 clobberFlags: true, 17539 asm: s390x.AMULHDU, 17540 reg: regInfo{ 17541 inputs: []inputInfo{ 17542 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17543 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17544 }, 17545 outputs: []outputInfo{ 17546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17547 }, 17548 }, 17549 }, 17550 { 17551 name: "DIVD", 17552 argLen: 2, 17553 resultInArg0: true, 17554 clobberFlags: true, 17555 asm: s390x.ADIVD, 17556 reg: regInfo{ 17557 inputs: []inputInfo{ 17558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17559 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17560 }, 17561 outputs: []outputInfo{ 17562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17563 }, 17564 }, 17565 }, 17566 { 17567 name: "DIVW", 17568 argLen: 2, 17569 resultInArg0: true, 17570 clobberFlags: true, 17571 asm: s390x.ADIVW, 17572 reg: regInfo{ 17573 inputs: []inputInfo{ 17574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17575 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17576 }, 17577 outputs: []outputInfo{ 17578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17579 }, 17580 }, 17581 }, 17582 { 17583 name: "DIVDU", 17584 argLen: 2, 17585 resultInArg0: true, 17586 clobberFlags: true, 17587 asm: s390x.ADIVDU, 17588 reg: regInfo{ 17589 inputs: []inputInfo{ 17590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17591 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17592 }, 17593 outputs: []outputInfo{ 17594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17595 }, 17596 }, 17597 }, 17598 { 17599 name: "DIVWU", 17600 argLen: 2, 17601 resultInArg0: true, 17602 clobberFlags: true, 17603 asm: s390x.ADIVWU, 17604 reg: regInfo{ 17605 inputs: []inputInfo{ 17606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17607 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17608 }, 17609 outputs: []outputInfo{ 17610 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17611 }, 17612 }, 17613 }, 17614 { 17615 name: "MODD", 17616 argLen: 2, 17617 resultInArg0: true, 17618 clobberFlags: true, 17619 asm: s390x.AMODD, 17620 reg: regInfo{ 17621 inputs: []inputInfo{ 17622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17623 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17624 }, 17625 outputs: []outputInfo{ 17626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17627 }, 17628 }, 17629 }, 17630 { 17631 name: "MODW", 17632 argLen: 2, 17633 resultInArg0: true, 17634 clobberFlags: true, 17635 asm: s390x.AMODW, 17636 reg: regInfo{ 17637 inputs: []inputInfo{ 17638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17639 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17640 }, 17641 outputs: []outputInfo{ 17642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17643 }, 17644 }, 17645 }, 17646 { 17647 name: "MODDU", 17648 argLen: 2, 17649 resultInArg0: true, 17650 clobberFlags: true, 17651 asm: s390x.AMODDU, 17652 reg: regInfo{ 17653 inputs: []inputInfo{ 17654 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17655 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17656 }, 17657 outputs: []outputInfo{ 17658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17659 }, 17660 }, 17661 }, 17662 { 17663 name: "MODWU", 17664 argLen: 2, 17665 resultInArg0: true, 17666 clobberFlags: true, 17667 asm: s390x.AMODWU, 17668 reg: regInfo{ 17669 inputs: []inputInfo{ 17670 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17671 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17672 }, 17673 outputs: []outputInfo{ 17674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17675 }, 17676 }, 17677 }, 17678 { 17679 name: "AND", 17680 argLen: 2, 17681 commutative: true, 17682 clobberFlags: true, 17683 asm: s390x.AAND, 17684 reg: regInfo{ 17685 inputs: []inputInfo{ 17686 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17687 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17688 }, 17689 outputs: []outputInfo{ 17690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17691 }, 17692 }, 17693 }, 17694 { 17695 name: "ANDW", 17696 argLen: 2, 17697 commutative: true, 17698 clobberFlags: true, 17699 asm: s390x.AANDW, 17700 reg: regInfo{ 17701 inputs: []inputInfo{ 17702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17703 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17704 }, 17705 outputs: []outputInfo{ 17706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17707 }, 17708 }, 17709 }, 17710 { 17711 name: "ANDconst", 17712 auxType: auxInt64, 17713 argLen: 1, 17714 resultInArg0: true, 17715 clobberFlags: true, 17716 asm: s390x.AAND, 17717 reg: regInfo{ 17718 inputs: []inputInfo{ 17719 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17720 }, 17721 outputs: []outputInfo{ 17722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17723 }, 17724 }, 17725 }, 17726 { 17727 name: "ANDWconst", 17728 auxType: auxInt32, 17729 argLen: 1, 17730 resultInArg0: true, 17731 clobberFlags: true, 17732 asm: s390x.AANDW, 17733 reg: regInfo{ 17734 inputs: []inputInfo{ 17735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17736 }, 17737 outputs: []outputInfo{ 17738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17739 }, 17740 }, 17741 }, 17742 { 17743 name: "ANDload", 17744 auxType: auxSymOff, 17745 argLen: 3, 17746 resultInArg0: true, 17747 clobberFlags: true, 17748 faultOnNilArg1: true, 17749 asm: s390x.AAND, 17750 reg: regInfo{ 17751 inputs: []inputInfo{ 17752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17753 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17754 }, 17755 outputs: []outputInfo{ 17756 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17757 }, 17758 }, 17759 }, 17760 { 17761 name: "ANDWload", 17762 auxType: auxSymOff, 17763 argLen: 3, 17764 resultInArg0: true, 17765 clobberFlags: true, 17766 faultOnNilArg1: true, 17767 asm: s390x.AANDW, 17768 reg: regInfo{ 17769 inputs: []inputInfo{ 17770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17771 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17772 }, 17773 outputs: []outputInfo{ 17774 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17775 }, 17776 }, 17777 }, 17778 { 17779 name: "OR", 17780 argLen: 2, 17781 commutative: true, 17782 clobberFlags: true, 17783 asm: s390x.AOR, 17784 reg: regInfo{ 17785 inputs: []inputInfo{ 17786 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17787 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17788 }, 17789 outputs: []outputInfo{ 17790 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17791 }, 17792 }, 17793 }, 17794 { 17795 name: "ORW", 17796 argLen: 2, 17797 commutative: true, 17798 clobberFlags: true, 17799 asm: s390x.AORW, 17800 reg: regInfo{ 17801 inputs: []inputInfo{ 17802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17803 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17804 }, 17805 outputs: []outputInfo{ 17806 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17807 }, 17808 }, 17809 }, 17810 { 17811 name: "ORconst", 17812 auxType: auxInt64, 17813 argLen: 1, 17814 resultInArg0: true, 17815 clobberFlags: true, 17816 asm: s390x.AOR, 17817 reg: regInfo{ 17818 inputs: []inputInfo{ 17819 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17820 }, 17821 outputs: []outputInfo{ 17822 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17823 }, 17824 }, 17825 }, 17826 { 17827 name: "ORWconst", 17828 auxType: auxInt32, 17829 argLen: 1, 17830 resultInArg0: true, 17831 clobberFlags: true, 17832 asm: s390x.AORW, 17833 reg: regInfo{ 17834 inputs: []inputInfo{ 17835 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17836 }, 17837 outputs: []outputInfo{ 17838 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17839 }, 17840 }, 17841 }, 17842 { 17843 name: "ORload", 17844 auxType: auxSymOff, 17845 argLen: 3, 17846 resultInArg0: true, 17847 clobberFlags: true, 17848 faultOnNilArg1: true, 17849 asm: s390x.AOR, 17850 reg: regInfo{ 17851 inputs: []inputInfo{ 17852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17853 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17854 }, 17855 outputs: []outputInfo{ 17856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17857 }, 17858 }, 17859 }, 17860 { 17861 name: "ORWload", 17862 auxType: auxSymOff, 17863 argLen: 3, 17864 resultInArg0: true, 17865 clobberFlags: true, 17866 faultOnNilArg1: true, 17867 asm: s390x.AORW, 17868 reg: regInfo{ 17869 inputs: []inputInfo{ 17870 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17871 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17872 }, 17873 outputs: []outputInfo{ 17874 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17875 }, 17876 }, 17877 }, 17878 { 17879 name: "XOR", 17880 argLen: 2, 17881 commutative: true, 17882 clobberFlags: true, 17883 asm: s390x.AXOR, 17884 reg: regInfo{ 17885 inputs: []inputInfo{ 17886 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17887 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17888 }, 17889 outputs: []outputInfo{ 17890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17891 }, 17892 }, 17893 }, 17894 { 17895 name: "XORW", 17896 argLen: 2, 17897 commutative: true, 17898 clobberFlags: true, 17899 asm: s390x.AXORW, 17900 reg: regInfo{ 17901 inputs: []inputInfo{ 17902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17903 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17904 }, 17905 outputs: []outputInfo{ 17906 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17907 }, 17908 }, 17909 }, 17910 { 17911 name: "XORconst", 17912 auxType: auxInt64, 17913 argLen: 1, 17914 resultInArg0: true, 17915 clobberFlags: true, 17916 asm: s390x.AXOR, 17917 reg: regInfo{ 17918 inputs: []inputInfo{ 17919 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17920 }, 17921 outputs: []outputInfo{ 17922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17923 }, 17924 }, 17925 }, 17926 { 17927 name: "XORWconst", 17928 auxType: auxInt32, 17929 argLen: 1, 17930 resultInArg0: true, 17931 clobberFlags: true, 17932 asm: s390x.AXORW, 17933 reg: regInfo{ 17934 inputs: []inputInfo{ 17935 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17936 }, 17937 outputs: []outputInfo{ 17938 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17939 }, 17940 }, 17941 }, 17942 { 17943 name: "XORload", 17944 auxType: auxSymOff, 17945 argLen: 3, 17946 resultInArg0: true, 17947 clobberFlags: true, 17948 faultOnNilArg1: true, 17949 asm: s390x.AXOR, 17950 reg: regInfo{ 17951 inputs: []inputInfo{ 17952 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17953 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17954 }, 17955 outputs: []outputInfo{ 17956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17957 }, 17958 }, 17959 }, 17960 { 17961 name: "XORWload", 17962 auxType: auxSymOff, 17963 argLen: 3, 17964 resultInArg0: true, 17965 clobberFlags: true, 17966 faultOnNilArg1: true, 17967 asm: s390x.AXORW, 17968 reg: regInfo{ 17969 inputs: []inputInfo{ 17970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17971 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17972 }, 17973 outputs: []outputInfo{ 17974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17975 }, 17976 }, 17977 }, 17978 { 17979 name: "CMP", 17980 argLen: 2, 17981 asm: s390x.ACMP, 17982 reg: regInfo{ 17983 inputs: []inputInfo{ 17984 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17985 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17986 }, 17987 }, 17988 }, 17989 { 17990 name: "CMPW", 17991 argLen: 2, 17992 asm: s390x.ACMPW, 17993 reg: regInfo{ 17994 inputs: []inputInfo{ 17995 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17996 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17997 }, 17998 }, 17999 }, 18000 { 18001 name: "CMPU", 18002 argLen: 2, 18003 asm: s390x.ACMPU, 18004 reg: regInfo{ 18005 inputs: []inputInfo{ 18006 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18007 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18008 }, 18009 }, 18010 }, 18011 { 18012 name: "CMPWU", 18013 argLen: 2, 18014 asm: s390x.ACMPWU, 18015 reg: regInfo{ 18016 inputs: []inputInfo{ 18017 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18018 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18019 }, 18020 }, 18021 }, 18022 { 18023 name: "CMPconst", 18024 auxType: auxInt64, 18025 argLen: 1, 18026 asm: s390x.ACMP, 18027 reg: regInfo{ 18028 inputs: []inputInfo{ 18029 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18030 }, 18031 }, 18032 }, 18033 { 18034 name: "CMPWconst", 18035 auxType: auxInt32, 18036 argLen: 1, 18037 asm: s390x.ACMPW, 18038 reg: regInfo{ 18039 inputs: []inputInfo{ 18040 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18041 }, 18042 }, 18043 }, 18044 { 18045 name: "CMPUconst", 18046 auxType: auxInt64, 18047 argLen: 1, 18048 asm: s390x.ACMPU, 18049 reg: regInfo{ 18050 inputs: []inputInfo{ 18051 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18052 }, 18053 }, 18054 }, 18055 { 18056 name: "CMPWUconst", 18057 auxType: auxInt32, 18058 argLen: 1, 18059 asm: s390x.ACMPWU, 18060 reg: regInfo{ 18061 inputs: []inputInfo{ 18062 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18063 }, 18064 }, 18065 }, 18066 { 18067 name: "FCMPS", 18068 argLen: 2, 18069 asm: s390x.ACEBR, 18070 reg: regInfo{ 18071 inputs: []inputInfo{ 18072 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18073 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18074 }, 18075 }, 18076 }, 18077 { 18078 name: "FCMP", 18079 argLen: 2, 18080 asm: s390x.AFCMPU, 18081 reg: regInfo{ 18082 inputs: []inputInfo{ 18083 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18084 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18085 }, 18086 }, 18087 }, 18088 { 18089 name: "SLD", 18090 argLen: 2, 18091 asm: s390x.ASLD, 18092 reg: regInfo{ 18093 inputs: []inputInfo{ 18094 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18096 }, 18097 outputs: []outputInfo{ 18098 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18099 }, 18100 }, 18101 }, 18102 { 18103 name: "SLW", 18104 argLen: 2, 18105 asm: s390x.ASLW, 18106 reg: regInfo{ 18107 inputs: []inputInfo{ 18108 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18109 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18110 }, 18111 outputs: []outputInfo{ 18112 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18113 }, 18114 }, 18115 }, 18116 { 18117 name: "SLDconst", 18118 auxType: auxInt64, 18119 argLen: 1, 18120 asm: s390x.ASLD, 18121 reg: regInfo{ 18122 inputs: []inputInfo{ 18123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18124 }, 18125 outputs: []outputInfo{ 18126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18127 }, 18128 }, 18129 }, 18130 { 18131 name: "SLWconst", 18132 auxType: auxInt32, 18133 argLen: 1, 18134 asm: s390x.ASLW, 18135 reg: regInfo{ 18136 inputs: []inputInfo{ 18137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18138 }, 18139 outputs: []outputInfo{ 18140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18141 }, 18142 }, 18143 }, 18144 { 18145 name: "SRD", 18146 argLen: 2, 18147 asm: s390x.ASRD, 18148 reg: regInfo{ 18149 inputs: []inputInfo{ 18150 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18152 }, 18153 outputs: []outputInfo{ 18154 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18155 }, 18156 }, 18157 }, 18158 { 18159 name: "SRW", 18160 argLen: 2, 18161 asm: s390x.ASRW, 18162 reg: regInfo{ 18163 inputs: []inputInfo{ 18164 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18166 }, 18167 outputs: []outputInfo{ 18168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18169 }, 18170 }, 18171 }, 18172 { 18173 name: "SRDconst", 18174 auxType: auxInt64, 18175 argLen: 1, 18176 asm: s390x.ASRD, 18177 reg: regInfo{ 18178 inputs: []inputInfo{ 18179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18180 }, 18181 outputs: []outputInfo{ 18182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18183 }, 18184 }, 18185 }, 18186 { 18187 name: "SRWconst", 18188 auxType: auxInt32, 18189 argLen: 1, 18190 asm: s390x.ASRW, 18191 reg: regInfo{ 18192 inputs: []inputInfo{ 18193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18194 }, 18195 outputs: []outputInfo{ 18196 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18197 }, 18198 }, 18199 }, 18200 { 18201 name: "SRAD", 18202 argLen: 2, 18203 clobberFlags: true, 18204 asm: s390x.ASRAD, 18205 reg: regInfo{ 18206 inputs: []inputInfo{ 18207 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18209 }, 18210 outputs: []outputInfo{ 18211 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18212 }, 18213 }, 18214 }, 18215 { 18216 name: "SRAW", 18217 argLen: 2, 18218 clobberFlags: true, 18219 asm: s390x.ASRAW, 18220 reg: regInfo{ 18221 inputs: []inputInfo{ 18222 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18224 }, 18225 outputs: []outputInfo{ 18226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18227 }, 18228 }, 18229 }, 18230 { 18231 name: "SRADconst", 18232 auxType: auxInt64, 18233 argLen: 1, 18234 clobberFlags: true, 18235 asm: s390x.ASRAD, 18236 reg: regInfo{ 18237 inputs: []inputInfo{ 18238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18239 }, 18240 outputs: []outputInfo{ 18241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18242 }, 18243 }, 18244 }, 18245 { 18246 name: "SRAWconst", 18247 auxType: auxInt32, 18248 argLen: 1, 18249 clobberFlags: true, 18250 asm: s390x.ASRAW, 18251 reg: regInfo{ 18252 inputs: []inputInfo{ 18253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18254 }, 18255 outputs: []outputInfo{ 18256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18257 }, 18258 }, 18259 }, 18260 { 18261 name: "RLLGconst", 18262 auxType: auxInt64, 18263 argLen: 1, 18264 asm: s390x.ARLLG, 18265 reg: regInfo{ 18266 inputs: []inputInfo{ 18267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18268 }, 18269 outputs: []outputInfo{ 18270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18271 }, 18272 }, 18273 }, 18274 { 18275 name: "RLLconst", 18276 auxType: auxInt32, 18277 argLen: 1, 18278 asm: s390x.ARLL, 18279 reg: regInfo{ 18280 inputs: []inputInfo{ 18281 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18282 }, 18283 outputs: []outputInfo{ 18284 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18285 }, 18286 }, 18287 }, 18288 { 18289 name: "NEG", 18290 argLen: 1, 18291 clobberFlags: true, 18292 asm: s390x.ANEG, 18293 reg: regInfo{ 18294 inputs: []inputInfo{ 18295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18296 }, 18297 outputs: []outputInfo{ 18298 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18299 }, 18300 }, 18301 }, 18302 { 18303 name: "NEGW", 18304 argLen: 1, 18305 clobberFlags: true, 18306 asm: s390x.ANEGW, 18307 reg: regInfo{ 18308 inputs: []inputInfo{ 18309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18310 }, 18311 outputs: []outputInfo{ 18312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18313 }, 18314 }, 18315 }, 18316 { 18317 name: "NOT", 18318 argLen: 1, 18319 resultInArg0: true, 18320 clobberFlags: true, 18321 reg: regInfo{ 18322 inputs: []inputInfo{ 18323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18324 }, 18325 outputs: []outputInfo{ 18326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18327 }, 18328 }, 18329 }, 18330 { 18331 name: "NOTW", 18332 argLen: 1, 18333 resultInArg0: true, 18334 clobberFlags: true, 18335 reg: regInfo{ 18336 inputs: []inputInfo{ 18337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18338 }, 18339 outputs: []outputInfo{ 18340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18341 }, 18342 }, 18343 }, 18344 { 18345 name: "FSQRT", 18346 argLen: 1, 18347 asm: s390x.AFSQRT, 18348 reg: regInfo{ 18349 inputs: []inputInfo{ 18350 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18351 }, 18352 outputs: []outputInfo{ 18353 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18354 }, 18355 }, 18356 }, 18357 { 18358 name: "SUBEcarrymask", 18359 argLen: 1, 18360 asm: s390x.ASUBE, 18361 reg: regInfo{ 18362 outputs: []outputInfo{ 18363 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18364 }, 18365 }, 18366 }, 18367 { 18368 name: "SUBEWcarrymask", 18369 argLen: 1, 18370 asm: s390x.ASUBE, 18371 reg: regInfo{ 18372 outputs: []outputInfo{ 18373 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18374 }, 18375 }, 18376 }, 18377 { 18378 name: "MOVDEQ", 18379 argLen: 3, 18380 resultInArg0: true, 18381 asm: s390x.AMOVDEQ, 18382 reg: regInfo{ 18383 inputs: []inputInfo{ 18384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18385 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18386 }, 18387 outputs: []outputInfo{ 18388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18389 }, 18390 }, 18391 }, 18392 { 18393 name: "MOVDNE", 18394 argLen: 3, 18395 resultInArg0: true, 18396 asm: s390x.AMOVDNE, 18397 reg: regInfo{ 18398 inputs: []inputInfo{ 18399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18400 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18401 }, 18402 outputs: []outputInfo{ 18403 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18404 }, 18405 }, 18406 }, 18407 { 18408 name: "MOVDLT", 18409 argLen: 3, 18410 resultInArg0: true, 18411 asm: s390x.AMOVDLT, 18412 reg: regInfo{ 18413 inputs: []inputInfo{ 18414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18415 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18416 }, 18417 outputs: []outputInfo{ 18418 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18419 }, 18420 }, 18421 }, 18422 { 18423 name: "MOVDLE", 18424 argLen: 3, 18425 resultInArg0: true, 18426 asm: s390x.AMOVDLE, 18427 reg: regInfo{ 18428 inputs: []inputInfo{ 18429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18430 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18431 }, 18432 outputs: []outputInfo{ 18433 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18434 }, 18435 }, 18436 }, 18437 { 18438 name: "MOVDGT", 18439 argLen: 3, 18440 resultInArg0: true, 18441 asm: s390x.AMOVDGT, 18442 reg: regInfo{ 18443 inputs: []inputInfo{ 18444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18445 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18446 }, 18447 outputs: []outputInfo{ 18448 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18449 }, 18450 }, 18451 }, 18452 { 18453 name: "MOVDGE", 18454 argLen: 3, 18455 resultInArg0: true, 18456 asm: s390x.AMOVDGE, 18457 reg: regInfo{ 18458 inputs: []inputInfo{ 18459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18460 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18461 }, 18462 outputs: []outputInfo{ 18463 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18464 }, 18465 }, 18466 }, 18467 { 18468 name: "MOVDGTnoinv", 18469 argLen: 3, 18470 resultInArg0: true, 18471 asm: s390x.AMOVDGT, 18472 reg: regInfo{ 18473 inputs: []inputInfo{ 18474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18475 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18476 }, 18477 outputs: []outputInfo{ 18478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18479 }, 18480 }, 18481 }, 18482 { 18483 name: "MOVDGEnoinv", 18484 argLen: 3, 18485 resultInArg0: true, 18486 asm: s390x.AMOVDGE, 18487 reg: regInfo{ 18488 inputs: []inputInfo{ 18489 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18490 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18491 }, 18492 outputs: []outputInfo{ 18493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18494 }, 18495 }, 18496 }, 18497 { 18498 name: "MOVBreg", 18499 argLen: 1, 18500 asm: s390x.AMOVB, 18501 reg: regInfo{ 18502 inputs: []inputInfo{ 18503 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18504 }, 18505 outputs: []outputInfo{ 18506 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18507 }, 18508 }, 18509 }, 18510 { 18511 name: "MOVBZreg", 18512 argLen: 1, 18513 asm: s390x.AMOVBZ, 18514 reg: regInfo{ 18515 inputs: []inputInfo{ 18516 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18517 }, 18518 outputs: []outputInfo{ 18519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18520 }, 18521 }, 18522 }, 18523 { 18524 name: "MOVHreg", 18525 argLen: 1, 18526 asm: s390x.AMOVH, 18527 reg: regInfo{ 18528 inputs: []inputInfo{ 18529 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18530 }, 18531 outputs: []outputInfo{ 18532 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18533 }, 18534 }, 18535 }, 18536 { 18537 name: "MOVHZreg", 18538 argLen: 1, 18539 asm: s390x.AMOVHZ, 18540 reg: regInfo{ 18541 inputs: []inputInfo{ 18542 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18543 }, 18544 outputs: []outputInfo{ 18545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18546 }, 18547 }, 18548 }, 18549 { 18550 name: "MOVWreg", 18551 argLen: 1, 18552 asm: s390x.AMOVW, 18553 reg: regInfo{ 18554 inputs: []inputInfo{ 18555 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18556 }, 18557 outputs: []outputInfo{ 18558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18559 }, 18560 }, 18561 }, 18562 { 18563 name: "MOVWZreg", 18564 argLen: 1, 18565 asm: s390x.AMOVWZ, 18566 reg: regInfo{ 18567 inputs: []inputInfo{ 18568 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18569 }, 18570 outputs: []outputInfo{ 18571 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18572 }, 18573 }, 18574 }, 18575 { 18576 name: "MOVDreg", 18577 argLen: 1, 18578 asm: s390x.AMOVD, 18579 reg: regInfo{ 18580 inputs: []inputInfo{ 18581 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18582 }, 18583 outputs: []outputInfo{ 18584 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18585 }, 18586 }, 18587 }, 18588 { 18589 name: "MOVDnop", 18590 argLen: 1, 18591 resultInArg0: true, 18592 reg: regInfo{ 18593 inputs: []inputInfo{ 18594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18595 }, 18596 outputs: []outputInfo{ 18597 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18598 }, 18599 }, 18600 }, 18601 { 18602 name: "MOVDconst", 18603 auxType: auxInt64, 18604 argLen: 0, 18605 rematerializeable: true, 18606 asm: s390x.AMOVD, 18607 reg: regInfo{ 18608 outputs: []outputInfo{ 18609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18610 }, 18611 }, 18612 }, 18613 { 18614 name: "CFDBRA", 18615 argLen: 1, 18616 asm: s390x.ACFDBRA, 18617 reg: regInfo{ 18618 inputs: []inputInfo{ 18619 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18620 }, 18621 outputs: []outputInfo{ 18622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18623 }, 18624 }, 18625 }, 18626 { 18627 name: "CGDBRA", 18628 argLen: 1, 18629 asm: s390x.ACGDBRA, 18630 reg: regInfo{ 18631 inputs: []inputInfo{ 18632 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18633 }, 18634 outputs: []outputInfo{ 18635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18636 }, 18637 }, 18638 }, 18639 { 18640 name: "CFEBRA", 18641 argLen: 1, 18642 asm: s390x.ACFEBRA, 18643 reg: regInfo{ 18644 inputs: []inputInfo{ 18645 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18646 }, 18647 outputs: []outputInfo{ 18648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18649 }, 18650 }, 18651 }, 18652 { 18653 name: "CGEBRA", 18654 argLen: 1, 18655 asm: s390x.ACGEBRA, 18656 reg: regInfo{ 18657 inputs: []inputInfo{ 18658 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18659 }, 18660 outputs: []outputInfo{ 18661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18662 }, 18663 }, 18664 }, 18665 { 18666 name: "CEFBRA", 18667 argLen: 1, 18668 asm: s390x.ACEFBRA, 18669 reg: regInfo{ 18670 inputs: []inputInfo{ 18671 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18672 }, 18673 outputs: []outputInfo{ 18674 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18675 }, 18676 }, 18677 }, 18678 { 18679 name: "CDFBRA", 18680 argLen: 1, 18681 asm: s390x.ACDFBRA, 18682 reg: regInfo{ 18683 inputs: []inputInfo{ 18684 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18685 }, 18686 outputs: []outputInfo{ 18687 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18688 }, 18689 }, 18690 }, 18691 { 18692 name: "CEGBRA", 18693 argLen: 1, 18694 asm: s390x.ACEGBRA, 18695 reg: regInfo{ 18696 inputs: []inputInfo{ 18697 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18698 }, 18699 outputs: []outputInfo{ 18700 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18701 }, 18702 }, 18703 }, 18704 { 18705 name: "CDGBRA", 18706 argLen: 1, 18707 asm: s390x.ACDGBRA, 18708 reg: regInfo{ 18709 inputs: []inputInfo{ 18710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18711 }, 18712 outputs: []outputInfo{ 18713 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18714 }, 18715 }, 18716 }, 18717 { 18718 name: "LEDBR", 18719 argLen: 1, 18720 asm: s390x.ALEDBR, 18721 reg: regInfo{ 18722 inputs: []inputInfo{ 18723 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18724 }, 18725 outputs: []outputInfo{ 18726 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18727 }, 18728 }, 18729 }, 18730 { 18731 name: "LDEBR", 18732 argLen: 1, 18733 asm: s390x.ALDEBR, 18734 reg: regInfo{ 18735 inputs: []inputInfo{ 18736 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18737 }, 18738 outputs: []outputInfo{ 18739 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18740 }, 18741 }, 18742 }, 18743 { 18744 name: "MOVDaddr", 18745 auxType: auxSymOff, 18746 argLen: 1, 18747 rematerializeable: true, 18748 clobberFlags: true, 18749 reg: regInfo{ 18750 inputs: []inputInfo{ 18751 {0, 4295000064}, // SP SB 18752 }, 18753 outputs: []outputInfo{ 18754 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18755 }, 18756 }, 18757 }, 18758 { 18759 name: "MOVDaddridx", 18760 auxType: auxSymOff, 18761 argLen: 2, 18762 clobberFlags: true, 18763 reg: regInfo{ 18764 inputs: []inputInfo{ 18765 {0, 4295000064}, // SP SB 18766 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18767 }, 18768 outputs: []outputInfo{ 18769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18770 }, 18771 }, 18772 }, 18773 { 18774 name: "MOVBZload", 18775 auxType: auxSymOff, 18776 argLen: 2, 18777 clobberFlags: true, 18778 faultOnNilArg0: true, 18779 asm: s390x.AMOVBZ, 18780 reg: regInfo{ 18781 inputs: []inputInfo{ 18782 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18783 }, 18784 outputs: []outputInfo{ 18785 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18786 }, 18787 }, 18788 }, 18789 { 18790 name: "MOVBload", 18791 auxType: auxSymOff, 18792 argLen: 2, 18793 clobberFlags: true, 18794 faultOnNilArg0: true, 18795 asm: s390x.AMOVB, 18796 reg: regInfo{ 18797 inputs: []inputInfo{ 18798 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18799 }, 18800 outputs: []outputInfo{ 18801 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18802 }, 18803 }, 18804 }, 18805 { 18806 name: "MOVHZload", 18807 auxType: auxSymOff, 18808 argLen: 2, 18809 clobberFlags: true, 18810 faultOnNilArg0: true, 18811 asm: s390x.AMOVHZ, 18812 reg: regInfo{ 18813 inputs: []inputInfo{ 18814 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18815 }, 18816 outputs: []outputInfo{ 18817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18818 }, 18819 }, 18820 }, 18821 { 18822 name: "MOVHload", 18823 auxType: auxSymOff, 18824 argLen: 2, 18825 clobberFlags: true, 18826 faultOnNilArg0: true, 18827 asm: s390x.AMOVH, 18828 reg: regInfo{ 18829 inputs: []inputInfo{ 18830 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18831 }, 18832 outputs: []outputInfo{ 18833 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18834 }, 18835 }, 18836 }, 18837 { 18838 name: "MOVWZload", 18839 auxType: auxSymOff, 18840 argLen: 2, 18841 clobberFlags: true, 18842 faultOnNilArg0: true, 18843 asm: s390x.AMOVWZ, 18844 reg: regInfo{ 18845 inputs: []inputInfo{ 18846 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18847 }, 18848 outputs: []outputInfo{ 18849 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18850 }, 18851 }, 18852 }, 18853 { 18854 name: "MOVWload", 18855 auxType: auxSymOff, 18856 argLen: 2, 18857 clobberFlags: true, 18858 faultOnNilArg0: true, 18859 asm: s390x.AMOVW, 18860 reg: regInfo{ 18861 inputs: []inputInfo{ 18862 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18863 }, 18864 outputs: []outputInfo{ 18865 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18866 }, 18867 }, 18868 }, 18869 { 18870 name: "MOVDload", 18871 auxType: auxSymOff, 18872 argLen: 2, 18873 clobberFlags: true, 18874 faultOnNilArg0: true, 18875 asm: s390x.AMOVD, 18876 reg: regInfo{ 18877 inputs: []inputInfo{ 18878 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18879 }, 18880 outputs: []outputInfo{ 18881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18882 }, 18883 }, 18884 }, 18885 { 18886 name: "MOVWBR", 18887 argLen: 1, 18888 asm: s390x.AMOVWBR, 18889 reg: regInfo{ 18890 inputs: []inputInfo{ 18891 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18892 }, 18893 outputs: []outputInfo{ 18894 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18895 }, 18896 }, 18897 }, 18898 { 18899 name: "MOVDBR", 18900 argLen: 1, 18901 asm: s390x.AMOVDBR, 18902 reg: regInfo{ 18903 inputs: []inputInfo{ 18904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18905 }, 18906 outputs: []outputInfo{ 18907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18908 }, 18909 }, 18910 }, 18911 { 18912 name: "MOVHBRload", 18913 auxType: auxSymOff, 18914 argLen: 2, 18915 clobberFlags: true, 18916 faultOnNilArg0: true, 18917 asm: s390x.AMOVHBR, 18918 reg: regInfo{ 18919 inputs: []inputInfo{ 18920 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18921 }, 18922 outputs: []outputInfo{ 18923 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18924 }, 18925 }, 18926 }, 18927 { 18928 name: "MOVWBRload", 18929 auxType: auxSymOff, 18930 argLen: 2, 18931 clobberFlags: true, 18932 faultOnNilArg0: true, 18933 asm: s390x.AMOVWBR, 18934 reg: regInfo{ 18935 inputs: []inputInfo{ 18936 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18937 }, 18938 outputs: []outputInfo{ 18939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18940 }, 18941 }, 18942 }, 18943 { 18944 name: "MOVDBRload", 18945 auxType: auxSymOff, 18946 argLen: 2, 18947 clobberFlags: true, 18948 faultOnNilArg0: true, 18949 asm: s390x.AMOVDBR, 18950 reg: regInfo{ 18951 inputs: []inputInfo{ 18952 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18953 }, 18954 outputs: []outputInfo{ 18955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18956 }, 18957 }, 18958 }, 18959 { 18960 name: "MOVBstore", 18961 auxType: auxSymOff, 18962 argLen: 3, 18963 clobberFlags: true, 18964 faultOnNilArg0: true, 18965 asm: s390x.AMOVB, 18966 reg: regInfo{ 18967 inputs: []inputInfo{ 18968 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18969 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18970 }, 18971 }, 18972 }, 18973 { 18974 name: "MOVHstore", 18975 auxType: auxSymOff, 18976 argLen: 3, 18977 clobberFlags: true, 18978 faultOnNilArg0: true, 18979 asm: s390x.AMOVH, 18980 reg: regInfo{ 18981 inputs: []inputInfo{ 18982 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18983 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18984 }, 18985 }, 18986 }, 18987 { 18988 name: "MOVWstore", 18989 auxType: auxSymOff, 18990 argLen: 3, 18991 clobberFlags: true, 18992 faultOnNilArg0: true, 18993 asm: s390x.AMOVW, 18994 reg: regInfo{ 18995 inputs: []inputInfo{ 18996 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18997 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18998 }, 18999 }, 19000 }, 19001 { 19002 name: "MOVDstore", 19003 auxType: auxSymOff, 19004 argLen: 3, 19005 clobberFlags: true, 19006 faultOnNilArg0: true, 19007 asm: s390x.AMOVD, 19008 reg: regInfo{ 19009 inputs: []inputInfo{ 19010 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19011 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19012 }, 19013 }, 19014 }, 19015 { 19016 name: "MOVHBRstore", 19017 auxType: auxSymOff, 19018 argLen: 3, 19019 clobberFlags: true, 19020 faultOnNilArg0: true, 19021 asm: s390x.AMOVHBR, 19022 reg: regInfo{ 19023 inputs: []inputInfo{ 19024 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19025 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19026 }, 19027 }, 19028 }, 19029 { 19030 name: "MOVWBRstore", 19031 auxType: auxSymOff, 19032 argLen: 3, 19033 clobberFlags: true, 19034 faultOnNilArg0: true, 19035 asm: s390x.AMOVWBR, 19036 reg: regInfo{ 19037 inputs: []inputInfo{ 19038 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19039 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19040 }, 19041 }, 19042 }, 19043 { 19044 name: "MOVDBRstore", 19045 auxType: auxSymOff, 19046 argLen: 3, 19047 clobberFlags: true, 19048 faultOnNilArg0: true, 19049 asm: s390x.AMOVDBR, 19050 reg: regInfo{ 19051 inputs: []inputInfo{ 19052 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19053 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19054 }, 19055 }, 19056 }, 19057 { 19058 name: "MVC", 19059 auxType: auxSymValAndOff, 19060 argLen: 3, 19061 clobberFlags: true, 19062 faultOnNilArg0: true, 19063 faultOnNilArg1: true, 19064 asm: s390x.AMVC, 19065 reg: regInfo{ 19066 inputs: []inputInfo{ 19067 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19068 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19069 }, 19070 }, 19071 }, 19072 { 19073 name: "MOVBZloadidx", 19074 auxType: auxSymOff, 19075 argLen: 3, 19076 clobberFlags: true, 19077 asm: s390x.AMOVBZ, 19078 reg: regInfo{ 19079 inputs: []inputInfo{ 19080 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19081 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19082 }, 19083 outputs: []outputInfo{ 19084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19085 }, 19086 }, 19087 }, 19088 { 19089 name: "MOVHZloadidx", 19090 auxType: auxSymOff, 19091 argLen: 3, 19092 clobberFlags: true, 19093 asm: s390x.AMOVHZ, 19094 reg: regInfo{ 19095 inputs: []inputInfo{ 19096 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19097 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19098 }, 19099 outputs: []outputInfo{ 19100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19101 }, 19102 }, 19103 }, 19104 { 19105 name: "MOVWZloadidx", 19106 auxType: auxSymOff, 19107 argLen: 3, 19108 clobberFlags: true, 19109 asm: s390x.AMOVWZ, 19110 reg: regInfo{ 19111 inputs: []inputInfo{ 19112 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19113 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19114 }, 19115 outputs: []outputInfo{ 19116 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19117 }, 19118 }, 19119 }, 19120 { 19121 name: "MOVDloadidx", 19122 auxType: auxSymOff, 19123 argLen: 3, 19124 clobberFlags: true, 19125 asm: s390x.AMOVD, 19126 reg: regInfo{ 19127 inputs: []inputInfo{ 19128 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19129 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19130 }, 19131 outputs: []outputInfo{ 19132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19133 }, 19134 }, 19135 }, 19136 { 19137 name: "MOVHBRloadidx", 19138 auxType: auxSymOff, 19139 argLen: 3, 19140 clobberFlags: true, 19141 asm: s390x.AMOVHBR, 19142 reg: regInfo{ 19143 inputs: []inputInfo{ 19144 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19145 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19146 }, 19147 outputs: []outputInfo{ 19148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19149 }, 19150 }, 19151 }, 19152 { 19153 name: "MOVWBRloadidx", 19154 auxType: auxSymOff, 19155 argLen: 3, 19156 clobberFlags: true, 19157 asm: s390x.AMOVWBR, 19158 reg: regInfo{ 19159 inputs: []inputInfo{ 19160 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19161 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19162 }, 19163 outputs: []outputInfo{ 19164 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19165 }, 19166 }, 19167 }, 19168 { 19169 name: "MOVDBRloadidx", 19170 auxType: auxSymOff, 19171 argLen: 3, 19172 clobberFlags: true, 19173 asm: s390x.AMOVDBR, 19174 reg: regInfo{ 19175 inputs: []inputInfo{ 19176 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19177 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19178 }, 19179 outputs: []outputInfo{ 19180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19181 }, 19182 }, 19183 }, 19184 { 19185 name: "MOVBstoreidx", 19186 auxType: auxSymOff, 19187 argLen: 4, 19188 clobberFlags: true, 19189 asm: s390x.AMOVB, 19190 reg: regInfo{ 19191 inputs: []inputInfo{ 19192 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19193 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19194 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19195 }, 19196 }, 19197 }, 19198 { 19199 name: "MOVHstoreidx", 19200 auxType: auxSymOff, 19201 argLen: 4, 19202 clobberFlags: true, 19203 asm: s390x.AMOVH, 19204 reg: regInfo{ 19205 inputs: []inputInfo{ 19206 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19207 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19208 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19209 }, 19210 }, 19211 }, 19212 { 19213 name: "MOVWstoreidx", 19214 auxType: auxSymOff, 19215 argLen: 4, 19216 clobberFlags: true, 19217 asm: s390x.AMOVW, 19218 reg: regInfo{ 19219 inputs: []inputInfo{ 19220 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19221 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19222 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19223 }, 19224 }, 19225 }, 19226 { 19227 name: "MOVDstoreidx", 19228 auxType: auxSymOff, 19229 argLen: 4, 19230 clobberFlags: true, 19231 asm: s390x.AMOVD, 19232 reg: regInfo{ 19233 inputs: []inputInfo{ 19234 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19235 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19236 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19237 }, 19238 }, 19239 }, 19240 { 19241 name: "MOVHBRstoreidx", 19242 auxType: auxSymOff, 19243 argLen: 4, 19244 clobberFlags: true, 19245 asm: s390x.AMOVHBR, 19246 reg: regInfo{ 19247 inputs: []inputInfo{ 19248 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19249 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19250 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19251 }, 19252 }, 19253 }, 19254 { 19255 name: "MOVWBRstoreidx", 19256 auxType: auxSymOff, 19257 argLen: 4, 19258 clobberFlags: true, 19259 asm: s390x.AMOVWBR, 19260 reg: regInfo{ 19261 inputs: []inputInfo{ 19262 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19263 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19264 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19265 }, 19266 }, 19267 }, 19268 { 19269 name: "MOVDBRstoreidx", 19270 auxType: auxSymOff, 19271 argLen: 4, 19272 clobberFlags: true, 19273 asm: s390x.AMOVDBR, 19274 reg: regInfo{ 19275 inputs: []inputInfo{ 19276 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19277 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19278 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19279 }, 19280 }, 19281 }, 19282 { 19283 name: "MOVBstoreconst", 19284 auxType: auxSymValAndOff, 19285 argLen: 2, 19286 clobberFlags: true, 19287 faultOnNilArg0: true, 19288 asm: s390x.AMOVB, 19289 reg: regInfo{ 19290 inputs: []inputInfo{ 19291 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19292 }, 19293 }, 19294 }, 19295 { 19296 name: "MOVHstoreconst", 19297 auxType: auxSymValAndOff, 19298 argLen: 2, 19299 clobberFlags: true, 19300 faultOnNilArg0: true, 19301 asm: s390x.AMOVH, 19302 reg: regInfo{ 19303 inputs: []inputInfo{ 19304 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19305 }, 19306 }, 19307 }, 19308 { 19309 name: "MOVWstoreconst", 19310 auxType: auxSymValAndOff, 19311 argLen: 2, 19312 clobberFlags: true, 19313 faultOnNilArg0: true, 19314 asm: s390x.AMOVW, 19315 reg: regInfo{ 19316 inputs: []inputInfo{ 19317 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19318 }, 19319 }, 19320 }, 19321 { 19322 name: "MOVDstoreconst", 19323 auxType: auxSymValAndOff, 19324 argLen: 2, 19325 clobberFlags: true, 19326 faultOnNilArg0: true, 19327 asm: s390x.AMOVD, 19328 reg: regInfo{ 19329 inputs: []inputInfo{ 19330 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19331 }, 19332 }, 19333 }, 19334 { 19335 name: "CLEAR", 19336 auxType: auxSymValAndOff, 19337 argLen: 2, 19338 clobberFlags: true, 19339 faultOnNilArg0: true, 19340 asm: s390x.ACLEAR, 19341 reg: regInfo{ 19342 inputs: []inputInfo{ 19343 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19344 }, 19345 }, 19346 }, 19347 { 19348 name: "CALLstatic", 19349 auxType: auxSymOff, 19350 argLen: 1, 19351 clobberFlags: true, 19352 call: true, 19353 reg: regInfo{ 19354 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19355 }, 19356 }, 19357 { 19358 name: "CALLclosure", 19359 auxType: auxInt64, 19360 argLen: 3, 19361 clobberFlags: true, 19362 call: true, 19363 reg: regInfo{ 19364 inputs: []inputInfo{ 19365 {1, 4096}, // R12 19366 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19367 }, 19368 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19369 }, 19370 }, 19371 { 19372 name: "CALLdefer", 19373 auxType: auxInt64, 19374 argLen: 1, 19375 clobberFlags: true, 19376 call: true, 19377 reg: regInfo{ 19378 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19379 }, 19380 }, 19381 { 19382 name: "CALLgo", 19383 auxType: auxInt64, 19384 argLen: 1, 19385 clobberFlags: true, 19386 call: true, 19387 reg: regInfo{ 19388 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19389 }, 19390 }, 19391 { 19392 name: "CALLinter", 19393 auxType: auxInt64, 19394 argLen: 2, 19395 clobberFlags: true, 19396 call: true, 19397 reg: regInfo{ 19398 inputs: []inputInfo{ 19399 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19400 }, 19401 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19402 }, 19403 }, 19404 { 19405 name: "InvertFlags", 19406 argLen: 1, 19407 reg: regInfo{}, 19408 }, 19409 { 19410 name: "LoweredGetG", 19411 argLen: 1, 19412 reg: regInfo{ 19413 outputs: []outputInfo{ 19414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19415 }, 19416 }, 19417 }, 19418 { 19419 name: "LoweredGetClosurePtr", 19420 argLen: 0, 19421 reg: regInfo{ 19422 outputs: []outputInfo{ 19423 {0, 4096}, // R12 19424 }, 19425 }, 19426 }, 19427 { 19428 name: "LoweredNilCheck", 19429 argLen: 2, 19430 clobberFlags: true, 19431 nilCheck: true, 19432 faultOnNilArg0: true, 19433 reg: regInfo{ 19434 inputs: []inputInfo{ 19435 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19436 }, 19437 }, 19438 }, 19439 { 19440 name: "MOVDconvert", 19441 argLen: 2, 19442 asm: s390x.AMOVD, 19443 reg: regInfo{ 19444 inputs: []inputInfo{ 19445 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19446 }, 19447 outputs: []outputInfo{ 19448 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19449 }, 19450 }, 19451 }, 19452 { 19453 name: "FlagEQ", 19454 argLen: 0, 19455 reg: regInfo{}, 19456 }, 19457 { 19458 name: "FlagLT", 19459 argLen: 0, 19460 reg: regInfo{}, 19461 }, 19462 { 19463 name: "FlagGT", 19464 argLen: 0, 19465 reg: regInfo{}, 19466 }, 19467 { 19468 name: "MOVWZatomicload", 19469 auxType: auxSymOff, 19470 argLen: 2, 19471 faultOnNilArg0: true, 19472 asm: s390x.AMOVWZ, 19473 reg: regInfo{ 19474 inputs: []inputInfo{ 19475 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19476 }, 19477 outputs: []outputInfo{ 19478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19479 }, 19480 }, 19481 }, 19482 { 19483 name: "MOVDatomicload", 19484 auxType: auxSymOff, 19485 argLen: 2, 19486 faultOnNilArg0: true, 19487 asm: s390x.AMOVD, 19488 reg: regInfo{ 19489 inputs: []inputInfo{ 19490 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19491 }, 19492 outputs: []outputInfo{ 19493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19494 }, 19495 }, 19496 }, 19497 { 19498 name: "MOVWatomicstore", 19499 auxType: auxSymOff, 19500 argLen: 3, 19501 clobberFlags: true, 19502 faultOnNilArg0: true, 19503 asm: s390x.AMOVW, 19504 reg: regInfo{ 19505 inputs: []inputInfo{ 19506 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19507 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19508 }, 19509 }, 19510 }, 19511 { 19512 name: "MOVDatomicstore", 19513 auxType: auxSymOff, 19514 argLen: 3, 19515 clobberFlags: true, 19516 faultOnNilArg0: true, 19517 asm: s390x.AMOVD, 19518 reg: regInfo{ 19519 inputs: []inputInfo{ 19520 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19521 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19522 }, 19523 }, 19524 }, 19525 { 19526 name: "LAA", 19527 auxType: auxSymOff, 19528 argLen: 3, 19529 faultOnNilArg0: true, 19530 asm: s390x.ALAA, 19531 reg: regInfo{ 19532 inputs: []inputInfo{ 19533 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19534 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19535 }, 19536 outputs: []outputInfo{ 19537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19538 }, 19539 }, 19540 }, 19541 { 19542 name: "LAAG", 19543 auxType: auxSymOff, 19544 argLen: 3, 19545 faultOnNilArg0: true, 19546 asm: s390x.ALAAG, 19547 reg: regInfo{ 19548 inputs: []inputInfo{ 19549 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19550 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19551 }, 19552 outputs: []outputInfo{ 19553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19554 }, 19555 }, 19556 }, 19557 { 19558 name: "AddTupleFirst32", 19559 argLen: 2, 19560 reg: regInfo{}, 19561 }, 19562 { 19563 name: "AddTupleFirst64", 19564 argLen: 2, 19565 reg: regInfo{}, 19566 }, 19567 { 19568 name: "LoweredAtomicCas32", 19569 auxType: auxSymOff, 19570 argLen: 4, 19571 clobberFlags: true, 19572 faultOnNilArg0: true, 19573 asm: s390x.ACS, 19574 reg: regInfo{ 19575 inputs: []inputInfo{ 19576 {1, 1}, // R0 19577 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19578 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19579 }, 19580 clobbers: 1, // R0 19581 outputs: []outputInfo{ 19582 {1, 0}, 19583 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19584 }, 19585 }, 19586 }, 19587 { 19588 name: "LoweredAtomicCas64", 19589 auxType: auxSymOff, 19590 argLen: 4, 19591 clobberFlags: true, 19592 faultOnNilArg0: true, 19593 asm: s390x.ACSG, 19594 reg: regInfo{ 19595 inputs: []inputInfo{ 19596 {1, 1}, // R0 19597 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19598 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19599 }, 19600 clobbers: 1, // R0 19601 outputs: []outputInfo{ 19602 {1, 0}, 19603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19604 }, 19605 }, 19606 }, 19607 { 19608 name: "LoweredAtomicExchange32", 19609 auxType: auxSymOff, 19610 argLen: 3, 19611 clobberFlags: true, 19612 faultOnNilArg0: true, 19613 asm: s390x.ACS, 19614 reg: regInfo{ 19615 inputs: []inputInfo{ 19616 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19617 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19618 }, 19619 outputs: []outputInfo{ 19620 {1, 0}, 19621 {0, 1}, // R0 19622 }, 19623 }, 19624 }, 19625 { 19626 name: "LoweredAtomicExchange64", 19627 auxType: auxSymOff, 19628 argLen: 3, 19629 clobberFlags: true, 19630 faultOnNilArg0: true, 19631 asm: s390x.ACSG, 19632 reg: regInfo{ 19633 inputs: []inputInfo{ 19634 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19635 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19636 }, 19637 outputs: []outputInfo{ 19638 {1, 0}, 19639 {0, 1}, // R0 19640 }, 19641 }, 19642 }, 19643 { 19644 name: "FLOGR", 19645 argLen: 1, 19646 clobberFlags: true, 19647 asm: s390x.AFLOGR, 19648 reg: regInfo{ 19649 inputs: []inputInfo{ 19650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19651 }, 19652 clobbers: 2, // R1 19653 outputs: []outputInfo{ 19654 {0, 1}, // R0 19655 }, 19656 }, 19657 }, 19658 { 19659 name: "STMG2", 19660 auxType: auxSymOff, 19661 argLen: 4, 19662 faultOnNilArg0: true, 19663 asm: s390x.ASTMG, 19664 reg: regInfo{ 19665 inputs: []inputInfo{ 19666 {1, 2}, // R1 19667 {2, 4}, // R2 19668 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19669 }, 19670 }, 19671 }, 19672 { 19673 name: "STMG3", 19674 auxType: auxSymOff, 19675 argLen: 5, 19676 faultOnNilArg0: true, 19677 asm: s390x.ASTMG, 19678 reg: regInfo{ 19679 inputs: []inputInfo{ 19680 {1, 2}, // R1 19681 {2, 4}, // R2 19682 {3, 8}, // R3 19683 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19684 }, 19685 }, 19686 }, 19687 { 19688 name: "STMG4", 19689 auxType: auxSymOff, 19690 argLen: 6, 19691 faultOnNilArg0: true, 19692 asm: s390x.ASTMG, 19693 reg: regInfo{ 19694 inputs: []inputInfo{ 19695 {1, 2}, // R1 19696 {2, 4}, // R2 19697 {3, 8}, // R3 19698 {4, 16}, // R4 19699 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19700 }, 19701 }, 19702 }, 19703 { 19704 name: "STM2", 19705 auxType: auxSymOff, 19706 argLen: 4, 19707 faultOnNilArg0: true, 19708 asm: s390x.ASTMY, 19709 reg: regInfo{ 19710 inputs: []inputInfo{ 19711 {1, 2}, // R1 19712 {2, 4}, // R2 19713 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19714 }, 19715 }, 19716 }, 19717 { 19718 name: "STM3", 19719 auxType: auxSymOff, 19720 argLen: 5, 19721 faultOnNilArg0: true, 19722 asm: s390x.ASTMY, 19723 reg: regInfo{ 19724 inputs: []inputInfo{ 19725 {1, 2}, // R1 19726 {2, 4}, // R2 19727 {3, 8}, // R3 19728 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19729 }, 19730 }, 19731 }, 19732 { 19733 name: "STM4", 19734 auxType: auxSymOff, 19735 argLen: 6, 19736 faultOnNilArg0: true, 19737 asm: s390x.ASTMY, 19738 reg: regInfo{ 19739 inputs: []inputInfo{ 19740 {1, 2}, // R1 19741 {2, 4}, // R2 19742 {3, 8}, // R3 19743 {4, 16}, // R4 19744 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19745 }, 19746 }, 19747 }, 19748 { 19749 name: "LoweredMove", 19750 auxType: auxInt64, 19751 argLen: 4, 19752 clobberFlags: true, 19753 reg: regInfo{ 19754 inputs: []inputInfo{ 19755 {0, 2}, // R1 19756 {1, 4}, // R2 19757 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19758 }, 19759 clobbers: 6, // R1 R2 19760 }, 19761 }, 19762 { 19763 name: "LoweredZero", 19764 auxType: auxInt64, 19765 argLen: 3, 19766 clobberFlags: true, 19767 reg: regInfo{ 19768 inputs: []inputInfo{ 19769 {0, 2}, // R1 19770 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19771 }, 19772 clobbers: 2, // R1 19773 }, 19774 }, 19775 19776 { 19777 name: "Add8", 19778 argLen: 2, 19779 commutative: true, 19780 generic: true, 19781 }, 19782 { 19783 name: "Add16", 19784 argLen: 2, 19785 commutative: true, 19786 generic: true, 19787 }, 19788 { 19789 name: "Add32", 19790 argLen: 2, 19791 commutative: true, 19792 generic: true, 19793 }, 19794 { 19795 name: "Add64", 19796 argLen: 2, 19797 commutative: true, 19798 generic: true, 19799 }, 19800 { 19801 name: "AddPtr", 19802 argLen: 2, 19803 generic: true, 19804 }, 19805 { 19806 name: "Add32F", 19807 argLen: 2, 19808 generic: true, 19809 }, 19810 { 19811 name: "Add64F", 19812 argLen: 2, 19813 generic: true, 19814 }, 19815 { 19816 name: "Sub8", 19817 argLen: 2, 19818 generic: true, 19819 }, 19820 { 19821 name: "Sub16", 19822 argLen: 2, 19823 generic: true, 19824 }, 19825 { 19826 name: "Sub32", 19827 argLen: 2, 19828 generic: true, 19829 }, 19830 { 19831 name: "Sub64", 19832 argLen: 2, 19833 generic: true, 19834 }, 19835 { 19836 name: "SubPtr", 19837 argLen: 2, 19838 generic: true, 19839 }, 19840 { 19841 name: "Sub32F", 19842 argLen: 2, 19843 generic: true, 19844 }, 19845 { 19846 name: "Sub64F", 19847 argLen: 2, 19848 generic: true, 19849 }, 19850 { 19851 name: "Mul8", 19852 argLen: 2, 19853 commutative: true, 19854 generic: true, 19855 }, 19856 { 19857 name: "Mul16", 19858 argLen: 2, 19859 commutative: true, 19860 generic: true, 19861 }, 19862 { 19863 name: "Mul32", 19864 argLen: 2, 19865 commutative: true, 19866 generic: true, 19867 }, 19868 { 19869 name: "Mul64", 19870 argLen: 2, 19871 commutative: true, 19872 generic: true, 19873 }, 19874 { 19875 name: "Mul32F", 19876 argLen: 2, 19877 generic: true, 19878 }, 19879 { 19880 name: "Mul64F", 19881 argLen: 2, 19882 generic: true, 19883 }, 19884 { 19885 name: "Div32F", 19886 argLen: 2, 19887 generic: true, 19888 }, 19889 { 19890 name: "Div64F", 19891 argLen: 2, 19892 generic: true, 19893 }, 19894 { 19895 name: "Hmul8", 19896 argLen: 2, 19897 generic: true, 19898 }, 19899 { 19900 name: "Hmul8u", 19901 argLen: 2, 19902 generic: true, 19903 }, 19904 { 19905 name: "Hmul16", 19906 argLen: 2, 19907 generic: true, 19908 }, 19909 { 19910 name: "Hmul16u", 19911 argLen: 2, 19912 generic: true, 19913 }, 19914 { 19915 name: "Hmul32", 19916 argLen: 2, 19917 generic: true, 19918 }, 19919 { 19920 name: "Hmul32u", 19921 argLen: 2, 19922 generic: true, 19923 }, 19924 { 19925 name: "Hmul64", 19926 argLen: 2, 19927 generic: true, 19928 }, 19929 { 19930 name: "Hmul64u", 19931 argLen: 2, 19932 generic: true, 19933 }, 19934 { 19935 name: "Mul32uhilo", 19936 argLen: 2, 19937 generic: true, 19938 }, 19939 { 19940 name: "Mul64uhilo", 19941 argLen: 2, 19942 generic: true, 19943 }, 19944 { 19945 name: "Avg64u", 19946 argLen: 2, 19947 generic: true, 19948 }, 19949 { 19950 name: "Div8", 19951 argLen: 2, 19952 generic: true, 19953 }, 19954 { 19955 name: "Div8u", 19956 argLen: 2, 19957 generic: true, 19958 }, 19959 { 19960 name: "Div16", 19961 argLen: 2, 19962 generic: true, 19963 }, 19964 { 19965 name: "Div16u", 19966 argLen: 2, 19967 generic: true, 19968 }, 19969 { 19970 name: "Div32", 19971 argLen: 2, 19972 generic: true, 19973 }, 19974 { 19975 name: "Div32u", 19976 argLen: 2, 19977 generic: true, 19978 }, 19979 { 19980 name: "Div64", 19981 argLen: 2, 19982 generic: true, 19983 }, 19984 { 19985 name: "Div64u", 19986 argLen: 2, 19987 generic: true, 19988 }, 19989 { 19990 name: "Div128u", 19991 argLen: 3, 19992 generic: true, 19993 }, 19994 { 19995 name: "Mod8", 19996 argLen: 2, 19997 generic: true, 19998 }, 19999 { 20000 name: "Mod8u", 20001 argLen: 2, 20002 generic: true, 20003 }, 20004 { 20005 name: "Mod16", 20006 argLen: 2, 20007 generic: true, 20008 }, 20009 { 20010 name: "Mod16u", 20011 argLen: 2, 20012 generic: true, 20013 }, 20014 { 20015 name: "Mod32", 20016 argLen: 2, 20017 generic: true, 20018 }, 20019 { 20020 name: "Mod32u", 20021 argLen: 2, 20022 generic: true, 20023 }, 20024 { 20025 name: "Mod64", 20026 argLen: 2, 20027 generic: true, 20028 }, 20029 { 20030 name: "Mod64u", 20031 argLen: 2, 20032 generic: true, 20033 }, 20034 { 20035 name: "And8", 20036 argLen: 2, 20037 commutative: true, 20038 generic: true, 20039 }, 20040 { 20041 name: "And16", 20042 argLen: 2, 20043 commutative: true, 20044 generic: true, 20045 }, 20046 { 20047 name: "And32", 20048 argLen: 2, 20049 commutative: true, 20050 generic: true, 20051 }, 20052 { 20053 name: "And64", 20054 argLen: 2, 20055 commutative: true, 20056 generic: true, 20057 }, 20058 { 20059 name: "Or8", 20060 argLen: 2, 20061 commutative: true, 20062 generic: true, 20063 }, 20064 { 20065 name: "Or16", 20066 argLen: 2, 20067 commutative: true, 20068 generic: true, 20069 }, 20070 { 20071 name: "Or32", 20072 argLen: 2, 20073 commutative: true, 20074 generic: true, 20075 }, 20076 { 20077 name: "Or64", 20078 argLen: 2, 20079 commutative: true, 20080 generic: true, 20081 }, 20082 { 20083 name: "Xor8", 20084 argLen: 2, 20085 commutative: true, 20086 generic: true, 20087 }, 20088 { 20089 name: "Xor16", 20090 argLen: 2, 20091 commutative: true, 20092 generic: true, 20093 }, 20094 { 20095 name: "Xor32", 20096 argLen: 2, 20097 commutative: true, 20098 generic: true, 20099 }, 20100 { 20101 name: "Xor64", 20102 argLen: 2, 20103 commutative: true, 20104 generic: true, 20105 }, 20106 { 20107 name: "Lsh8x8", 20108 argLen: 2, 20109 generic: true, 20110 }, 20111 { 20112 name: "Lsh8x16", 20113 argLen: 2, 20114 generic: true, 20115 }, 20116 { 20117 name: "Lsh8x32", 20118 argLen: 2, 20119 generic: true, 20120 }, 20121 { 20122 name: "Lsh8x64", 20123 argLen: 2, 20124 generic: true, 20125 }, 20126 { 20127 name: "Lsh16x8", 20128 argLen: 2, 20129 generic: true, 20130 }, 20131 { 20132 name: "Lsh16x16", 20133 argLen: 2, 20134 generic: true, 20135 }, 20136 { 20137 name: "Lsh16x32", 20138 argLen: 2, 20139 generic: true, 20140 }, 20141 { 20142 name: "Lsh16x64", 20143 argLen: 2, 20144 generic: true, 20145 }, 20146 { 20147 name: "Lsh32x8", 20148 argLen: 2, 20149 generic: true, 20150 }, 20151 { 20152 name: "Lsh32x16", 20153 argLen: 2, 20154 generic: true, 20155 }, 20156 { 20157 name: "Lsh32x32", 20158 argLen: 2, 20159 generic: true, 20160 }, 20161 { 20162 name: "Lsh32x64", 20163 argLen: 2, 20164 generic: true, 20165 }, 20166 { 20167 name: "Lsh64x8", 20168 argLen: 2, 20169 generic: true, 20170 }, 20171 { 20172 name: "Lsh64x16", 20173 argLen: 2, 20174 generic: true, 20175 }, 20176 { 20177 name: "Lsh64x32", 20178 argLen: 2, 20179 generic: true, 20180 }, 20181 { 20182 name: "Lsh64x64", 20183 argLen: 2, 20184 generic: true, 20185 }, 20186 { 20187 name: "Rsh8x8", 20188 argLen: 2, 20189 generic: true, 20190 }, 20191 { 20192 name: "Rsh8x16", 20193 argLen: 2, 20194 generic: true, 20195 }, 20196 { 20197 name: "Rsh8x32", 20198 argLen: 2, 20199 generic: true, 20200 }, 20201 { 20202 name: "Rsh8x64", 20203 argLen: 2, 20204 generic: true, 20205 }, 20206 { 20207 name: "Rsh16x8", 20208 argLen: 2, 20209 generic: true, 20210 }, 20211 { 20212 name: "Rsh16x16", 20213 argLen: 2, 20214 generic: true, 20215 }, 20216 { 20217 name: "Rsh16x32", 20218 argLen: 2, 20219 generic: true, 20220 }, 20221 { 20222 name: "Rsh16x64", 20223 argLen: 2, 20224 generic: true, 20225 }, 20226 { 20227 name: "Rsh32x8", 20228 argLen: 2, 20229 generic: true, 20230 }, 20231 { 20232 name: "Rsh32x16", 20233 argLen: 2, 20234 generic: true, 20235 }, 20236 { 20237 name: "Rsh32x32", 20238 argLen: 2, 20239 generic: true, 20240 }, 20241 { 20242 name: "Rsh32x64", 20243 argLen: 2, 20244 generic: true, 20245 }, 20246 { 20247 name: "Rsh64x8", 20248 argLen: 2, 20249 generic: true, 20250 }, 20251 { 20252 name: "Rsh64x16", 20253 argLen: 2, 20254 generic: true, 20255 }, 20256 { 20257 name: "Rsh64x32", 20258 argLen: 2, 20259 generic: true, 20260 }, 20261 { 20262 name: "Rsh64x64", 20263 argLen: 2, 20264 generic: true, 20265 }, 20266 { 20267 name: "Rsh8Ux8", 20268 argLen: 2, 20269 generic: true, 20270 }, 20271 { 20272 name: "Rsh8Ux16", 20273 argLen: 2, 20274 generic: true, 20275 }, 20276 { 20277 name: "Rsh8Ux32", 20278 argLen: 2, 20279 generic: true, 20280 }, 20281 { 20282 name: "Rsh8Ux64", 20283 argLen: 2, 20284 generic: true, 20285 }, 20286 { 20287 name: "Rsh16Ux8", 20288 argLen: 2, 20289 generic: true, 20290 }, 20291 { 20292 name: "Rsh16Ux16", 20293 argLen: 2, 20294 generic: true, 20295 }, 20296 { 20297 name: "Rsh16Ux32", 20298 argLen: 2, 20299 generic: true, 20300 }, 20301 { 20302 name: "Rsh16Ux64", 20303 argLen: 2, 20304 generic: true, 20305 }, 20306 { 20307 name: "Rsh32Ux8", 20308 argLen: 2, 20309 generic: true, 20310 }, 20311 { 20312 name: "Rsh32Ux16", 20313 argLen: 2, 20314 generic: true, 20315 }, 20316 { 20317 name: "Rsh32Ux32", 20318 argLen: 2, 20319 generic: true, 20320 }, 20321 { 20322 name: "Rsh32Ux64", 20323 argLen: 2, 20324 generic: true, 20325 }, 20326 { 20327 name: "Rsh64Ux8", 20328 argLen: 2, 20329 generic: true, 20330 }, 20331 { 20332 name: "Rsh64Ux16", 20333 argLen: 2, 20334 generic: true, 20335 }, 20336 { 20337 name: "Rsh64Ux32", 20338 argLen: 2, 20339 generic: true, 20340 }, 20341 { 20342 name: "Rsh64Ux64", 20343 argLen: 2, 20344 generic: true, 20345 }, 20346 { 20347 name: "Lrot8", 20348 auxType: auxInt64, 20349 argLen: 1, 20350 generic: true, 20351 }, 20352 { 20353 name: "Lrot16", 20354 auxType: auxInt64, 20355 argLen: 1, 20356 generic: true, 20357 }, 20358 { 20359 name: "Lrot32", 20360 auxType: auxInt64, 20361 argLen: 1, 20362 generic: true, 20363 }, 20364 { 20365 name: "Lrot64", 20366 auxType: auxInt64, 20367 argLen: 1, 20368 generic: true, 20369 }, 20370 { 20371 name: "Eq8", 20372 argLen: 2, 20373 commutative: true, 20374 generic: true, 20375 }, 20376 { 20377 name: "Eq16", 20378 argLen: 2, 20379 commutative: true, 20380 generic: true, 20381 }, 20382 { 20383 name: "Eq32", 20384 argLen: 2, 20385 commutative: true, 20386 generic: true, 20387 }, 20388 { 20389 name: "Eq64", 20390 argLen: 2, 20391 commutative: true, 20392 generic: true, 20393 }, 20394 { 20395 name: "EqPtr", 20396 argLen: 2, 20397 commutative: true, 20398 generic: true, 20399 }, 20400 { 20401 name: "EqInter", 20402 argLen: 2, 20403 generic: true, 20404 }, 20405 { 20406 name: "EqSlice", 20407 argLen: 2, 20408 generic: true, 20409 }, 20410 { 20411 name: "Eq32F", 20412 argLen: 2, 20413 generic: true, 20414 }, 20415 { 20416 name: "Eq64F", 20417 argLen: 2, 20418 generic: true, 20419 }, 20420 { 20421 name: "Neq8", 20422 argLen: 2, 20423 commutative: true, 20424 generic: true, 20425 }, 20426 { 20427 name: "Neq16", 20428 argLen: 2, 20429 commutative: true, 20430 generic: true, 20431 }, 20432 { 20433 name: "Neq32", 20434 argLen: 2, 20435 commutative: true, 20436 generic: true, 20437 }, 20438 { 20439 name: "Neq64", 20440 argLen: 2, 20441 commutative: true, 20442 generic: true, 20443 }, 20444 { 20445 name: "NeqPtr", 20446 argLen: 2, 20447 commutative: true, 20448 generic: true, 20449 }, 20450 { 20451 name: "NeqInter", 20452 argLen: 2, 20453 generic: true, 20454 }, 20455 { 20456 name: "NeqSlice", 20457 argLen: 2, 20458 generic: true, 20459 }, 20460 { 20461 name: "Neq32F", 20462 argLen: 2, 20463 generic: true, 20464 }, 20465 { 20466 name: "Neq64F", 20467 argLen: 2, 20468 generic: true, 20469 }, 20470 { 20471 name: "Less8", 20472 argLen: 2, 20473 generic: true, 20474 }, 20475 { 20476 name: "Less8U", 20477 argLen: 2, 20478 generic: true, 20479 }, 20480 { 20481 name: "Less16", 20482 argLen: 2, 20483 generic: true, 20484 }, 20485 { 20486 name: "Less16U", 20487 argLen: 2, 20488 generic: true, 20489 }, 20490 { 20491 name: "Less32", 20492 argLen: 2, 20493 generic: true, 20494 }, 20495 { 20496 name: "Less32U", 20497 argLen: 2, 20498 generic: true, 20499 }, 20500 { 20501 name: "Less64", 20502 argLen: 2, 20503 generic: true, 20504 }, 20505 { 20506 name: "Less64U", 20507 argLen: 2, 20508 generic: true, 20509 }, 20510 { 20511 name: "Less32F", 20512 argLen: 2, 20513 generic: true, 20514 }, 20515 { 20516 name: "Less64F", 20517 argLen: 2, 20518 generic: true, 20519 }, 20520 { 20521 name: "Leq8", 20522 argLen: 2, 20523 generic: true, 20524 }, 20525 { 20526 name: "Leq8U", 20527 argLen: 2, 20528 generic: true, 20529 }, 20530 { 20531 name: "Leq16", 20532 argLen: 2, 20533 generic: true, 20534 }, 20535 { 20536 name: "Leq16U", 20537 argLen: 2, 20538 generic: true, 20539 }, 20540 { 20541 name: "Leq32", 20542 argLen: 2, 20543 generic: true, 20544 }, 20545 { 20546 name: "Leq32U", 20547 argLen: 2, 20548 generic: true, 20549 }, 20550 { 20551 name: "Leq64", 20552 argLen: 2, 20553 generic: true, 20554 }, 20555 { 20556 name: "Leq64U", 20557 argLen: 2, 20558 generic: true, 20559 }, 20560 { 20561 name: "Leq32F", 20562 argLen: 2, 20563 generic: true, 20564 }, 20565 { 20566 name: "Leq64F", 20567 argLen: 2, 20568 generic: true, 20569 }, 20570 { 20571 name: "Greater8", 20572 argLen: 2, 20573 generic: true, 20574 }, 20575 { 20576 name: "Greater8U", 20577 argLen: 2, 20578 generic: true, 20579 }, 20580 { 20581 name: "Greater16", 20582 argLen: 2, 20583 generic: true, 20584 }, 20585 { 20586 name: "Greater16U", 20587 argLen: 2, 20588 generic: true, 20589 }, 20590 { 20591 name: "Greater32", 20592 argLen: 2, 20593 generic: true, 20594 }, 20595 { 20596 name: "Greater32U", 20597 argLen: 2, 20598 generic: true, 20599 }, 20600 { 20601 name: "Greater64", 20602 argLen: 2, 20603 generic: true, 20604 }, 20605 { 20606 name: "Greater64U", 20607 argLen: 2, 20608 generic: true, 20609 }, 20610 { 20611 name: "Greater32F", 20612 argLen: 2, 20613 generic: true, 20614 }, 20615 { 20616 name: "Greater64F", 20617 argLen: 2, 20618 generic: true, 20619 }, 20620 { 20621 name: "Geq8", 20622 argLen: 2, 20623 generic: true, 20624 }, 20625 { 20626 name: "Geq8U", 20627 argLen: 2, 20628 generic: true, 20629 }, 20630 { 20631 name: "Geq16", 20632 argLen: 2, 20633 generic: true, 20634 }, 20635 { 20636 name: "Geq16U", 20637 argLen: 2, 20638 generic: true, 20639 }, 20640 { 20641 name: "Geq32", 20642 argLen: 2, 20643 generic: true, 20644 }, 20645 { 20646 name: "Geq32U", 20647 argLen: 2, 20648 generic: true, 20649 }, 20650 { 20651 name: "Geq64", 20652 argLen: 2, 20653 generic: true, 20654 }, 20655 { 20656 name: "Geq64U", 20657 argLen: 2, 20658 generic: true, 20659 }, 20660 { 20661 name: "Geq32F", 20662 argLen: 2, 20663 generic: true, 20664 }, 20665 { 20666 name: "Geq64F", 20667 argLen: 2, 20668 generic: true, 20669 }, 20670 { 20671 name: "AndB", 20672 argLen: 2, 20673 generic: true, 20674 }, 20675 { 20676 name: "OrB", 20677 argLen: 2, 20678 generic: true, 20679 }, 20680 { 20681 name: "EqB", 20682 argLen: 2, 20683 generic: true, 20684 }, 20685 { 20686 name: "NeqB", 20687 argLen: 2, 20688 generic: true, 20689 }, 20690 { 20691 name: "Not", 20692 argLen: 1, 20693 generic: true, 20694 }, 20695 { 20696 name: "Neg8", 20697 argLen: 1, 20698 generic: true, 20699 }, 20700 { 20701 name: "Neg16", 20702 argLen: 1, 20703 generic: true, 20704 }, 20705 { 20706 name: "Neg32", 20707 argLen: 1, 20708 generic: true, 20709 }, 20710 { 20711 name: "Neg64", 20712 argLen: 1, 20713 generic: true, 20714 }, 20715 { 20716 name: "Neg32F", 20717 argLen: 1, 20718 generic: true, 20719 }, 20720 { 20721 name: "Neg64F", 20722 argLen: 1, 20723 generic: true, 20724 }, 20725 { 20726 name: "Com8", 20727 argLen: 1, 20728 generic: true, 20729 }, 20730 { 20731 name: "Com16", 20732 argLen: 1, 20733 generic: true, 20734 }, 20735 { 20736 name: "Com32", 20737 argLen: 1, 20738 generic: true, 20739 }, 20740 { 20741 name: "Com64", 20742 argLen: 1, 20743 generic: true, 20744 }, 20745 { 20746 name: "Ctz32", 20747 argLen: 1, 20748 generic: true, 20749 }, 20750 { 20751 name: "Ctz64", 20752 argLen: 1, 20753 generic: true, 20754 }, 20755 { 20756 name: "Bswap32", 20757 argLen: 1, 20758 generic: true, 20759 }, 20760 { 20761 name: "Bswap64", 20762 argLen: 1, 20763 generic: true, 20764 }, 20765 { 20766 name: "Sqrt", 20767 argLen: 1, 20768 generic: true, 20769 }, 20770 { 20771 name: "Phi", 20772 argLen: -1, 20773 generic: true, 20774 }, 20775 { 20776 name: "Copy", 20777 argLen: 1, 20778 generic: true, 20779 }, 20780 { 20781 name: "Convert", 20782 argLen: 2, 20783 generic: true, 20784 }, 20785 { 20786 name: "ConstBool", 20787 auxType: auxBool, 20788 argLen: 0, 20789 generic: true, 20790 }, 20791 { 20792 name: "ConstString", 20793 auxType: auxString, 20794 argLen: 0, 20795 generic: true, 20796 }, 20797 { 20798 name: "ConstNil", 20799 argLen: 0, 20800 generic: true, 20801 }, 20802 { 20803 name: "Const8", 20804 auxType: auxInt8, 20805 argLen: 0, 20806 generic: true, 20807 }, 20808 { 20809 name: "Const16", 20810 auxType: auxInt16, 20811 argLen: 0, 20812 generic: true, 20813 }, 20814 { 20815 name: "Const32", 20816 auxType: auxInt32, 20817 argLen: 0, 20818 generic: true, 20819 }, 20820 { 20821 name: "Const64", 20822 auxType: auxInt64, 20823 argLen: 0, 20824 generic: true, 20825 }, 20826 { 20827 name: "Const32F", 20828 auxType: auxFloat32, 20829 argLen: 0, 20830 generic: true, 20831 }, 20832 { 20833 name: "Const64F", 20834 auxType: auxFloat64, 20835 argLen: 0, 20836 generic: true, 20837 }, 20838 { 20839 name: "ConstInterface", 20840 argLen: 0, 20841 generic: true, 20842 }, 20843 { 20844 name: "ConstSlice", 20845 argLen: 0, 20846 generic: true, 20847 }, 20848 { 20849 name: "InitMem", 20850 argLen: 0, 20851 generic: true, 20852 }, 20853 { 20854 name: "Arg", 20855 auxType: auxSymOff, 20856 argLen: 0, 20857 generic: true, 20858 }, 20859 { 20860 name: "Addr", 20861 auxType: auxSym, 20862 argLen: 1, 20863 generic: true, 20864 }, 20865 { 20866 name: "SP", 20867 argLen: 0, 20868 generic: true, 20869 }, 20870 { 20871 name: "SB", 20872 argLen: 0, 20873 generic: true, 20874 }, 20875 { 20876 name: "Func", 20877 auxType: auxSym, 20878 argLen: 0, 20879 generic: true, 20880 }, 20881 { 20882 name: "Load", 20883 argLen: 2, 20884 generic: true, 20885 }, 20886 { 20887 name: "Store", 20888 auxType: auxInt64, 20889 argLen: 3, 20890 generic: true, 20891 }, 20892 { 20893 name: "Move", 20894 auxType: auxSizeAndAlign, 20895 argLen: 3, 20896 generic: true, 20897 }, 20898 { 20899 name: "Zero", 20900 auxType: auxSizeAndAlign, 20901 argLen: 2, 20902 generic: true, 20903 }, 20904 { 20905 name: "StoreWB", 20906 auxType: auxInt64, 20907 argLen: 3, 20908 generic: true, 20909 }, 20910 { 20911 name: "MoveWB", 20912 auxType: auxSymSizeAndAlign, 20913 argLen: 3, 20914 generic: true, 20915 }, 20916 { 20917 name: "MoveWBVolatile", 20918 auxType: auxSymSizeAndAlign, 20919 argLen: 3, 20920 generic: true, 20921 }, 20922 { 20923 name: "ZeroWB", 20924 auxType: auxSymSizeAndAlign, 20925 argLen: 2, 20926 generic: true, 20927 }, 20928 { 20929 name: "ClosureCall", 20930 auxType: auxInt64, 20931 argLen: 3, 20932 call: true, 20933 generic: true, 20934 }, 20935 { 20936 name: "StaticCall", 20937 auxType: auxSymOff, 20938 argLen: 1, 20939 call: true, 20940 generic: true, 20941 }, 20942 { 20943 name: "DeferCall", 20944 auxType: auxInt64, 20945 argLen: 1, 20946 call: true, 20947 generic: true, 20948 }, 20949 { 20950 name: "GoCall", 20951 auxType: auxInt64, 20952 argLen: 1, 20953 call: true, 20954 generic: true, 20955 }, 20956 { 20957 name: "InterCall", 20958 auxType: auxInt64, 20959 argLen: 2, 20960 call: true, 20961 generic: true, 20962 }, 20963 { 20964 name: "SignExt8to16", 20965 argLen: 1, 20966 generic: true, 20967 }, 20968 { 20969 name: "SignExt8to32", 20970 argLen: 1, 20971 generic: true, 20972 }, 20973 { 20974 name: "SignExt8to64", 20975 argLen: 1, 20976 generic: true, 20977 }, 20978 { 20979 name: "SignExt16to32", 20980 argLen: 1, 20981 generic: true, 20982 }, 20983 { 20984 name: "SignExt16to64", 20985 argLen: 1, 20986 generic: true, 20987 }, 20988 { 20989 name: "SignExt32to64", 20990 argLen: 1, 20991 generic: true, 20992 }, 20993 { 20994 name: "ZeroExt8to16", 20995 argLen: 1, 20996 generic: true, 20997 }, 20998 { 20999 name: "ZeroExt8to32", 21000 argLen: 1, 21001 generic: true, 21002 }, 21003 { 21004 name: "ZeroExt8to64", 21005 argLen: 1, 21006 generic: true, 21007 }, 21008 { 21009 name: "ZeroExt16to32", 21010 argLen: 1, 21011 generic: true, 21012 }, 21013 { 21014 name: "ZeroExt16to64", 21015 argLen: 1, 21016 generic: true, 21017 }, 21018 { 21019 name: "ZeroExt32to64", 21020 argLen: 1, 21021 generic: true, 21022 }, 21023 { 21024 name: "Trunc16to8", 21025 argLen: 1, 21026 generic: true, 21027 }, 21028 { 21029 name: "Trunc32to8", 21030 argLen: 1, 21031 generic: true, 21032 }, 21033 { 21034 name: "Trunc32to16", 21035 argLen: 1, 21036 generic: true, 21037 }, 21038 { 21039 name: "Trunc64to8", 21040 argLen: 1, 21041 generic: true, 21042 }, 21043 { 21044 name: "Trunc64to16", 21045 argLen: 1, 21046 generic: true, 21047 }, 21048 { 21049 name: "Trunc64to32", 21050 argLen: 1, 21051 generic: true, 21052 }, 21053 { 21054 name: "Cvt32to32F", 21055 argLen: 1, 21056 generic: true, 21057 }, 21058 { 21059 name: "Cvt32to64F", 21060 argLen: 1, 21061 generic: true, 21062 }, 21063 { 21064 name: "Cvt64to32F", 21065 argLen: 1, 21066 generic: true, 21067 }, 21068 { 21069 name: "Cvt64to64F", 21070 argLen: 1, 21071 generic: true, 21072 }, 21073 { 21074 name: "Cvt32Fto32", 21075 argLen: 1, 21076 generic: true, 21077 }, 21078 { 21079 name: "Cvt32Fto64", 21080 argLen: 1, 21081 generic: true, 21082 }, 21083 { 21084 name: "Cvt64Fto32", 21085 argLen: 1, 21086 generic: true, 21087 }, 21088 { 21089 name: "Cvt64Fto64", 21090 argLen: 1, 21091 generic: true, 21092 }, 21093 { 21094 name: "Cvt32Fto64F", 21095 argLen: 1, 21096 generic: true, 21097 }, 21098 { 21099 name: "Cvt64Fto32F", 21100 argLen: 1, 21101 generic: true, 21102 }, 21103 { 21104 name: "IsNonNil", 21105 argLen: 1, 21106 generic: true, 21107 }, 21108 { 21109 name: "IsInBounds", 21110 argLen: 2, 21111 generic: true, 21112 }, 21113 { 21114 name: "IsSliceInBounds", 21115 argLen: 2, 21116 generic: true, 21117 }, 21118 { 21119 name: "NilCheck", 21120 argLen: 2, 21121 generic: true, 21122 }, 21123 { 21124 name: "GetG", 21125 argLen: 1, 21126 generic: true, 21127 }, 21128 { 21129 name: "GetClosurePtr", 21130 argLen: 0, 21131 generic: true, 21132 }, 21133 { 21134 name: "PtrIndex", 21135 argLen: 2, 21136 generic: true, 21137 }, 21138 { 21139 name: "OffPtr", 21140 auxType: auxInt64, 21141 argLen: 1, 21142 generic: true, 21143 }, 21144 { 21145 name: "SliceMake", 21146 argLen: 3, 21147 generic: true, 21148 }, 21149 { 21150 name: "SlicePtr", 21151 argLen: 1, 21152 generic: true, 21153 }, 21154 { 21155 name: "SliceLen", 21156 argLen: 1, 21157 generic: true, 21158 }, 21159 { 21160 name: "SliceCap", 21161 argLen: 1, 21162 generic: true, 21163 }, 21164 { 21165 name: "ComplexMake", 21166 argLen: 2, 21167 generic: true, 21168 }, 21169 { 21170 name: "ComplexReal", 21171 argLen: 1, 21172 generic: true, 21173 }, 21174 { 21175 name: "ComplexImag", 21176 argLen: 1, 21177 generic: true, 21178 }, 21179 { 21180 name: "StringMake", 21181 argLen: 2, 21182 generic: true, 21183 }, 21184 { 21185 name: "StringPtr", 21186 argLen: 1, 21187 generic: true, 21188 }, 21189 { 21190 name: "StringLen", 21191 argLen: 1, 21192 generic: true, 21193 }, 21194 { 21195 name: "IMake", 21196 argLen: 2, 21197 generic: true, 21198 }, 21199 { 21200 name: "ITab", 21201 argLen: 1, 21202 generic: true, 21203 }, 21204 { 21205 name: "IData", 21206 argLen: 1, 21207 generic: true, 21208 }, 21209 { 21210 name: "StructMake0", 21211 argLen: 0, 21212 generic: true, 21213 }, 21214 { 21215 name: "StructMake1", 21216 argLen: 1, 21217 generic: true, 21218 }, 21219 { 21220 name: "StructMake2", 21221 argLen: 2, 21222 generic: true, 21223 }, 21224 { 21225 name: "StructMake3", 21226 argLen: 3, 21227 generic: true, 21228 }, 21229 { 21230 name: "StructMake4", 21231 argLen: 4, 21232 generic: true, 21233 }, 21234 { 21235 name: "StructSelect", 21236 auxType: auxInt64, 21237 argLen: 1, 21238 generic: true, 21239 }, 21240 { 21241 name: "ArrayMake0", 21242 argLen: 0, 21243 generic: true, 21244 }, 21245 { 21246 name: "ArrayMake1", 21247 argLen: 1, 21248 generic: true, 21249 }, 21250 { 21251 name: "ArraySelect", 21252 auxType: auxInt64, 21253 argLen: 1, 21254 generic: true, 21255 }, 21256 { 21257 name: "StoreReg", 21258 argLen: 1, 21259 generic: true, 21260 }, 21261 { 21262 name: "LoadReg", 21263 argLen: 1, 21264 generic: true, 21265 }, 21266 { 21267 name: "FwdRef", 21268 auxType: auxSym, 21269 argLen: 0, 21270 generic: true, 21271 }, 21272 { 21273 name: "Unknown", 21274 argLen: 0, 21275 generic: true, 21276 }, 21277 { 21278 name: "VarDef", 21279 auxType: auxSym, 21280 argLen: 1, 21281 generic: true, 21282 }, 21283 { 21284 name: "VarKill", 21285 auxType: auxSym, 21286 argLen: 1, 21287 generic: true, 21288 }, 21289 { 21290 name: "VarLive", 21291 auxType: auxSym, 21292 argLen: 1, 21293 generic: true, 21294 }, 21295 { 21296 name: "KeepAlive", 21297 argLen: 2, 21298 generic: true, 21299 }, 21300 { 21301 name: "Int64Make", 21302 argLen: 2, 21303 generic: true, 21304 }, 21305 { 21306 name: "Int64Hi", 21307 argLen: 1, 21308 generic: true, 21309 }, 21310 { 21311 name: "Int64Lo", 21312 argLen: 1, 21313 generic: true, 21314 }, 21315 { 21316 name: "Add32carry", 21317 argLen: 2, 21318 commutative: true, 21319 generic: true, 21320 }, 21321 { 21322 name: "Add32withcarry", 21323 argLen: 3, 21324 commutative: true, 21325 generic: true, 21326 }, 21327 { 21328 name: "Sub32carry", 21329 argLen: 2, 21330 generic: true, 21331 }, 21332 { 21333 name: "Sub32withcarry", 21334 argLen: 3, 21335 generic: true, 21336 }, 21337 { 21338 name: "Signmask", 21339 argLen: 1, 21340 generic: true, 21341 }, 21342 { 21343 name: "Zeromask", 21344 argLen: 1, 21345 generic: true, 21346 }, 21347 { 21348 name: "Slicemask", 21349 argLen: 1, 21350 generic: true, 21351 }, 21352 { 21353 name: "Cvt32Uto32F", 21354 argLen: 1, 21355 generic: true, 21356 }, 21357 { 21358 name: "Cvt32Uto64F", 21359 argLen: 1, 21360 generic: true, 21361 }, 21362 { 21363 name: "Cvt32Fto32U", 21364 argLen: 1, 21365 generic: true, 21366 }, 21367 { 21368 name: "Cvt64Fto32U", 21369 argLen: 1, 21370 generic: true, 21371 }, 21372 { 21373 name: "Cvt64Uto32F", 21374 argLen: 1, 21375 generic: true, 21376 }, 21377 { 21378 name: "Cvt64Uto64F", 21379 argLen: 1, 21380 generic: true, 21381 }, 21382 { 21383 name: "Cvt32Fto64U", 21384 argLen: 1, 21385 generic: true, 21386 }, 21387 { 21388 name: "Cvt64Fto64U", 21389 argLen: 1, 21390 generic: true, 21391 }, 21392 { 21393 name: "Select0", 21394 argLen: 1, 21395 generic: true, 21396 }, 21397 { 21398 name: "Select1", 21399 argLen: 1, 21400 generic: true, 21401 }, 21402 { 21403 name: "AtomicLoad32", 21404 argLen: 2, 21405 generic: true, 21406 }, 21407 { 21408 name: "AtomicLoad64", 21409 argLen: 2, 21410 generic: true, 21411 }, 21412 { 21413 name: "AtomicLoadPtr", 21414 argLen: 2, 21415 generic: true, 21416 }, 21417 { 21418 name: "AtomicStore32", 21419 argLen: 3, 21420 generic: true, 21421 }, 21422 { 21423 name: "AtomicStore64", 21424 argLen: 3, 21425 generic: true, 21426 }, 21427 { 21428 name: "AtomicStorePtrNoWB", 21429 argLen: 3, 21430 generic: true, 21431 }, 21432 { 21433 name: "AtomicExchange32", 21434 argLen: 3, 21435 generic: true, 21436 }, 21437 { 21438 name: "AtomicExchange64", 21439 argLen: 3, 21440 generic: true, 21441 }, 21442 { 21443 name: "AtomicAdd32", 21444 argLen: 3, 21445 generic: true, 21446 }, 21447 { 21448 name: "AtomicAdd64", 21449 argLen: 3, 21450 generic: true, 21451 }, 21452 { 21453 name: "AtomicCompareAndSwap32", 21454 argLen: 4, 21455 generic: true, 21456 }, 21457 { 21458 name: "AtomicCompareAndSwap64", 21459 argLen: 4, 21460 generic: true, 21461 }, 21462 { 21463 name: "AtomicAnd8", 21464 argLen: 3, 21465 generic: true, 21466 }, 21467 { 21468 name: "AtomicOr8", 21469 argLen: 3, 21470 generic: true, 21471 }, 21472 } 21473 21474 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 21475 func (o Op) String() string { return opcodeTable[o].name } 21476 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 21477 21478 var registers386 = [...]Register{ 21479 {0, x86.REG_AX, "AX"}, 21480 {1, x86.REG_CX, "CX"}, 21481 {2, x86.REG_DX, "DX"}, 21482 {3, x86.REG_BX, "BX"}, 21483 {4, x86.REGSP, "SP"}, 21484 {5, x86.REG_BP, "BP"}, 21485 {6, x86.REG_SI, "SI"}, 21486 {7, x86.REG_DI, "DI"}, 21487 {8, x86.REG_X0, "X0"}, 21488 {9, x86.REG_X1, "X1"}, 21489 {10, x86.REG_X2, "X2"}, 21490 {11, x86.REG_X3, "X3"}, 21491 {12, x86.REG_X4, "X4"}, 21492 {13, x86.REG_X5, "X5"}, 21493 {14, x86.REG_X6, "X6"}, 21494 {15, x86.REG_X7, "X7"}, 21495 {16, 0, "SB"}, 21496 } 21497 var gpRegMask386 = regMask(239) 21498 var fpRegMask386 = regMask(65280) 21499 var specialRegMask386 = regMask(0) 21500 var framepointerReg386 = int8(5) 21501 var linkReg386 = int8(-1) 21502 var registersAMD64 = [...]Register{ 21503 {0, x86.REG_AX, "AX"}, 21504 {1, x86.REG_CX, "CX"}, 21505 {2, x86.REG_DX, "DX"}, 21506 {3, x86.REG_BX, "BX"}, 21507 {4, x86.REGSP, "SP"}, 21508 {5, x86.REG_BP, "BP"}, 21509 {6, x86.REG_SI, "SI"}, 21510 {7, x86.REG_DI, "DI"}, 21511 {8, x86.REG_R8, "R8"}, 21512 {9, x86.REG_R9, "R9"}, 21513 {10, x86.REG_R10, "R10"}, 21514 {11, x86.REG_R11, "R11"}, 21515 {12, x86.REG_R12, "R12"}, 21516 {13, x86.REG_R13, "R13"}, 21517 {14, x86.REG_R14, "R14"}, 21518 {15, x86.REG_R15, "R15"}, 21519 {16, x86.REG_X0, "X0"}, 21520 {17, x86.REG_X1, "X1"}, 21521 {18, x86.REG_X2, "X2"}, 21522 {19, x86.REG_X3, "X3"}, 21523 {20, x86.REG_X4, "X4"}, 21524 {21, x86.REG_X5, "X5"}, 21525 {22, x86.REG_X6, "X6"}, 21526 {23, x86.REG_X7, "X7"}, 21527 {24, x86.REG_X8, "X8"}, 21528 {25, x86.REG_X9, "X9"}, 21529 {26, x86.REG_X10, "X10"}, 21530 {27, x86.REG_X11, "X11"}, 21531 {28, x86.REG_X12, "X12"}, 21532 {29, x86.REG_X13, "X13"}, 21533 {30, x86.REG_X14, "X14"}, 21534 {31, x86.REG_X15, "X15"}, 21535 {32, 0, "SB"}, 21536 } 21537 var gpRegMaskAMD64 = regMask(65519) 21538 var fpRegMaskAMD64 = regMask(4294901760) 21539 var specialRegMaskAMD64 = regMask(0) 21540 var framepointerRegAMD64 = int8(5) 21541 var linkRegAMD64 = int8(-1) 21542 var registersARM = [...]Register{ 21543 {0, arm.REG_R0, "R0"}, 21544 {1, arm.REG_R1, "R1"}, 21545 {2, arm.REG_R2, "R2"}, 21546 {3, arm.REG_R3, "R3"}, 21547 {4, arm.REG_R4, "R4"}, 21548 {5, arm.REG_R5, "R5"}, 21549 {6, arm.REG_R6, "R6"}, 21550 {7, arm.REG_R7, "R7"}, 21551 {8, arm.REG_R8, "R8"}, 21552 {9, arm.REG_R9, "R9"}, 21553 {10, arm.REGG, "g"}, 21554 {11, arm.REG_R11, "R11"}, 21555 {12, arm.REG_R12, "R12"}, 21556 {13, arm.REGSP, "SP"}, 21557 {14, arm.REG_R14, "R14"}, 21558 {15, arm.REG_R15, "R15"}, 21559 {16, arm.REG_F0, "F0"}, 21560 {17, arm.REG_F1, "F1"}, 21561 {18, arm.REG_F2, "F2"}, 21562 {19, arm.REG_F3, "F3"}, 21563 {20, arm.REG_F4, "F4"}, 21564 {21, arm.REG_F5, "F5"}, 21565 {22, arm.REG_F6, "F6"}, 21566 {23, arm.REG_F7, "F7"}, 21567 {24, arm.REG_F8, "F8"}, 21568 {25, arm.REG_F9, "F9"}, 21569 {26, arm.REG_F10, "F10"}, 21570 {27, arm.REG_F11, "F11"}, 21571 {28, arm.REG_F12, "F12"}, 21572 {29, arm.REG_F13, "F13"}, 21573 {30, arm.REG_F14, "F14"}, 21574 {31, arm.REG_F15, "F15"}, 21575 {32, 0, "SB"}, 21576 } 21577 var gpRegMaskARM = regMask(21503) 21578 var fpRegMaskARM = regMask(4294901760) 21579 var specialRegMaskARM = regMask(0) 21580 var framepointerRegARM = int8(-1) 21581 var linkRegARM = int8(14) 21582 var registersARM64 = [...]Register{ 21583 {0, arm64.REG_R0, "R0"}, 21584 {1, arm64.REG_R1, "R1"}, 21585 {2, arm64.REG_R2, "R2"}, 21586 {3, arm64.REG_R3, "R3"}, 21587 {4, arm64.REG_R4, "R4"}, 21588 {5, arm64.REG_R5, "R5"}, 21589 {6, arm64.REG_R6, "R6"}, 21590 {7, arm64.REG_R7, "R7"}, 21591 {8, arm64.REG_R8, "R8"}, 21592 {9, arm64.REG_R9, "R9"}, 21593 {10, arm64.REG_R10, "R10"}, 21594 {11, arm64.REG_R11, "R11"}, 21595 {12, arm64.REG_R12, "R12"}, 21596 {13, arm64.REG_R13, "R13"}, 21597 {14, arm64.REG_R14, "R14"}, 21598 {15, arm64.REG_R15, "R15"}, 21599 {16, arm64.REG_R16, "R16"}, 21600 {17, arm64.REG_R17, "R17"}, 21601 {18, arm64.REG_R18, "R18"}, 21602 {19, arm64.REG_R19, "R19"}, 21603 {20, arm64.REG_R20, "R20"}, 21604 {21, arm64.REG_R21, "R21"}, 21605 {22, arm64.REG_R22, "R22"}, 21606 {23, arm64.REG_R23, "R23"}, 21607 {24, arm64.REG_R24, "R24"}, 21608 {25, arm64.REG_R25, "R25"}, 21609 {26, arm64.REG_R26, "R26"}, 21610 {27, arm64.REGG, "g"}, 21611 {28, arm64.REG_R29, "R29"}, 21612 {29, arm64.REG_R30, "R30"}, 21613 {30, arm64.REGSP, "SP"}, 21614 {31, arm64.REG_F0, "F0"}, 21615 {32, arm64.REG_F1, "F1"}, 21616 {33, arm64.REG_F2, "F2"}, 21617 {34, arm64.REG_F3, "F3"}, 21618 {35, arm64.REG_F4, "F4"}, 21619 {36, arm64.REG_F5, "F5"}, 21620 {37, arm64.REG_F6, "F6"}, 21621 {38, arm64.REG_F7, "F7"}, 21622 {39, arm64.REG_F8, "F8"}, 21623 {40, arm64.REG_F9, "F9"}, 21624 {41, arm64.REG_F10, "F10"}, 21625 {42, arm64.REG_F11, "F11"}, 21626 {43, arm64.REG_F12, "F12"}, 21627 {44, arm64.REG_F13, "F13"}, 21628 {45, arm64.REG_F14, "F14"}, 21629 {46, arm64.REG_F15, "F15"}, 21630 {47, arm64.REG_F16, "F16"}, 21631 {48, arm64.REG_F17, "F17"}, 21632 {49, arm64.REG_F18, "F18"}, 21633 {50, arm64.REG_F19, "F19"}, 21634 {51, arm64.REG_F20, "F20"}, 21635 {52, arm64.REG_F21, "F21"}, 21636 {53, arm64.REG_F22, "F22"}, 21637 {54, arm64.REG_F23, "F23"}, 21638 {55, arm64.REG_F24, "F24"}, 21639 {56, arm64.REG_F25, "F25"}, 21640 {57, arm64.REG_F26, "F26"}, 21641 {58, arm64.REG_F27, "F27"}, 21642 {59, arm64.REG_F28, "F28"}, 21643 {60, arm64.REG_F29, "F29"}, 21644 {61, arm64.REG_F30, "F30"}, 21645 {62, arm64.REG_F31, "F31"}, 21646 {63, 0, "SB"}, 21647 } 21648 var gpRegMaskARM64 = regMask(670826495) 21649 var fpRegMaskARM64 = regMask(9223372034707292160) 21650 var specialRegMaskARM64 = regMask(0) 21651 var framepointerRegARM64 = int8(-1) 21652 var linkRegARM64 = int8(29) 21653 var registersMIPS = [...]Register{ 21654 {0, mips.REG_R0, "R0"}, 21655 {1, mips.REG_R1, "R1"}, 21656 {2, mips.REG_R2, "R2"}, 21657 {3, mips.REG_R3, "R3"}, 21658 {4, mips.REG_R4, "R4"}, 21659 {5, mips.REG_R5, "R5"}, 21660 {6, mips.REG_R6, "R6"}, 21661 {7, mips.REG_R7, "R7"}, 21662 {8, mips.REG_R8, "R8"}, 21663 {9, mips.REG_R9, "R9"}, 21664 {10, mips.REG_R10, "R10"}, 21665 {11, mips.REG_R11, "R11"}, 21666 {12, mips.REG_R12, "R12"}, 21667 {13, mips.REG_R13, "R13"}, 21668 {14, mips.REG_R14, "R14"}, 21669 {15, mips.REG_R15, "R15"}, 21670 {16, mips.REG_R16, "R16"}, 21671 {17, mips.REG_R17, "R17"}, 21672 {18, mips.REG_R18, "R18"}, 21673 {19, mips.REG_R19, "R19"}, 21674 {20, mips.REG_R20, "R20"}, 21675 {21, mips.REG_R21, "R21"}, 21676 {22, mips.REG_R22, "R22"}, 21677 {23, mips.REG_R24, "R24"}, 21678 {24, mips.REG_R25, "R25"}, 21679 {25, mips.REG_R28, "R28"}, 21680 {26, mips.REGSP, "SP"}, 21681 {27, mips.REGG, "g"}, 21682 {28, mips.REG_R31, "R31"}, 21683 {29, mips.REG_F0, "F0"}, 21684 {30, mips.REG_F2, "F2"}, 21685 {31, mips.REG_F4, "F4"}, 21686 {32, mips.REG_F6, "F6"}, 21687 {33, mips.REG_F8, "F8"}, 21688 {34, mips.REG_F10, "F10"}, 21689 {35, mips.REG_F12, "F12"}, 21690 {36, mips.REG_F14, "F14"}, 21691 {37, mips.REG_F16, "F16"}, 21692 {38, mips.REG_F18, "F18"}, 21693 {39, mips.REG_F20, "F20"}, 21694 {40, mips.REG_F22, "F22"}, 21695 {41, mips.REG_F24, "F24"}, 21696 {42, mips.REG_F26, "F26"}, 21697 {43, mips.REG_F28, "F28"}, 21698 {44, mips.REG_F30, "F30"}, 21699 {45, mips.REG_HI, "HI"}, 21700 {46, mips.REG_LO, "LO"}, 21701 {47, 0, "SB"}, 21702 } 21703 var gpRegMaskMIPS = regMask(335544318) 21704 var fpRegMaskMIPS = regMask(35183835217920) 21705 var specialRegMaskMIPS = regMask(105553116266496) 21706 var framepointerRegMIPS = int8(-1) 21707 var linkRegMIPS = int8(28) 21708 var registersMIPS64 = [...]Register{ 21709 {0, mips.REG_R0, "R0"}, 21710 {1, mips.REG_R1, "R1"}, 21711 {2, mips.REG_R2, "R2"}, 21712 {3, mips.REG_R3, "R3"}, 21713 {4, mips.REG_R4, "R4"}, 21714 {5, mips.REG_R5, "R5"}, 21715 {6, mips.REG_R6, "R6"}, 21716 {7, mips.REG_R7, "R7"}, 21717 {8, mips.REG_R8, "R8"}, 21718 {9, mips.REG_R9, "R9"}, 21719 {10, mips.REG_R10, "R10"}, 21720 {11, mips.REG_R11, "R11"}, 21721 {12, mips.REG_R12, "R12"}, 21722 {13, mips.REG_R13, "R13"}, 21723 {14, mips.REG_R14, "R14"}, 21724 {15, mips.REG_R15, "R15"}, 21725 {16, mips.REG_R16, "R16"}, 21726 {17, mips.REG_R17, "R17"}, 21727 {18, mips.REG_R18, "R18"}, 21728 {19, mips.REG_R19, "R19"}, 21729 {20, mips.REG_R20, "R20"}, 21730 {21, mips.REG_R21, "R21"}, 21731 {22, mips.REG_R22, "R22"}, 21732 {23, mips.REG_R24, "R24"}, 21733 {24, mips.REG_R25, "R25"}, 21734 {25, mips.REGSP, "SP"}, 21735 {26, mips.REGG, "g"}, 21736 {27, mips.REG_R31, "R31"}, 21737 {28, mips.REG_F0, "F0"}, 21738 {29, mips.REG_F1, "F1"}, 21739 {30, mips.REG_F2, "F2"}, 21740 {31, mips.REG_F3, "F3"}, 21741 {32, mips.REG_F4, "F4"}, 21742 {33, mips.REG_F5, "F5"}, 21743 {34, mips.REG_F6, "F6"}, 21744 {35, mips.REG_F7, "F7"}, 21745 {36, mips.REG_F8, "F8"}, 21746 {37, mips.REG_F9, "F9"}, 21747 {38, mips.REG_F10, "F10"}, 21748 {39, mips.REG_F11, "F11"}, 21749 {40, mips.REG_F12, "F12"}, 21750 {41, mips.REG_F13, "F13"}, 21751 {42, mips.REG_F14, "F14"}, 21752 {43, mips.REG_F15, "F15"}, 21753 {44, mips.REG_F16, "F16"}, 21754 {45, mips.REG_F17, "F17"}, 21755 {46, mips.REG_F18, "F18"}, 21756 {47, mips.REG_F19, "F19"}, 21757 {48, mips.REG_F20, "F20"}, 21758 {49, mips.REG_F21, "F21"}, 21759 {50, mips.REG_F22, "F22"}, 21760 {51, mips.REG_F23, "F23"}, 21761 {52, mips.REG_F24, "F24"}, 21762 {53, mips.REG_F25, "F25"}, 21763 {54, mips.REG_F26, "F26"}, 21764 {55, mips.REG_F27, "F27"}, 21765 {56, mips.REG_F28, "F28"}, 21766 {57, mips.REG_F29, "F29"}, 21767 {58, mips.REG_F30, "F30"}, 21768 {59, mips.REG_F31, "F31"}, 21769 {60, mips.REG_HI, "HI"}, 21770 {61, mips.REG_LO, "LO"}, 21771 {62, 0, "SB"}, 21772 } 21773 var gpRegMaskMIPS64 = regMask(167772158) 21774 var fpRegMaskMIPS64 = regMask(1152921504338411520) 21775 var specialRegMaskMIPS64 = regMask(3458764513820540928) 21776 var framepointerRegMIPS64 = int8(-1) 21777 var linkRegMIPS64 = int8(27) 21778 var registersPPC64 = [...]Register{ 21779 {0, ppc64.REG_R0, "R0"}, 21780 {1, ppc64.REGSP, "SP"}, 21781 {2, 0, "SB"}, 21782 {3, ppc64.REG_R3, "R3"}, 21783 {4, ppc64.REG_R4, "R4"}, 21784 {5, ppc64.REG_R5, "R5"}, 21785 {6, ppc64.REG_R6, "R6"}, 21786 {7, ppc64.REG_R7, "R7"}, 21787 {8, ppc64.REG_R8, "R8"}, 21788 {9, ppc64.REG_R9, "R9"}, 21789 {10, ppc64.REG_R10, "R10"}, 21790 {11, ppc64.REG_R11, "R11"}, 21791 {12, ppc64.REG_R12, "R12"}, 21792 {13, ppc64.REG_R13, "R13"}, 21793 {14, ppc64.REG_R14, "R14"}, 21794 {15, ppc64.REG_R15, "R15"}, 21795 {16, ppc64.REG_R16, "R16"}, 21796 {17, ppc64.REG_R17, "R17"}, 21797 {18, ppc64.REG_R18, "R18"}, 21798 {19, ppc64.REG_R19, "R19"}, 21799 {20, ppc64.REG_R20, "R20"}, 21800 {21, ppc64.REG_R21, "R21"}, 21801 {22, ppc64.REG_R22, "R22"}, 21802 {23, ppc64.REG_R23, "R23"}, 21803 {24, ppc64.REG_R24, "R24"}, 21804 {25, ppc64.REG_R25, "R25"}, 21805 {26, ppc64.REG_R26, "R26"}, 21806 {27, ppc64.REG_R27, "R27"}, 21807 {28, ppc64.REG_R28, "R28"}, 21808 {29, ppc64.REG_R29, "R29"}, 21809 {30, ppc64.REGG, "g"}, 21810 {31, ppc64.REG_R31, "R31"}, 21811 {32, ppc64.REG_F0, "F0"}, 21812 {33, ppc64.REG_F1, "F1"}, 21813 {34, ppc64.REG_F2, "F2"}, 21814 {35, ppc64.REG_F3, "F3"}, 21815 {36, ppc64.REG_F4, "F4"}, 21816 {37, ppc64.REG_F5, "F5"}, 21817 {38, ppc64.REG_F6, "F6"}, 21818 {39, ppc64.REG_F7, "F7"}, 21819 {40, ppc64.REG_F8, "F8"}, 21820 {41, ppc64.REG_F9, "F9"}, 21821 {42, ppc64.REG_F10, "F10"}, 21822 {43, ppc64.REG_F11, "F11"}, 21823 {44, ppc64.REG_F12, "F12"}, 21824 {45, ppc64.REG_F13, "F13"}, 21825 {46, ppc64.REG_F14, "F14"}, 21826 {47, ppc64.REG_F15, "F15"}, 21827 {48, ppc64.REG_F16, "F16"}, 21828 {49, ppc64.REG_F17, "F17"}, 21829 {50, ppc64.REG_F18, "F18"}, 21830 {51, ppc64.REG_F19, "F19"}, 21831 {52, ppc64.REG_F20, "F20"}, 21832 {53, ppc64.REG_F21, "F21"}, 21833 {54, ppc64.REG_F22, "F22"}, 21834 {55, ppc64.REG_F23, "F23"}, 21835 {56, ppc64.REG_F24, "F24"}, 21836 {57, ppc64.REG_F25, "F25"}, 21837 {58, ppc64.REG_F26, "F26"}, 21838 {59, ppc64.REG_F27, "F27"}, 21839 {60, ppc64.REG_F28, "F28"}, 21840 {61, ppc64.REG_F29, "F29"}, 21841 {62, ppc64.REG_F30, "F30"}, 21842 {63, ppc64.REG_F31, "F31"}, 21843 } 21844 var gpRegMaskPPC64 = regMask(1073733624) 21845 var fpRegMaskPPC64 = regMask(576460743713488896) 21846 var specialRegMaskPPC64 = regMask(0) 21847 var framepointerRegPPC64 = int8(1) 21848 var linkRegPPC64 = int8(-1) 21849 var registersS390X = [...]Register{ 21850 {0, s390x.REG_R0, "R0"}, 21851 {1, s390x.REG_R1, "R1"}, 21852 {2, s390x.REG_R2, "R2"}, 21853 {3, s390x.REG_R3, "R3"}, 21854 {4, s390x.REG_R4, "R4"}, 21855 {5, s390x.REG_R5, "R5"}, 21856 {6, s390x.REG_R6, "R6"}, 21857 {7, s390x.REG_R7, "R7"}, 21858 {8, s390x.REG_R8, "R8"}, 21859 {9, s390x.REG_R9, "R9"}, 21860 {10, s390x.REG_R10, "R10"}, 21861 {11, s390x.REG_R11, "R11"}, 21862 {12, s390x.REG_R12, "R12"}, 21863 {13, s390x.REGG, "g"}, 21864 {14, s390x.REG_R14, "R14"}, 21865 {15, s390x.REGSP, "SP"}, 21866 {16, s390x.REG_F0, "F0"}, 21867 {17, s390x.REG_F1, "F1"}, 21868 {18, s390x.REG_F2, "F2"}, 21869 {19, s390x.REG_F3, "F3"}, 21870 {20, s390x.REG_F4, "F4"}, 21871 {21, s390x.REG_F5, "F5"}, 21872 {22, s390x.REG_F6, "F6"}, 21873 {23, s390x.REG_F7, "F7"}, 21874 {24, s390x.REG_F8, "F8"}, 21875 {25, s390x.REG_F9, "F9"}, 21876 {26, s390x.REG_F10, "F10"}, 21877 {27, s390x.REG_F11, "F11"}, 21878 {28, s390x.REG_F12, "F12"}, 21879 {29, s390x.REG_F13, "F13"}, 21880 {30, s390x.REG_F14, "F14"}, 21881 {31, s390x.REG_F15, "F15"}, 21882 {32, 0, "SB"}, 21883 } 21884 var gpRegMaskS390X = regMask(21503) 21885 var fpRegMaskS390X = regMask(4294901760) 21886 var specialRegMaskS390X = regMask(0) 21887 var framepointerRegS390X = int8(-1) 21888 var linkRegS390X = int8(14) 21889
