1 /* tc-bfin.c -- Assembler for the ADI Blackfin. 2 Copyright (C) 2005-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "struc-symbol.h" 23 #include "bfin-defs.h" 24 #include "obstack.h" 25 #include "safe-ctype.h" 26 #ifdef OBJ_ELF 27 #include "dwarf2dbg.h" 28 #endif 29 #include "libbfd.h" 30 #include "elf/common.h" 31 #include "elf/bfin.h" 32 33 extern int yyparse (void); 34 struct yy_buffer_state; 35 typedef struct yy_buffer_state *YY_BUFFER_STATE; 36 extern YY_BUFFER_STATE yy_scan_string (const char *yy_str); 37 extern void yy_delete_buffer (YY_BUFFER_STATE b); 38 static parse_state parse (char *line); 39 40 /* Global variables. */ 41 struct bfin_insn *insn; 42 int last_insn_size; 43 44 extern struct obstack mempool; 45 FILE *errorf; 46 47 /* Flags to set in the elf header */ 48 #define DEFAULT_FLAGS 0 49 50 #ifdef OBJ_FDPIC_ELF 51 # define DEFAULT_FDPIC EF_BFIN_FDPIC 52 #else 53 # define DEFAULT_FDPIC 0 54 #endif 55 56 static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC; 57 static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0; 58 59 /* Blackfin specific function to handle FD-PIC pointer initializations. */ 60 61 static void 62 bfin_pic_ptr (int nbytes) 63 { 64 expressionS exp; 65 char *p; 66 67 if (nbytes != 4) 68 abort (); 69 70 #ifdef md_flush_pending_output 71 md_flush_pending_output (); 72 #endif 73 74 if (is_it_end_of_statement ()) 75 { 76 demand_empty_rest_of_line (); 77 return; 78 } 79 80 #ifdef md_cons_align 81 md_cons_align (nbytes); 82 #endif 83 84 do 85 { 86 bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC; 87 88 if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0) 89 { 90 input_line_pointer += 9; 91 expression (&exp); 92 if (*input_line_pointer == ')') 93 input_line_pointer++; 94 else 95 as_bad (_("missing ')'")); 96 } 97 else 98 error ("missing funcdesc in picptr"); 99 100 p = frag_more (4); 101 memset (p, 0, 4); 102 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0, 103 reloc_type); 104 } 105 while (*input_line_pointer++ == ','); 106 107 input_line_pointer--; /* Put terminator back into stream. */ 108 demand_empty_rest_of_line (); 109 } 110 111 static void 112 bfin_s_bss (int ignore ATTRIBUTE_UNUSED) 113 { 114 int temp; 115 116 temp = get_absolute_expression (); 117 subseg_set (bss_section, (subsegT) temp); 118 demand_empty_rest_of_line (); 119 } 120 121 const pseudo_typeS md_pseudo_table[] = { 122 {"align", s_align_bytes, 0}, 123 {"byte2", cons, 2}, 124 {"byte4", cons, 4}, 125 {"picptr", bfin_pic_ptr, 4}, 126 {"code", obj_elf_section, 0}, 127 {"db", cons, 1}, 128 {"dd", cons, 4}, 129 {"dw", cons, 2}, 130 {"p", s_ignore, 0}, 131 {"pdata", s_ignore, 0}, 132 {"var", s_ignore, 0}, 133 {"bss", bfin_s_bss, 0}, 134 {0, 0, 0} 135 }; 136 137 /* Characters that are used to denote comments and line separators. */ 138 const char comment_chars[] = "#"; 139 const char line_comment_chars[] = "#"; 140 const char line_separator_chars[] = ";"; 141 142 /* Characters that can be used to separate the mantissa from the 143 exponent in floating point numbers. */ 144 const char EXP_CHARS[] = "eE"; 145 146 /* Characters that mean this number is a floating point constant. 147 As in 0f12.456 or 0d1.2345e12. */ 148 const char FLT_CHARS[] = "fFdDxX"; 149 150 typedef enum bfin_cpu_type 151 { 152 BFIN_CPU_UNKNOWN, 153 BFIN_CPU_BF504, 154 BFIN_CPU_BF506, 155 BFIN_CPU_BF512, 156 BFIN_CPU_BF514, 157 BFIN_CPU_BF516, 158 BFIN_CPU_BF518, 159 BFIN_CPU_BF522, 160 BFIN_CPU_BF523, 161 BFIN_CPU_BF524, 162 BFIN_CPU_BF525, 163 BFIN_CPU_BF526, 164 BFIN_CPU_BF527, 165 BFIN_CPU_BF531, 166 BFIN_CPU_BF532, 167 BFIN_CPU_BF533, 168 BFIN_CPU_BF534, 169 BFIN_CPU_BF536, 170 BFIN_CPU_BF537, 171 BFIN_CPU_BF538, 172 BFIN_CPU_BF539, 173 BFIN_CPU_BF542, 174 BFIN_CPU_BF542M, 175 BFIN_CPU_BF544, 176 BFIN_CPU_BF544M, 177 BFIN_CPU_BF547, 178 BFIN_CPU_BF547M, 179 BFIN_CPU_BF548, 180 BFIN_CPU_BF548M, 181 BFIN_CPU_BF549, 182 BFIN_CPU_BF549M, 183 BFIN_CPU_BF561, 184 BFIN_CPU_BF592, 185 } bfin_cpu_t; 186 187 bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN; 188 /* -msi-revision support. There are three special values: 189 -1 -msi-revision=none. 190 0xffff -msi-revision=any. */ 191 int bfin_si_revision; 192 193 unsigned int bfin_anomaly_checks = 0; 194 195 struct bfin_cpu 196 { 197 const char *name; 198 bfin_cpu_t type; 199 int si_revision; 200 unsigned int anomaly_checks; 201 }; 202 203 struct bfin_cpu bfin_cpus[] = 204 { 205 {"bf504", BFIN_CPU_BF504, 0x0000, AC_05000074}, 206 207 {"bf506", BFIN_CPU_BF506, 0x0000, AC_05000074}, 208 209 {"bf512", BFIN_CPU_BF512, 0x0002, AC_05000074}, 210 {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074}, 211 {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074}, 212 213 {"bf514", BFIN_CPU_BF514, 0x0002, AC_05000074}, 214 {"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074}, 215 {"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074}, 216 217 {"bf516", BFIN_CPU_BF516, 0x0002, AC_05000074}, 218 {"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074}, 219 {"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074}, 220 221 {"bf518", BFIN_CPU_BF518, 0x0002, AC_05000074}, 222 {"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074}, 223 {"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074}, 224 225 {"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074}, 226 {"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074}, 227 {"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074}, 228 229 {"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074}, 230 {"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074}, 231 {"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074}, 232 233 {"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074}, 234 {"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074}, 235 {"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074}, 236 237 {"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074}, 238 {"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074}, 239 {"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074}, 240 241 {"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074}, 242 {"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074}, 243 {"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074}, 244 245 {"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074}, 246 {"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074}, 247 {"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074}, 248 249 {"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074}, 250 {"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074}, 251 {"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074}, 252 {"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074}, 253 254 {"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074}, 255 {"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074}, 256 {"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074}, 257 {"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074}, 258 259 {"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074}, 260 {"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074}, 261 {"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074}, 262 {"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074}, 263 264 {"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074}, 265 {"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074}, 266 {"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074}, 267 268 {"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074}, 269 {"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074}, 270 {"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074}, 271 272 {"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074}, 273 {"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074}, 274 {"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074}, 275 276 {"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074}, 277 {"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074}, 278 {"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074}, 279 {"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074}, 280 281 {"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074}, 282 {"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074}, 283 {"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074}, 284 {"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074}, 285 286 {"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074}, 287 288 {"bf542", BFIN_CPU_BF542, 0x0004, AC_05000074}, 289 {"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074}, 290 {"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074}, 291 {"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074}, 292 293 {"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074}, 294 295 {"bf544", BFIN_CPU_BF544, 0x0004, AC_05000074}, 296 {"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074}, 297 {"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074}, 298 {"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074}, 299 300 {"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074}, 301 302 {"bf547", BFIN_CPU_BF547, 0x0004, AC_05000074}, 303 {"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074}, 304 {"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074}, 305 {"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074}, 306 307 {"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074}, 308 309 {"bf548", BFIN_CPU_BF548, 0x0004, AC_05000074}, 310 {"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074}, 311 {"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074}, 312 {"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074}, 313 314 {"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074}, 315 316 {"bf549", BFIN_CPU_BF549, 0x0004, AC_05000074}, 317 {"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074}, 318 {"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074}, 319 {"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074}, 320 321 {"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074}, 322 {"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074}, 323 {"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074}, 324 325 {"bf592", BFIN_CPU_BF592, 0x0001, AC_05000074}, 326 {"bf592", BFIN_CPU_BF592, 0x0000, AC_05000074}, 327 328 {NULL, 0, 0, 0} 329 }; 330 331 /* Define bfin-specific command-line options (there are none). */ 332 const char *md_shortopts = ""; 333 334 #define OPTION_FDPIC (OPTION_MD_BASE) 335 #define OPTION_NOPIC (OPTION_MD_BASE + 1) 336 #define OPTION_MCPU (OPTION_MD_BASE + 2) 337 338 struct option md_longopts[] = 339 { 340 { "mcpu", required_argument, NULL, OPTION_MCPU }, 341 { "mfdpic", no_argument, NULL, OPTION_FDPIC }, 342 { "mnopic", no_argument, NULL, OPTION_NOPIC }, 343 { "mno-fdpic", no_argument, NULL, OPTION_NOPIC }, 344 { NULL, no_argument, NULL, 0 }, 345 }; 346 347 size_t md_longopts_size = sizeof (md_longopts); 348 349 350 int 351 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) 352 { 353 switch (c) 354 { 355 default: 356 return 0; 357 358 case OPTION_MCPU: 359 { 360 const char *p, *q; 361 int i; 362 363 i = 0; 364 while ((p = bfin_cpus[i].name) != NULL) 365 { 366 if (strncmp (arg, p, strlen (p)) == 0) 367 break; 368 i++; 369 } 370 371 if (p == NULL) 372 as_fatal ("-mcpu=%s is not valid", arg); 373 374 bfin_cpu_type = bfin_cpus[i].type; 375 376 q = arg + strlen (p); 377 378 if (*q == '\0') 379 { 380 bfin_si_revision = bfin_cpus[i].si_revision; 381 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks; 382 } 383 else if (strcmp (q, "-none") == 0) 384 bfin_si_revision = -1; 385 else if (strcmp (q, "-any") == 0) 386 { 387 bfin_si_revision = 0xffff; 388 while (bfin_cpus[i].type == bfin_cpu_type) 389 { 390 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks; 391 i++; 392 } 393 } 394 else 395 { 396 unsigned int si_major, si_minor; 397 int rev_len, n; 398 399 rev_len = strlen (q); 400 401 if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2 402 || n != rev_len 403 || si_major > 0xff || si_minor > 0xff) 404 { 405 invalid_silicon_revision: 406 as_fatal ("-mcpu=%s has invalid silicon revision", arg); 407 } 408 409 bfin_si_revision = (si_major << 8) | si_minor; 410 411 while (bfin_cpus[i].type == bfin_cpu_type 412 && bfin_cpus[i].si_revision != bfin_si_revision) 413 i++; 414 415 if (bfin_cpus[i].type != bfin_cpu_type) 416 goto invalid_silicon_revision; 417 418 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks; 419 } 420 421 break; 422 } 423 424 case OPTION_FDPIC: 425 bfin_flags |= EF_BFIN_FDPIC; 426 bfin_pic_flag = "-mfdpic"; 427 break; 428 429 case OPTION_NOPIC: 430 bfin_flags &= ~(EF_BFIN_FDPIC); 431 bfin_pic_flag = 0; 432 break; 433 } 434 435 return 1; 436 } 437 438 void 439 md_show_usage (FILE * stream) 440 { 441 fprintf (stream, _(" Blackfin specific assembler options:\n")); 442 fprintf (stream, _(" -mcpu=<cpu[-sirevision]> specify the name of the target CPU\n")); 443 fprintf (stream, _(" -mfdpic assemble for the FDPIC ABI\n")); 444 fprintf (stream, _(" -mno-fdpic/-mnopic disable -mfdpic\n")); 445 } 446 447 /* Perform machine-specific initializations. */ 448 void 449 md_begin () 450 { 451 /* Set the ELF flags if desired. */ 452 if (bfin_flags) 453 bfd_set_private_flags (stdoutput, bfin_flags); 454 455 /* Set the default machine type. */ 456 if (!bfd_set_arch_mach (stdoutput, bfd_arch_bfin, 0)) 457 as_warn (_("Could not set architecture and machine.")); 458 459 /* Ensure that lines can begin with '(', for multiple 460 register stack pops. */ 461 lex_type ['('] = LEX_BEGIN_NAME; 462 463 #ifdef OBJ_ELF 464 record_alignment (text_section, 2); 465 record_alignment (data_section, 2); 466 record_alignment (bss_section, 2); 467 #endif 468 469 errorf = stderr; 470 obstack_init (&mempool); 471 472 #ifdef DEBUG 473 extern int debug_codeselection; 474 debug_codeselection = 1; 475 #endif 476 477 last_insn_size = 0; 478 } 479 480 /* Perform the main parsing, and assembly of the input here. Also, 481 call the required routines for alignment and fixups here. 482 This is called for every line that contains real assembly code. */ 483 484 void 485 md_assemble (char *line) 486 { 487 char *toP = 0; 488 extern char *current_inputline; 489 int size, insn_size; 490 struct bfin_insn *tmp_insn; 491 size_t len; 492 static size_t buffer_len = 0; 493 parse_state state; 494 495 len = strlen (line); 496 if (len + 2 > buffer_len) 497 { 498 if (buffer_len > 0) 499 free (current_inputline); 500 buffer_len = len + 40; 501 current_inputline = xmalloc (buffer_len); 502 } 503 memcpy (current_inputline, line, len); 504 current_inputline[len] = ';'; 505 current_inputline[len + 1] = '\0'; 506 507 state = parse (current_inputline); 508 if (state == NO_INSN_GENERATED) 509 return; 510 511 for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next) 512 if (!tmp_insn->reloc || !tmp_insn->exp->symbol) 513 insn_size += 2; 514 515 if (insn_size) 516 toP = frag_more (insn_size); 517 518 last_insn_size = insn_size; 519 520 #ifdef DEBUG 521 printf ("INS:"); 522 #endif 523 while (insn) 524 { 525 if (insn->reloc && insn->exp->symbol) 526 { 527 char *prev_toP = toP - 2; 528 switch (insn->reloc) 529 { 530 case BFD_RELOC_BFIN_24_PCREL_JUMP_L: 531 case BFD_RELOC_24_PCREL: 532 case BFD_RELOC_BFIN_16_LOW: 533 case BFD_RELOC_BFIN_16_HIGH: 534 size = 4; 535 break; 536 default: 537 size = 2; 538 } 539 540 /* Following if condition checks for the arithmetic relocations. 541 If the case then it doesn't required to generate the code. 542 It has been assumed that, their ID will be contiguous. */ 543 if ((BFD_ARELOC_BFIN_PUSH <= insn->reloc 544 && BFD_ARELOC_BFIN_COMP >= insn->reloc) 545 || insn->reloc == BFD_RELOC_BFIN_16_IMM) 546 { 547 size = 2; 548 } 549 if (insn->reloc == BFD_ARELOC_BFIN_CONST 550 || insn->reloc == BFD_ARELOC_BFIN_PUSH) 551 size = 4; 552 553 fix_new (frag_now, 554 (prev_toP - frag_now->fr_literal), 555 size, insn->exp->symbol, insn->exp->value, 556 insn->pcrel, insn->reloc); 557 } 558 else 559 { 560 md_number_to_chars (toP, insn->value, 2); 561 toP += 2; 562 } 563 564 #ifdef DEBUG 565 printf (" reloc :"); 566 printf (" %02x%02x", ((unsigned char *) &insn->value)[0], 567 ((unsigned char *) &insn->value)[1]); 568 printf ("\n"); 569 #endif 570 insn = insn->next; 571 } 572 #ifdef OBJ_ELF 573 dwarf2_emit_insn (insn_size); 574 #endif 575 576 while (*line++ != '\0') 577 if (*line == '\n') 578 bump_line_counters (); 579 } 580 581 /* Parse one line of instructions, and generate opcode for it. 582 To parse the line, YACC and LEX are used, because the instruction set 583 syntax doesn't confirm to the AT&T assembly syntax. 584 To call a YACC & LEX generated parser, we must provide the input via 585 a FILE stream, otherwise stdin is used by default. Below the input 586 to the function will be put into a temporary file, then the generated 587 parser uses the temporary file for parsing. */ 588 589 static parse_state 590 parse (char *line) 591 { 592 parse_state state; 593 YY_BUFFER_STATE buffstate; 594 595 buffstate = yy_scan_string (line); 596 597 /* our lex requires setting the start state to keyword 598 every line as the first word may be a keyword. 599 Fixes a bug where we could not have keywords as labels. */ 600 set_start_state (); 601 602 /* Call yyparse here. */ 603 state = yyparse (); 604 if (state == SEMANTIC_ERROR) 605 { 606 as_bad (_("Parse failed.")); 607 insn = 0; 608 } 609 610 yy_delete_buffer (buffstate); 611 return state; 612 } 613 614 /* We need to handle various expressions properly. 615 Such as, [SP--] = 34, concerned by md_assemble(). */ 616 617 void 618 md_operand (expressionS * expressionP) 619 { 620 if (*input_line_pointer == '[') 621 { 622 as_tsktsk ("We found a '['!"); 623 input_line_pointer++; 624 expression (expressionP); 625 } 626 } 627 628 /* Handle undefined symbols. */ 629 symbolS * 630 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 631 { 632 return (symbolS *) 0; 633 } 634 635 int 636 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, 637 segT segment ATTRIBUTE_UNUSED) 638 { 639 return 0; 640 } 641 642 /* Convert from target byte order to host byte order. */ 643 644 static int 645 md_chars_to_number (char *val, int n) 646 { 647 int retval; 648 649 for (retval = 0; n--;) 650 { 651 retval <<= 8; 652 retval |= val[n]; 653 } 654 return retval; 655 } 656 657 void 658 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) 659 { 660 char *where = fixP->fx_frag->fr_literal + fixP->fx_where; 661 662 long value = *valueP; 663 long newval; 664 665 switch (fixP->fx_r_type) 666 { 667 case BFD_RELOC_BFIN_GOT: 668 case BFD_RELOC_BFIN_GOT17M4: 669 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4: 670 fixP->fx_no_overflow = 1; 671 newval = md_chars_to_number (where, 2); 672 newval |= 0x0 & 0x7f; 673 md_number_to_chars (where, newval, 2); 674 break; 675 676 case BFD_RELOC_BFIN_10_PCREL: 677 if (!value) 678 break; 679 if (value < -1024 || value > 1022) 680 as_bad_where (fixP->fx_file, fixP->fx_line, 681 _("pcrel too far BFD_RELOC_BFIN_10")); 682 683 /* 11 bit offset even numbered, so we remove right bit. */ 684 value = value >> 1; 685 newval = md_chars_to_number (where, 2); 686 newval |= value & 0x03ff; 687 md_number_to_chars (where, newval, 2); 688 break; 689 690 case BFD_RELOC_BFIN_12_PCREL_JUMP: 691 case BFD_RELOC_BFIN_12_PCREL_JUMP_S: 692 case BFD_RELOC_12_PCREL: 693 if (!value) 694 break; 695 696 if (value < -4096 || value > 4094) 697 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_12")); 698 /* 13 bit offset even numbered, so we remove right bit. */ 699 value = value >> 1; 700 newval = md_chars_to_number (where, 2); 701 newval |= value & 0xfff; 702 md_number_to_chars (where, newval, 2); 703 break; 704 705 case BFD_RELOC_BFIN_16_LOW: 706 case BFD_RELOC_BFIN_16_HIGH: 707 fixP->fx_done = FALSE; 708 break; 709 710 case BFD_RELOC_BFIN_24_PCREL_JUMP_L: 711 case BFD_RELOC_BFIN_24_PCREL_CALL_X: 712 case BFD_RELOC_24_PCREL: 713 if (!value) 714 break; 715 716 if (value < -16777216 || value > 16777214) 717 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_24")); 718 719 /* 25 bit offset even numbered, so we remove right bit. */ 720 value = value >> 1; 721 value++; 722 723 md_number_to_chars (where - 2, value >> 16, 1); 724 md_number_to_chars (where, value, 1); 725 md_number_to_chars (where + 1, value >> 8, 1); 726 break; 727 728 case BFD_RELOC_BFIN_5_PCREL: /* LSETUP (a, b) : "a" */ 729 if (!value) 730 break; 731 if (value < 4 || value > 30) 732 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_5")); 733 value = value >> 1; 734 newval = md_chars_to_number (where, 1); 735 newval = (newval & 0xf0) | (value & 0xf); 736 md_number_to_chars (where, newval, 1); 737 break; 738 739 case BFD_RELOC_BFIN_11_PCREL: /* LSETUP (a, b) : "b" */ 740 if (!value) 741 break; 742 value += 2; 743 if (value < 4 || value > 2046) 744 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_11_PCREL")); 745 /* 11 bit unsigned even, so we remove right bit. */ 746 value = value >> 1; 747 newval = md_chars_to_number (where, 2); 748 newval |= value & 0x03ff; 749 md_number_to_chars (where, newval, 2); 750 break; 751 752 case BFD_RELOC_8: 753 if (value < -0x80 || value >= 0x7f) 754 as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_8")); 755 md_number_to_chars (where, value, 1); 756 break; 757 758 case BFD_RELOC_BFIN_16_IMM: 759 case BFD_RELOC_16: 760 if (value < -0x8000 || value >= 0x7fff) 761 as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_16")); 762 md_number_to_chars (where, value, 2); 763 break; 764 765 case BFD_RELOC_32: 766 md_number_to_chars (where, value, 4); 767 break; 768 769 case BFD_RELOC_BFIN_PLTPC: 770 md_number_to_chars (where, value, 2); 771 break; 772 773 case BFD_RELOC_BFIN_FUNCDESC: 774 case BFD_RELOC_VTABLE_INHERIT: 775 case BFD_RELOC_VTABLE_ENTRY: 776 fixP->fx_done = FALSE; 777 break; 778 779 default: 780 if ((BFD_ARELOC_BFIN_PUSH > fixP->fx_r_type) || (BFD_ARELOC_BFIN_COMP < fixP->fx_r_type)) 781 { 782 fprintf (stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type); 783 return; 784 } 785 } 786 787 if (!fixP->fx_addsy) 788 fixP->fx_done = TRUE; 789 790 } 791 792 /* Round up a section size to the appropriate boundary. */ 793 valueT 794 md_section_align (segment, size) 795 segT segment; 796 valueT size; 797 { 798 int boundary = bfd_get_section_alignment (stdoutput, segment); 799 return ((size + (1 << boundary) - 1) & (-1 << boundary)); 800 } 801 802 803 char * 804 md_atof (int type, char * litP, int * sizeP) 805 { 806 return ieee_md_atof (type, litP, sizeP, FALSE); 807 } 808 809 810 /* If while processing a fixup, a reloc really needs to be created 811 then it is done here. */ 812 813 arelent * 814 tc_gen_reloc (seg, fixp) 815 asection *seg ATTRIBUTE_UNUSED; 816 fixS *fixp; 817 { 818 arelent *reloc; 819 820 reloc = (arelent *) xmalloc (sizeof (arelent)); 821 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 822 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 823 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 824 825 reloc->addend = fixp->fx_offset; 826 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 827 828 if (reloc->howto == (reloc_howto_type *) NULL) 829 { 830 as_bad_where (fixp->fx_file, fixp->fx_line, 831 /* xgettext:c-format. */ 832 _("reloc %d not supported by object file format"), 833 (int) fixp->fx_r_type); 834 835 xfree (reloc); 836 837 return NULL; 838 } 839 840 return reloc; 841 } 842 843 /* The location from which a PC relative jump should be calculated, 844 given a PC relative reloc. */ 845 846 long 847 md_pcrel_from_section (fixP, sec) 848 fixS *fixP; 849 segT sec; 850 { 851 if (fixP->fx_addsy != (symbolS *) NULL 852 && (!S_IS_DEFINED (fixP->fx_addsy) 853 || S_GET_SEGMENT (fixP->fx_addsy) != sec)) 854 { 855 /* The symbol is undefined (or is defined but not in this section). 856 Let the linker figure it out. */ 857 return 0; 858 } 859 return fixP->fx_frag->fr_address + fixP->fx_where; 860 } 861 862 /* Return true if the fix can be handled by GAS, false if it must 863 be passed through to the linker. */ 864 865 bfd_boolean 866 bfin_fix_adjustable (fixS *fixP) 867 { 868 switch (fixP->fx_r_type) 869 { 870 /* Adjust_reloc_syms doesn't know about the GOT. */ 871 case BFD_RELOC_BFIN_GOT: 872 case BFD_RELOC_BFIN_PLTPC: 873 /* We need the symbol name for the VTABLE entries. */ 874 case BFD_RELOC_VTABLE_INHERIT: 875 case BFD_RELOC_VTABLE_ENTRY: 876 return 0; 877 878 default: 879 return 1; 880 } 881 } 882 883 /* Special extra functions that help bfin-parse.y perform its job. */ 884 885 struct obstack mempool; 886 887 INSTR_T 888 conscode (INSTR_T head, INSTR_T tail) 889 { 890 if (!head) 891 return tail; 892 head->next = tail; 893 return head; 894 } 895 896 INSTR_T 897 conctcode (INSTR_T head, INSTR_T tail) 898 { 899 INSTR_T temp = (head); 900 if (!head) 901 return tail; 902 while (temp->next) 903 temp = temp->next; 904 temp->next = tail; 905 906 return head; 907 } 908 909 INSTR_T 910 note_reloc (INSTR_T code, Expr_Node * symbol, int reloc, int pcrel) 911 { 912 /* Assert that the symbol is not an operator. */ 913 gas_assert (symbol->type == Expr_Node_Reloc); 914 915 return note_reloc1 (code, symbol->value.s_value, reloc, pcrel); 916 917 } 918 919 INSTR_T 920 note_reloc1 (INSTR_T code, const char *symbol, int reloc, int pcrel) 921 { 922 code->reloc = reloc; 923 code->exp = mkexpr (0, symbol_find_or_make (symbol)); 924 code->pcrel = pcrel; 925 return code; 926 } 927 928 INSTR_T 929 note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel) 930 { 931 code->reloc = reloc; 932 code->exp = mkexpr (value, symbol_find_or_make (symbol)); 933 code->pcrel = pcrel; 934 return code; 935 } 936 937 INSTR_T 938 gencode (unsigned long x) 939 { 940 INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn)); 941 memset (cell, 0, sizeof (struct bfin_insn)); 942 cell->value = (x); 943 return cell; 944 } 945 946 int reloc; 947 int ninsns; 948 int count_insns; 949 950 static void * 951 allocate (size_t n) 952 { 953 return obstack_alloc (&mempool, n); 954 } 955 956 Expr_Node * 957 Expr_Node_Create (Expr_Node_Type type, 958 Expr_Node_Value value, 959 Expr_Node *Left_Child, 960 Expr_Node *Right_Child) 961 { 962 963 964 Expr_Node *node = (Expr_Node *) allocate (sizeof (Expr_Node)); 965 node->type = type; 966 node->value = value; 967 node->Left_Child = Left_Child; 968 node->Right_Child = Right_Child; 969 return node; 970 } 971 972 static const char *con = ".__constant"; 973 static const char *op = ".__operator"; 974 static INSTR_T Expr_Node_Gen_Reloc_R (Expr_Node * head); 975 INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc); 976 977 INSTR_T 978 Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc) 979 { 980 /* Top level reloction expression generator VDSP style. 981 If the relocation is just by itself, generate one item 982 else generate this convoluted expression. */ 983 984 INSTR_T note = NULL_CODE; 985 INSTR_T note1 = NULL_CODE; 986 int pcrel = 1; /* Is the parent reloc pcrelative? 987 This calculation here and HOWTO should match. */ 988 989 if (parent_reloc) 990 { 991 /* If it's 32 bit quantity then 16bit code needs to be added. */ 992 int value = 0; 993 994 if (head->type == Expr_Node_Constant) 995 { 996 /* If note1 is not null code, we have to generate a right 997 aligned value for the constant. Otherwise the reloc is 998 a part of the basic command and the yacc file 999 generates this. */ 1000 value = head->value.i_value; 1001 } 1002 switch (parent_reloc) 1003 { 1004 /* Some relocations will need to allocate extra words. */ 1005 case BFD_RELOC_BFIN_16_IMM: 1006 case BFD_RELOC_BFIN_16_LOW: 1007 case BFD_RELOC_BFIN_16_HIGH: 1008 note1 = conscode (gencode (value), NULL_CODE); 1009 pcrel = 0; 1010 break; 1011 case BFD_RELOC_BFIN_PLTPC: 1012 note1 = conscode (gencode (value), NULL_CODE); 1013 pcrel = 0; 1014 break; 1015 case BFD_RELOC_16: 1016 case BFD_RELOC_BFIN_GOT: 1017 case BFD_RELOC_BFIN_GOT17M4: 1018 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4: 1019 note1 = conscode (gencode (value), NULL_CODE); 1020 pcrel = 0; 1021 break; 1022 case BFD_RELOC_24_PCREL: 1023 case BFD_RELOC_BFIN_24_PCREL_JUMP_L: 1024 case BFD_RELOC_BFIN_24_PCREL_CALL_X: 1025 /* These offsets are even numbered pcrel. */ 1026 note1 = conscode (gencode (value >> 1), NULL_CODE); 1027 break; 1028 default: 1029 note1 = NULL_CODE; 1030 } 1031 } 1032 if (head->type == Expr_Node_Constant) 1033 note = note1; 1034 else if (head->type == Expr_Node_Reloc) 1035 { 1036 note = note_reloc1 (gencode (0), head->value.s_value, parent_reloc, pcrel); 1037 if (note1 != NULL_CODE) 1038 note = conscode (note1, note); 1039 } 1040 else if (head->type == Expr_Node_Binop 1041 && (head->value.op_value == Expr_Op_Type_Add 1042 || head->value.op_value == Expr_Op_Type_Sub) 1043 && head->Left_Child->type == Expr_Node_Reloc 1044 && head->Right_Child->type == Expr_Node_Constant) 1045 { 1046 int val = head->Right_Child->value.i_value; 1047 if (head->value.op_value == Expr_Op_Type_Sub) 1048 val = -val; 1049 note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value, 1050 parent_reloc, val, 0), 1051 NULL_CODE); 1052 if (note1 != NULL_CODE) 1053 note = conscode (note1, note); 1054 } 1055 else 1056 { 1057 /* Call the recursive function. */ 1058 note = note_reloc1 (gencode (0), op, parent_reloc, pcrel); 1059 if (note1 != NULL_CODE) 1060 note = conscode (note1, note); 1061 note = conctcode (Expr_Node_Gen_Reloc_R (head), note); 1062 } 1063 return note; 1064 } 1065 1066 static INSTR_T 1067 Expr_Node_Gen_Reloc_R (Expr_Node * head) 1068 { 1069 1070 INSTR_T note = 0; 1071 INSTR_T note1 = 0; 1072 1073 switch (head->type) 1074 { 1075 case Expr_Node_Constant: 1076 note = conscode (note_reloc2 (gencode (0), con, BFD_ARELOC_BFIN_CONST, head->value.i_value, 0), NULL_CODE); 1077 break; 1078 case Expr_Node_Reloc: 1079 note = conscode (note_reloc (gencode (0), head, BFD_ARELOC_BFIN_PUSH, 0), NULL_CODE); 1080 break; 1081 case Expr_Node_Binop: 1082 note1 = conctcode (Expr_Node_Gen_Reloc_R (head->Left_Child), Expr_Node_Gen_Reloc_R (head->Right_Child)); 1083 switch (head->value.op_value) 1084 { 1085 case Expr_Op_Type_Add: 1086 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_ADD, 0), NULL_CODE)); 1087 break; 1088 case Expr_Op_Type_Sub: 1089 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_SUB, 0), NULL_CODE)); 1090 break; 1091 case Expr_Op_Type_Mult: 1092 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MULT, 0), NULL_CODE)); 1093 break; 1094 case Expr_Op_Type_Div: 1095 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_DIV, 0), NULL_CODE)); 1096 break; 1097 case Expr_Op_Type_Mod: 1098 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MOD, 0), NULL_CODE)); 1099 break; 1100 case Expr_Op_Type_Lshift: 1101 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LSHIFT, 0), NULL_CODE)); 1102 break; 1103 case Expr_Op_Type_Rshift: 1104 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_RSHIFT, 0), NULL_CODE)); 1105 break; 1106 case Expr_Op_Type_BAND: 1107 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_AND, 0), NULL_CODE)); 1108 break; 1109 case Expr_Op_Type_BOR: 1110 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_OR, 0), NULL_CODE)); 1111 break; 1112 case Expr_Op_Type_BXOR: 1113 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_XOR, 0), NULL_CODE)); 1114 break; 1115 case Expr_Op_Type_LAND: 1116 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LAND, 0), NULL_CODE)); 1117 break; 1118 case Expr_Op_Type_LOR: 1119 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LOR, 0), NULL_CODE)); 1120 break; 1121 default: 1122 fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__); 1123 1124 1125 } 1126 break; 1127 case Expr_Node_Unop: 1128 note1 = conscode (Expr_Node_Gen_Reloc_R (head->Left_Child), NULL_CODE); 1129 switch (head->value.op_value) 1130 { 1131 case Expr_Op_Type_NEG: 1132 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_NEG, 0), NULL_CODE)); 1133 break; 1134 case Expr_Op_Type_COMP: 1135 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_COMP, 0), NULL_CODE)); 1136 break; 1137 default: 1138 fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__); 1139 } 1140 break; 1141 default: 1142 fprintf (stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__); 1143 } 1144 return note; 1145 } 1146 1147 /* Blackfin opcode generation. */ 1149 1150 /* These functions are called by the generated parser 1151 (from bfin-parse.y), the register type classification 1152 happens in bfin-lex.l. */ 1153 1154 #include "bfin-aux.h" 1155 #include "opcode/bfin.h" 1156 1157 #define INIT(t) t c_code = init_##t 1158 #define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x) 1159 #define ASSIGNF(x,f) c_code.opcode |= ((x & c_code.mask_##f)<<c_code.bits_##f) 1160 #define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x) 1161 1162 #define HI(x) ((x >> 16) & 0xffff) 1163 #define LO(x) ((x ) & 0xffff) 1164 1165 #define GROUP(x) ((x->regno & CLASS_MASK) >> 4) 1166 1167 #define GEN_OPCODE32() \ 1168 conscode (gencode (HI (c_code.opcode)), \ 1169 conscode (gencode (LO (c_code.opcode)), NULL_CODE)) 1170 1171 #define GEN_OPCODE16() \ 1172 conscode (gencode (c_code.opcode), NULL_CODE) 1173 1174 1175 /* 32 BIT INSTRUCTIONS. */ 1176 1177 1178 /* DSP32 instruction generation. */ 1179 1180 INSTR_T 1181 bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P, 1182 int h01, int h11, int h00, int h10, int op0, 1183 REG_T dst, REG_T src0, REG_T src1, int w0) 1184 { 1185 INIT (DSP32Mac); 1186 1187 ASSIGN (op0); 1188 ASSIGN (op1); 1189 ASSIGN (MM); 1190 ASSIGN (mmod); 1191 ASSIGN (w0); 1192 ASSIGN (w1); 1193 ASSIGN (h01); 1194 ASSIGN (h11); 1195 ASSIGN (h00); 1196 ASSIGN (h10); 1197 ASSIGN (P); 1198 1199 /* If we have full reg assignments, mask out LSB to encode 1200 single or simultaneous even/odd register moves. */ 1201 if (P) 1202 { 1203 dst->regno &= 0x06; 1204 } 1205 1206 ASSIGN_R (dst); 1207 ASSIGN_R (src0); 1208 ASSIGN_R (src1); 1209 1210 return GEN_OPCODE32 (); 1211 } 1212 1213 INSTR_T 1214 bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P, 1215 int h01, int h11, int h00, int h10, int op0, 1216 REG_T dst, REG_T src0, REG_T src1, int w0) 1217 { 1218 INIT (DSP32Mult); 1219 1220 ASSIGN (op0); 1221 ASSIGN (op1); 1222 ASSIGN (MM); 1223 ASSIGN (mmod); 1224 ASSIGN (w0); 1225 ASSIGN (w1); 1226 ASSIGN (h01); 1227 ASSIGN (h11); 1228 ASSIGN (h00); 1229 ASSIGN (h10); 1230 ASSIGN (P); 1231 1232 if (P) 1233 { 1234 dst->regno &= 0x06; 1235 } 1236 1237 ASSIGN_R (dst); 1238 ASSIGN_R (src0); 1239 ASSIGN_R (src1); 1240 1241 return GEN_OPCODE32 (); 1242 } 1243 1244 INSTR_T 1245 bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x, 1246 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1) 1247 { 1248 INIT (DSP32Alu); 1249 1250 ASSIGN (HL); 1251 ASSIGN (aopcde); 1252 ASSIGN (aop); 1253 ASSIGN (s); 1254 ASSIGN (x); 1255 ASSIGN_R (dst0); 1256 ASSIGN_R (dst1); 1257 ASSIGN_R (src0); 1258 ASSIGN_R (src1); 1259 1260 return GEN_OPCODE32 (); 1261 } 1262 1263 INSTR_T 1264 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, 1265 REG_T src1, int sop, int HLs) 1266 { 1267 INIT (DSP32Shift); 1268 1269 ASSIGN (sopcde); 1270 ASSIGN (sop); 1271 ASSIGN (HLs); 1272 1273 ASSIGN_R (dst0); 1274 ASSIGN_R (src0); 1275 ASSIGN_R (src1); 1276 1277 return GEN_OPCODE32 (); 1278 } 1279 1280 INSTR_T 1281 bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, 1282 REG_T src1, int sop, int HLs) 1283 { 1284 INIT (DSP32ShiftImm); 1285 1286 ASSIGN (sopcde); 1287 ASSIGN (sop); 1288 ASSIGN (HLs); 1289 1290 ASSIGN_R (dst0); 1291 ASSIGN (immag); 1292 ASSIGN_R (src1); 1293 1294 return GEN_OPCODE32 (); 1295 } 1296 1297 /* LOOP SETUP. */ 1298 1299 INSTR_T 1300 bfin_gen_loopsetup (Expr_Node * psoffset, REG_T c, int rop, 1301 Expr_Node * peoffset, REG_T reg) 1302 { 1303 int soffset, eoffset; 1304 INIT (LoopSetup); 1305 1306 soffset = (EXPR_VALUE (psoffset) >> 1); 1307 ASSIGN (soffset); 1308 eoffset = (EXPR_VALUE (peoffset) >> 1); 1309 ASSIGN (eoffset); 1310 ASSIGN (rop); 1311 ASSIGN_R (c); 1312 ASSIGN_R (reg); 1313 1314 return 1315 conscode (gencode (HI (c_code.opcode)), 1316 conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL), 1317 conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL)))); 1318 1319 } 1320 1321 /* Call, Link. */ 1322 1323 INSTR_T 1324 bfin_gen_calla (Expr_Node * addr, int S) 1325 { 1326 int val; 1327 int high_val; 1328 int rel = 0; 1329 INIT (CALLa); 1330 1331 switch(S){ 1332 case 0 : rel = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break; 1333 case 1 : rel = BFD_RELOC_24_PCREL; break; 1334 case 2 : rel = BFD_RELOC_BFIN_PLTPC; break; 1335 default : break; 1336 } 1337 1338 ASSIGN (S); 1339 1340 val = EXPR_VALUE (addr) >> 1; 1341 high_val = val >> 16; 1342 1343 return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)), 1344 Expr_Node_Gen_Reloc (addr, rel)); 1345 } 1346 1347 INSTR_T 1348 bfin_gen_linkage (int R, int framesize) 1349 { 1350 INIT (Linkage); 1351 1352 ASSIGN (R); 1353 ASSIGN (framesize); 1354 1355 return GEN_OPCODE32 (); 1356 } 1357 1358 1359 /* Load and Store. */ 1360 1361 INSTR_T 1362 bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int rel) 1363 { 1364 int grp, hword; 1365 unsigned val = EXPR_VALUE (phword); 1366 INIT (LDIMMhalf); 1367 1368 ASSIGN (H); 1369 ASSIGN (S); 1370 ASSIGN (Z); 1371 1372 ASSIGN_R (reg); 1373 grp = (GROUP (reg)); 1374 ASSIGN (grp); 1375 if (rel == 2) 1376 { 1377 return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM)); 1378 } 1379 else if (rel == 1) 1380 { 1381 return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW)); 1382 } 1383 else 1384 { 1385 hword = val; 1386 ASSIGN (hword); 1387 } 1388 return GEN_OPCODE32 (); 1389 } 1390 1391 INSTR_T 1392 bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffset) 1393 { 1394 INIT (LDSTidxI); 1395 1396 if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z)) 1397 { 1398 fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n"); 1399 return 0; 1400 } 1401 1402 ASSIGN_R (ptr); 1403 ASSIGN_R (reg); 1404 ASSIGN (W); 1405 ASSIGN (sz); 1406 1407 ASSIGN (Z); 1408 1409 if (poffset->type != Expr_Node_Constant) 1410 { 1411 /* a GOT relocation such as R0 = [P5 + symbol@GOT] */ 1412 /* distinguish between R0 = [P5 + symbol@GOT] and 1413 P5 = [P5 + _current_shared_library_p5_offset_] 1414 */ 1415 if (poffset->type == Expr_Node_Reloc 1416 && !strcmp (poffset->value.s_value, 1417 "_current_shared_library_p5_offset_")) 1418 { 1419 return conscode (gencode (HI (c_code.opcode)), 1420 Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16)); 1421 } 1422 else if (poffset->type != Expr_Node_GOT_Reloc) 1423 abort (); 1424 1425 return conscode (gencode (HI (c_code.opcode)), 1426 Expr_Node_Gen_Reloc(poffset->Left_Child, 1427 poffset->value.i_value)); 1428 } 1429 else 1430 { 1431 int value, offset; 1432 switch (sz) 1433 { /* load/store access size */ 1434 case 0: /* 32 bit */ 1435 value = EXPR_VALUE (poffset) >> 2; 1436 break; 1437 case 1: /* 16 bit */ 1438 value = EXPR_VALUE (poffset) >> 1; 1439 break; 1440 case 2: /* 8 bit */ 1441 value = EXPR_VALUE (poffset); 1442 break; 1443 default: 1444 abort (); 1445 } 1446 1447 offset = (value & 0xffff); 1448 ASSIGN (offset); 1449 return GEN_OPCODE32 (); 1450 } 1451 } 1452 1453 1454 INSTR_T 1455 bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int Z, int W) 1456 { 1457 INIT (LDST); 1458 1459 if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z)) 1460 { 1461 fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n"); 1462 return 0; 1463 } 1464 1465 ASSIGN_R (ptr); 1466 ASSIGN_R (reg); 1467 ASSIGN (aop); 1468 ASSIGN (sz); 1469 ASSIGN (Z); 1470 ASSIGN (W); 1471 1472 return GEN_OPCODE16 (); 1473 } 1474 1475 INSTR_T 1476 bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int opc) 1477 { 1478 int offset; 1479 int value = 0; 1480 INIT (LDSTii); 1481 1482 if (!IS_PREG (*ptr)) 1483 { 1484 fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n"); 1485 return 0; 1486 } 1487 1488 switch (opc) 1489 { 1490 case 1: 1491 case 2: 1492 value = EXPR_VALUE (poffset) >> 1; 1493 break; 1494 case 0: 1495 case 3: 1496 value = EXPR_VALUE (poffset) >> 2; 1497 break; 1498 } 1499 1500 ASSIGN_R (ptr); 1501 ASSIGN_R (reg); 1502 1503 offset = value; 1504 ASSIGN (offset); 1505 ASSIGN (W); 1506 ASSIGNF (opc, op); 1507 1508 return GEN_OPCODE16 (); 1509 } 1510 1511 INSTR_T 1512 bfin_gen_ldstiifp (REG_T sreg, Expr_Node * poffset, int W) 1513 { 1514 /* Set bit 4 if it's a Preg. */ 1515 int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0); 1516 int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1; 1517 INIT (LDSTiiFP); 1518 ASSIGN (reg); 1519 ASSIGN (offset); 1520 ASSIGN (W); 1521 1522 return GEN_OPCODE16 (); 1523 } 1524 1525 INSTR_T 1526 bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int W, REG_T idx) 1527 { 1528 INIT (LDSTpmod); 1529 1530 ASSIGN_R (ptr); 1531 ASSIGN_R (reg); 1532 ASSIGN (aop); 1533 ASSIGN (W); 1534 ASSIGN_R (idx); 1535 1536 return GEN_OPCODE16 (); 1537 } 1538 1539 INSTR_T 1540 bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int W, int m) 1541 { 1542 INIT (DspLDST); 1543 1544 ASSIGN_R (i); 1545 ASSIGN_R (reg); 1546 ASSIGN (aop); 1547 ASSIGN (W); 1548 ASSIGN (m); 1549 1550 return GEN_OPCODE16 (); 1551 } 1552 1553 INSTR_T 1554 bfin_gen_logi2op (int opc, int src, int dst) 1555 { 1556 INIT (LOGI2op); 1557 1558 ASSIGN (opc); 1559 ASSIGN (src); 1560 ASSIGN (dst); 1561 1562 return GEN_OPCODE16 (); 1563 } 1564 1565 INSTR_T 1566 bfin_gen_brcc (int T, int B, Expr_Node * poffset) 1567 { 1568 int offset; 1569 INIT (BRCC); 1570 1571 ASSIGN (T); 1572 ASSIGN (B); 1573 offset = ((EXPR_VALUE (poffset) >> 1)); 1574 ASSIGN (offset); 1575 return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL)); 1576 } 1577 1578 INSTR_T 1579 bfin_gen_ujump (Expr_Node * poffset) 1580 { 1581 int offset; 1582 INIT (UJump); 1583 1584 offset = ((EXPR_VALUE (poffset) >> 1)); 1585 ASSIGN (offset); 1586 1587 return conscode (gencode (c_code.opcode), 1588 Expr_Node_Gen_Reloc ( 1589 poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S)); 1590 } 1591 1592 INSTR_T 1593 bfin_gen_alu2op (REG_T dst, REG_T src, int opc) 1594 { 1595 INIT (ALU2op); 1596 1597 ASSIGN_R (dst); 1598 ASSIGN_R (src); 1599 ASSIGN (opc); 1600 1601 return GEN_OPCODE16 (); 1602 } 1603 1604 INSTR_T 1605 bfin_gen_compi2opd (REG_T dst, int src, int opc) 1606 { 1607 INIT (COMPI2opD); 1608 1609 ASSIGN_R (dst); 1610 ASSIGN (src); 1611 ASSIGNF (opc, op); 1612 1613 return GEN_OPCODE16 (); 1614 } 1615 1616 INSTR_T 1617 bfin_gen_compi2opp (REG_T dst, int src, int opc) 1618 { 1619 INIT (COMPI2opP); 1620 1621 ASSIGN_R (dst); 1622 ASSIGN (src); 1623 ASSIGNF (opc, op); 1624 1625 return GEN_OPCODE16 (); 1626 } 1627 1628 INSTR_T 1629 bfin_gen_dagmodik (REG_T i, int opc) 1630 { 1631 INIT (DagMODik); 1632 1633 ASSIGN_R (i); 1634 ASSIGNF (opc, op); 1635 1636 return GEN_OPCODE16 (); 1637 } 1638 1639 INSTR_T 1640 bfin_gen_dagmodim (REG_T i, REG_T m, int opc, int br) 1641 { 1642 INIT (DagMODim); 1643 1644 ASSIGN_R (i); 1645 ASSIGN_R (m); 1646 ASSIGNF (opc, op); 1647 ASSIGN (br); 1648 1649 return GEN_OPCODE16 (); 1650 } 1651 1652 INSTR_T 1653 bfin_gen_ptr2op (REG_T dst, REG_T src, int opc) 1654 { 1655 INIT (PTR2op); 1656 1657 ASSIGN_R (dst); 1658 ASSIGN_R (src); 1659 ASSIGN (opc); 1660 1661 return GEN_OPCODE16 (); 1662 } 1663 1664 INSTR_T 1665 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc) 1666 { 1667 INIT (COMP3op); 1668 1669 ASSIGN_R (src0); 1670 ASSIGN_R (src1); 1671 ASSIGN_R (dst); 1672 ASSIGN (opc); 1673 1674 return GEN_OPCODE16 (); 1675 } 1676 1677 INSTR_T 1678 bfin_gen_ccflag (REG_T x, int y, int opc, int I, int G) 1679 { 1680 INIT (CCflag); 1681 1682 ASSIGN_R (x); 1683 ASSIGN (y); 1684 ASSIGN (opc); 1685 ASSIGN (I); 1686 ASSIGN (G); 1687 1688 return GEN_OPCODE16 (); 1689 } 1690 1691 INSTR_T 1692 bfin_gen_ccmv (REG_T src, REG_T dst, int T) 1693 { 1694 int s, d; 1695 INIT (CCmv); 1696 1697 ASSIGN_R (src); 1698 ASSIGN_R (dst); 1699 s = (GROUP (src)); 1700 ASSIGN (s); 1701 d = (GROUP (dst)); 1702 ASSIGN (d); 1703 ASSIGN (T); 1704 1705 return GEN_OPCODE16 (); 1706 } 1707 1708 INSTR_T 1709 bfin_gen_cc2stat (int cbit, int opc, int D) 1710 { 1711 INIT (CC2stat); 1712 1713 ASSIGN (cbit); 1714 ASSIGNF (opc, op); 1715 ASSIGN (D); 1716 1717 return GEN_OPCODE16 (); 1718 } 1719 1720 INSTR_T 1721 bfin_gen_regmv (REG_T src, REG_T dst) 1722 { 1723 int gs, gd; 1724 INIT (RegMv); 1725 1726 ASSIGN_R (src); 1727 ASSIGN_R (dst); 1728 1729 gs = (GROUP (src)); 1730 ASSIGN (gs); 1731 gd = (GROUP (dst)); 1732 ASSIGN (gd); 1733 1734 return GEN_OPCODE16 (); 1735 } 1736 1737 INSTR_T 1738 bfin_gen_cc2dreg (int opc, REG_T reg) 1739 { 1740 INIT (CC2dreg); 1741 1742 ASSIGNF (opc, op); 1743 ASSIGN_R (reg); 1744 1745 return GEN_OPCODE16 (); 1746 } 1747 1748 INSTR_T 1749 bfin_gen_progctrl (int prgfunc, int poprnd) 1750 { 1751 INIT (ProgCtrl); 1752 1753 ASSIGN (prgfunc); 1754 ASSIGN (poprnd); 1755 1756 return GEN_OPCODE16 (); 1757 } 1758 1759 INSTR_T 1760 bfin_gen_cactrl (REG_T reg, int a, int opc) 1761 { 1762 INIT (CaCTRL); 1763 1764 ASSIGN_R (reg); 1765 ASSIGN (a); 1766 ASSIGNF (opc, op); 1767 1768 return GEN_OPCODE16 (); 1769 } 1770 1771 INSTR_T 1772 bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int W) 1773 { 1774 INIT (PushPopMultiple); 1775 1776 ASSIGN (dr); 1777 ASSIGN (pr); 1778 ASSIGN (d); 1779 ASSIGN (p); 1780 ASSIGN (W); 1781 1782 return GEN_OPCODE16 (); 1783 } 1784 1785 INSTR_T 1786 bfin_gen_pushpopreg (REG_T reg, int W) 1787 { 1788 int grp; 1789 INIT (PushPopReg); 1790 1791 ASSIGN_R (reg); 1792 grp = (GROUP (reg)); 1793 ASSIGN (grp); 1794 ASSIGN (W); 1795 1796 return GEN_OPCODE16 (); 1797 } 1798 1799 /* Pseudo Debugging Support. */ 1800 1801 INSTR_T 1802 bfin_gen_pseudodbg (int fn, int reg, int grp) 1803 { 1804 INIT (PseudoDbg); 1805 1806 ASSIGN (fn); 1807 ASSIGN (reg); 1808 ASSIGN (grp); 1809 1810 return GEN_OPCODE16 (); 1811 } 1812 1813 INSTR_T 1814 bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected) 1815 { 1816 int grp; 1817 INIT (PseudoDbg_Assert); 1818 1819 ASSIGN (dbgop); 1820 ASSIGN_R (regtest); 1821 grp = GROUP (regtest); 1822 ASSIGN (grp); 1823 ASSIGN (expected); 1824 1825 return GEN_OPCODE32 (); 1826 } 1827 1828 INSTR_T 1829 bfin_gen_pseudochr (int ch) 1830 { 1831 INIT (PseudoChr); 1832 1833 ASSIGN (ch); 1834 1835 return GEN_OPCODE16 (); 1836 } 1837 1838 /* Multiple instruction generation. */ 1839 1840 INSTR_T 1841 bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2) 1842 { 1843 INSTR_T walk; 1844 1845 /* If it's a 0, convert into MNOP. */ 1846 if (dsp32) 1847 { 1848 walk = dsp32->next; 1849 SET_MULTI_INSTRUCTION_BIT (dsp32); 1850 } 1851 else 1852 { 1853 dsp32 = gencode (0xc803); 1854 walk = gencode (0x1800); 1855 dsp32->next = walk; 1856 } 1857 1858 if (!dsp16_grp1) 1859 { 1860 dsp16_grp1 = gencode (0x0000); 1861 } 1862 1863 if (!dsp16_grp2) 1864 { 1865 dsp16_grp2 = gencode (0x0000); 1866 } 1867 1868 walk->next = dsp16_grp1; 1869 dsp16_grp1->next = dsp16_grp2; 1870 dsp16_grp2->next = NULL_CODE; 1871 1872 return dsp32; 1873 } 1874 1875 INSTR_T 1876 bfin_gen_loop (Expr_Node *exp, REG_T reg, int rop, REG_T preg) 1877 { 1878 const char *loopsym; 1879 char *lbeginsym, *lendsym; 1880 Expr_Node_Value lbeginval, lendval; 1881 Expr_Node *lbegin, *lend; 1882 symbolS *sym; 1883 1884 loopsym = exp->value.s_value; 1885 lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5); 1886 lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5); 1887 1888 lbeginsym[0] = 0; 1889 lendsym[0] = 0; 1890 1891 strcat (lbeginsym, "L$L$"); 1892 strcat (lbeginsym, loopsym); 1893 strcat (lbeginsym, "__BEGIN"); 1894 1895 strcat (lendsym, "L$L$"); 1896 strcat (lendsym, loopsym); 1897 strcat (lendsym, "__END"); 1898 1899 lbeginval.s_value = lbeginsym; 1900 lendval.s_value = lendsym; 1901 1902 lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL); 1903 lend = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL); 1904 1905 sym = symbol_find(loopsym); 1906 if (!S_IS_LOCAL (sym) || (S_IS_LOCAL (sym) && !symbol_used_p (sym))) 1907 symbol_remove (sym, &symbol_rootP, &symbol_lastP); 1908 1909 return bfin_gen_loopsetup (lbegin, reg, rop, lend, preg); 1910 } 1911 1912 void 1913 bfin_loop_attempt_create_label (Expr_Node *exp, int is_begin) 1914 { 1915 char *name; 1916 name = fb_label_name (exp->value.i_value, is_begin); 1917 exp->value.s_value = xstrdup (name); 1918 exp->type = Expr_Node_Reloc; 1919 } 1920 1921 void 1922 bfin_loop_beginend (Expr_Node *exp, int begin) 1923 { 1924 const char *loopsym; 1925 char *label_name; 1926 symbolS *linelabel; 1927 const char *suffix = begin ? "__BEGIN" : "__END"; 1928 1929 loopsym = exp->value.s_value; 1930 label_name = (char *) xmalloc (strlen (loopsym) + strlen (suffix) + 5); 1931 1932 label_name[0] = 0; 1933 1934 strcat (label_name, "L$L$"); 1935 strcat (label_name, loopsym); 1936 strcat (label_name, suffix); 1937 1938 linelabel = colon (label_name); 1939 1940 /* LOOP_END follows the last instruction in the loop. 1941 Adjust label address. */ 1942 if (!begin) 1943 ((struct local_symbol *) linelabel)->lsy_value -= last_insn_size; 1944 } 1945 1946 bfd_boolean 1947 bfin_eol_in_insn (char *line) 1948 { 1949 /* Allow a new-line to appear in the middle of a multi-issue instruction. */ 1950 1951 char *temp = line; 1952 1953 if (*line != '\n') 1954 return FALSE; 1955 1956 /* A semi-colon followed by a newline is always the end of a line. */ 1957 if (line[-1] == ';') 1958 return FALSE; 1959 1960 if (line[-1] == '|') 1961 return TRUE; 1962 1963 /* If the || is on the next line, there might be leading whitespace. */ 1964 temp++; 1965 while (*temp == ' ' || *temp == '\t') temp++; 1966 1967 if (*temp == '|') 1968 return TRUE; 1969 1970 return FALSE; 1971 } 1972 1973 bfd_boolean 1974 bfin_start_label (char *s, char *ptr) 1975 { 1976 while (s != ptr) 1977 { 1978 if (*s == '(' || *s == '[') 1979 return FALSE; 1980 s++; 1981 } 1982 1983 return TRUE; 1984 } 1985 1986 int 1987 bfin_force_relocation (struct fix *fixp) 1988 { 1989 if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW 1990 || fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH) 1991 return TRUE; 1992 1993 return generic_force_reloc (fixp); 1994 } 1995 1996 /* This is a stripped down version of the disassembler. The only thing it 1998 does is return a mask of registers modified by an instruction. Only 1999 instructions that can occur in a parallel-issue bundle are handled, and 2000 only the registers that can cause a conflict are recorded. */ 2001 2002 #define DREG_MASK(n) (0x101 << (n)) 2003 #define DREGH_MASK(n) (0x100 << (n)) 2004 #define DREGL_MASK(n) (0x001 << (n)) 2005 #define IREG_MASK(n) (1 << ((n) + 16)) 2006 2007 static int 2008 decode_ProgCtrl_0 (int iw0) 2009 { 2010 if (iw0 == 0) 2011 return 0; 2012 abort (); 2013 } 2014 2015 static int 2016 decode_LDSTpmod_0 (int iw0) 2017 { 2018 /* LDSTpmod 2019 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2020 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| 2021 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2022 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); 2023 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); 2024 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); 2025 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); 2026 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); 2027 2028 if (aop == 1 && W == 0 && idx == ptr) 2029 return DREGL_MASK (reg); 2030 else if (aop == 2 && W == 0 && idx == ptr) 2031 return DREGH_MASK (reg); 2032 else if (aop == 1 && W == 1 && idx == ptr) 2033 return 0; 2034 else if (aop == 2 && W == 1 && idx == ptr) 2035 return 0; 2036 else if (aop == 0 && W == 0) 2037 return DREG_MASK (reg); 2038 else if (aop == 1 && W == 0) 2039 return DREGL_MASK (reg); 2040 else if (aop == 2 && W == 0) 2041 return DREGH_MASK (reg); 2042 else if (aop == 3 && W == 0) 2043 return DREG_MASK (reg); 2044 else if (aop == 3 && W == 1) 2045 return DREG_MASK (reg); 2046 else if (aop == 0 && W == 1) 2047 return 0; 2048 else if (aop == 1 && W == 1) 2049 return 0; 2050 else if (aop == 2 && W == 1) 2051 return 0; 2052 else 2053 return 0; 2054 2055 return 2; 2056 } 2057 2058 static int 2059 decode_dagMODim_0 (int iw0) 2060 { 2061 /* dagMODim 2062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2063 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| 2064 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2065 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); 2066 int opc = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); 2067 2068 if (opc == 0 || opc == 1) 2069 return IREG_MASK (i); 2070 else 2071 return 0; 2072 2073 return 2; 2074 } 2075 2076 static int 2077 decode_dagMODik_0 (int iw0) 2078 { 2079 /* dagMODik 2080 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2081 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| 2082 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2083 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); 2084 return IREG_MASK (i); 2085 } 2086 2087 /* GOOD */ 2088 static int 2089 decode_dspLDST_0 (int iw0) 2090 { 2091 /* dspLDST 2092 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2093 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| 2094 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2095 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); 2096 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); 2097 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); 2098 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); 2099 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); 2100 2101 if (aop == 0 && W == 0 && m == 0) 2102 return DREG_MASK (reg) | IREG_MASK (i); 2103 else if (aop == 0 && W == 0 && m == 1) 2104 return DREGL_MASK (reg) | IREG_MASK (i); 2105 else if (aop == 0 && W == 0 && m == 2) 2106 return DREGH_MASK (reg) | IREG_MASK (i); 2107 else if (aop == 1 && W == 0 && m == 0) 2108 return DREG_MASK (reg) | IREG_MASK (i); 2109 else if (aop == 1 && W == 0 && m == 1) 2110 return DREGL_MASK (reg) | IREG_MASK (i); 2111 else if (aop == 1 && W == 0 && m == 2) 2112 return DREGH_MASK (reg) | IREG_MASK (i); 2113 else if (aop == 2 && W == 0 && m == 0) 2114 return DREG_MASK (reg); 2115 else if (aop == 2 && W == 0 && m == 1) 2116 return DREGL_MASK (reg); 2117 else if (aop == 2 && W == 0 && m == 2) 2118 return DREGH_MASK (reg); 2119 else if (aop == 0 && W == 1 && m == 0) 2120 return IREG_MASK (i); 2121 else if (aop == 0 && W == 1 && m == 1) 2122 return IREG_MASK (i); 2123 else if (aop == 0 && W == 1 && m == 2) 2124 return IREG_MASK (i); 2125 else if (aop == 1 && W == 1 && m == 0) 2126 return IREG_MASK (i); 2127 else if (aop == 1 && W == 1 && m == 1) 2128 return IREG_MASK (i); 2129 else if (aop == 1 && W == 1 && m == 2) 2130 return IREG_MASK (i); 2131 else if (aop == 2 && W == 1 && m == 0) 2132 return 0; 2133 else if (aop == 2 && W == 1 && m == 1) 2134 return 0; 2135 else if (aop == 2 && W == 1 && m == 2) 2136 return 0; 2137 else if (aop == 3 && W == 0) 2138 return DREG_MASK (reg) | IREG_MASK (i); 2139 else if (aop == 3 && W == 1) 2140 return IREG_MASK (i); 2141 2142 abort (); 2143 } 2144 2145 /* GOOD */ 2146 static int 2147 decode_LDST_0 (int iw0) 2148 { 2149 /* LDST 2150 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2151 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| 2152 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2153 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); 2154 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); 2155 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); 2156 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); 2157 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); 2158 2159 if (aop == 0 && sz == 0 && Z == 0 && W == 0) 2160 return DREG_MASK (reg); 2161 else if (aop == 0 && sz == 0 && Z == 1 && W == 0) 2162 return 0; 2163 else if (aop == 0 && sz == 1 && Z == 0 && W == 0) 2164 return DREG_MASK (reg); 2165 else if (aop == 0 && sz == 1 && Z == 1 && W == 0) 2166 return DREG_MASK (reg); 2167 else if (aop == 0 && sz == 2 && Z == 0 && W == 0) 2168 return DREG_MASK (reg); 2169 else if (aop == 0 && sz == 2 && Z == 1 && W == 0) 2170 return DREG_MASK (reg); 2171 else if (aop == 1 && sz == 0 && Z == 0 && W == 0) 2172 return DREG_MASK (reg); 2173 else if (aop == 1 && sz == 0 && Z == 1 && W == 0) 2174 return 0; 2175 else if (aop == 1 && sz == 1 && Z == 0 && W == 0) 2176 return DREG_MASK (reg); 2177 else if (aop == 1 && sz == 1 && Z == 1 && W == 0) 2178 return DREG_MASK (reg); 2179 else if (aop == 1 && sz == 2 && Z == 0 && W == 0) 2180 return DREG_MASK (reg); 2181 else if (aop == 1 && sz == 2 && Z == 1 && W == 0) 2182 return DREG_MASK (reg); 2183 else if (aop == 2 && sz == 0 && Z == 0 && W == 0) 2184 return DREG_MASK (reg); 2185 else if (aop == 2 && sz == 0 && Z == 1 && W == 0) 2186 return 0; 2187 else if (aop == 2 && sz == 1 && Z == 0 && W == 0) 2188 return DREG_MASK (reg); 2189 else if (aop == 2 && sz == 1 && Z == 1 && W == 0) 2190 return DREG_MASK (reg); 2191 else if (aop == 2 && sz == 2 && Z == 0 && W == 0) 2192 return DREG_MASK (reg); 2193 else if (aop == 2 && sz == 2 && Z == 1 && W == 0) 2194 return DREG_MASK (reg); 2195 else if (aop == 0 && sz == 0 && Z == 0 && W == 1) 2196 return 0; 2197 else if (aop == 0 && sz == 0 && Z == 1 && W == 1) 2198 return 0; 2199 else if (aop == 0 && sz == 1 && Z == 0 && W == 1) 2200 return 0; 2201 else if (aop == 0 && sz == 2 && Z == 0 && W == 1) 2202 return 0; 2203 else if (aop == 1 && sz == 0 && Z == 0 && W == 1) 2204 return 0; 2205 else if (aop == 1 && sz == 0 && Z == 1 && W == 1) 2206 return 0; 2207 else if (aop == 1 && sz == 1 && Z == 0 && W == 1) 2208 return 0; 2209 else if (aop == 1 && sz == 2 && Z == 0 && W == 1) 2210 return 0; 2211 else if (aop == 2 && sz == 0 && Z == 0 && W == 1) 2212 return 0; 2213 else if (aop == 2 && sz == 0 && Z == 1 && W == 1) 2214 return 0; 2215 else if (aop == 2 && sz == 1 && Z == 0 && W == 1) 2216 return 0; 2217 else if (aop == 2 && sz == 2 && Z == 0 && W == 1) 2218 return 0; 2219 2220 abort (); 2221 } 2222 2223 static int 2224 decode_LDSTiiFP_0 (int iw0) 2225 { 2226 /* LDSTiiFP 2227 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2228 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| 2229 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2230 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask); 2231 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); 2232 2233 if (W == 0) 2234 return reg < 8 ? DREG_MASK (reg) : 0; 2235 else 2236 return 0; 2237 } 2238 2239 static int 2240 decode_LDSTii_0 (int iw0) 2241 { 2242 /* LDSTii 2243 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2244 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| 2245 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2246 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); 2247 int opc = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); 2248 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); 2249 2250 if (W == 0 && opc != 3) 2251 return DREG_MASK (reg); 2252 else if (W == 0 && opc == 3) 2253 return 0; 2254 else if (W == 1 && opc == 0) 2255 return 0; 2256 else if (W == 1 && opc == 1) 2257 return 0; 2258 else if (W == 1 && opc == 3) 2259 return 0; 2260 2261 abort (); 2262 } 2263 2264 static int 2265 decode_dsp32mac_0 (int iw0, int iw1) 2266 { 2267 int result = 0; 2268 /* dsp32mac 2269 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2270 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| 2271 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| 2272 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2273 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); 2274 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); 2275 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); 2276 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); 2277 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); 2278 int MM = ((iw1 >> DSP32Mac_MM_bits) & DSP32Mac_MM_mask); 2279 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); 2280 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); 2281 2282 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) 2283 return 0; 2284 2285 if (op1 == 3 && MM) 2286 return 0; 2287 2288 if ((w1 || w0) && mmod == M_W32) 2289 return 0; 2290 2291 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0) 2292 return 0; 2293 2294 if (w1 == 1 || op1 != 3) 2295 { 2296 if (w1) 2297 { 2298 if (P) 2299 return DREG_MASK (dst + 1); 2300 else 2301 return DREGH_MASK (dst); 2302 } 2303 } 2304 2305 if (w0 == 1 || op0 != 3) 2306 { 2307 if (w0) 2308 { 2309 if (P) 2310 return DREG_MASK (dst); 2311 else 2312 return DREGL_MASK (dst); 2313 } 2314 } 2315 2316 return result; 2317 } 2318 2319 static int 2320 decode_dsp32mult_0 (int iw0, int iw1) 2321 { 2322 /* dsp32mult 2323 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2324 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| 2325 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| 2326 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2327 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); 2328 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); 2329 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); 2330 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); 2331 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); 2332 int result = 0; 2333 2334 if (w1 == 0 && w0 == 0) 2335 return 0; 2336 2337 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) 2338 return 0; 2339 2340 if (w1) 2341 { 2342 if (P) 2343 return DREG_MASK (dst | 1); 2344 else 2345 return DREGH_MASK (dst); 2346 } 2347 2348 if (w0) 2349 { 2350 if (P) 2351 return DREG_MASK (dst); 2352 else 2353 return DREGL_MASK (dst); 2354 } 2355 2356 return result; 2357 } 2358 2359 static int 2360 decode_dsp32alu_0 (int iw0, int iw1) 2361 { 2362 /* dsp32alu 2363 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2364 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| 2365 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| 2366 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2367 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); 2368 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); 2369 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); 2370 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); 2371 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); 2372 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); 2373 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); 2374 2375 if (aop == 0 && aopcde == 9 && s == 0) 2376 return 0; 2377 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) 2378 return 0; 2379 else if (aop >= x * 2 && aopcde == 5) 2380 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2381 else if (HL == 0 && aopcde == 2) 2382 return DREGL_MASK (dst0); 2383 else if (HL == 1 && aopcde == 2) 2384 return DREGH_MASK (dst0); 2385 else if (HL == 0 && aopcde == 3) 2386 return DREGL_MASK (dst0); 2387 else if (HL == 1 && aopcde == 3) 2388 return DREGH_MASK (dst0); 2389 2390 else if (aop == 0 && aopcde == 9 && s == 1) 2391 return 0; 2392 else if (aop == 1 && aopcde == 9 && s == 0) 2393 return 0; 2394 else if (aop == 2 && aopcde == 9 && s == 1) 2395 return 0; 2396 else if (aop == 3 && aopcde == 9 && s == 0) 2397 return 0; 2398 else if (aopcde == 8) 2399 return 0; 2400 else if (aop == 0 && aopcde == 11) 2401 return DREG_MASK (dst0); 2402 else if (aop == 1 && aopcde == 11) 2403 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2404 else if (aopcde == 11) 2405 return 0; 2406 else if (aopcde == 22) 2407 return DREG_MASK (dst0); 2408 2409 else if ((aop == 0 || aop == 1) && aopcde == 14) 2410 return 0; 2411 else if (aop == 3 && HL == 0 && aopcde == 14) 2412 return 0; 2413 2414 else if (aop == 3 && HL == 0 && aopcde == 15) 2415 return DREG_MASK (dst0); 2416 2417 else if (aop == 1 && aopcde == 16) 2418 return 0; 2419 2420 else if (aop == 0 && aopcde == 16) 2421 return 0; 2422 2423 else if (aop == 3 && HL == 0 && aopcde == 16) 2424 return 0; 2425 2426 else if (aop == 3 && HL == 0 && aopcde == 7) 2427 return DREG_MASK (dst0); 2428 else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 7) 2429 return DREG_MASK (dst0); 2430 2431 else if (aop == 0 && aopcde == 12) 2432 return DREG_MASK (dst0); 2433 else if (aop == 1 && aopcde == 12) 2434 return DREG_MASK (dst0) | DREG_MASK (dst1); 2435 else if (aop == 3 && aopcde == 12) 2436 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2437 2438 else if (aopcde == 0) 2439 return DREG_MASK (dst0); 2440 else if (aopcde == 1) 2441 return DREG_MASK (dst0) | DREG_MASK (dst1); 2442 2443 else if (aop == 0 && aopcde == 10) 2444 return DREGL_MASK (dst0); 2445 else if (aop == 1 && aopcde == 10) 2446 return DREGL_MASK (dst0); 2447 2448 else if ((aop == 1 || aop == 0) && aopcde == 4) 2449 return DREG_MASK (dst0); 2450 else if (aop == 2 && aopcde == 4) 2451 return DREG_MASK (dst0) | DREG_MASK (dst1); 2452 2453 else if (aop == 0 && aopcde == 17) 2454 return DREG_MASK (dst0) | DREG_MASK (dst1); 2455 else if (aop == 1 && aopcde == 17) 2456 return DREG_MASK (dst0) | DREG_MASK (dst1); 2457 else if (aop == 0 && aopcde == 18) 2458 return 0; 2459 else if (aop == 3 && aopcde == 18) 2460 return 0; 2461 2462 else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 6) 2463 return DREG_MASK (dst0); 2464 2465 else if ((aop == 0 || aop == 1) && aopcde == 20) 2466 return DREG_MASK (dst0); 2467 2468 else if ((aop == 0 || aop == 1) && aopcde == 21) 2469 return DREG_MASK (dst0) | DREG_MASK (dst1); 2470 2471 else if (aop == 0 && aopcde == 23 && HL == 1) 2472 return DREG_MASK (dst0); 2473 else if (aop == 0 && aopcde == 23 && HL == 0) 2474 return DREG_MASK (dst0); 2475 2476 else if (aop == 0 && aopcde == 24) 2477 return DREG_MASK (dst0); 2478 else if (aop == 1 && aopcde == 24) 2479 return DREG_MASK (dst0) | DREG_MASK (dst1); 2480 else if (aopcde == 13) 2481 return DREG_MASK (dst0) | DREG_MASK (dst1); 2482 else 2483 return 0; 2484 2485 return 4; 2486 } 2487 2488 static int 2489 decode_dsp32shift_0 (int iw0, int iw1) 2490 { 2491 /* dsp32shift 2492 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2493 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| 2494 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| 2495 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2496 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); 2497 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); 2498 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); 2499 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); 2500 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); 2501 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask); 2502 2503 if (sop == 0 && sopcde == 0) 2504 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2505 else if (sop == 1 && sopcde == 0) 2506 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2507 else if (sop == 2 && sopcde == 0) 2508 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2509 else if (sop == 0 && sopcde == 3) 2510 return 0; 2511 else if (sop == 1 && sopcde == 3) 2512 return 0; 2513 else if (sop == 2 && sopcde == 3) 2514 return 0; 2515 else if (sop == 3 && sopcde == 3) 2516 return DREG_MASK (dst0); 2517 else if (sop == 0 && sopcde == 1) 2518 return DREG_MASK (dst0); 2519 else if (sop == 1 && sopcde == 1) 2520 return DREG_MASK (dst0); 2521 else if (sop == 2 && sopcde == 1) 2522 return DREG_MASK (dst0); 2523 else if (sopcde == 2) 2524 return DREG_MASK (dst0); 2525 else if (sopcde == 4) 2526 return DREG_MASK (dst0); 2527 else if (sop == 0 && sopcde == 5) 2528 return DREGL_MASK (dst0); 2529 else if (sop == 1 && sopcde == 5) 2530 return DREGL_MASK (dst0); 2531 else if (sop == 2 && sopcde == 5) 2532 return DREGL_MASK (dst0); 2533 else if (sop == 0 && sopcde == 6) 2534 return DREGL_MASK (dst0); 2535 else if (sop == 1 && sopcde == 6) 2536 return DREGL_MASK (dst0); 2537 else if (sop == 3 && sopcde == 6) 2538 return DREGL_MASK (dst0); 2539 else if (sop == 0 && sopcde == 7) 2540 return DREGL_MASK (dst0); 2541 else if (sop == 1 && sopcde == 7) 2542 return DREGL_MASK (dst0); 2543 else if (sop == 2 && sopcde == 7) 2544 return DREGL_MASK (dst0); 2545 else if (sop == 3 && sopcde == 7) 2546 return DREGL_MASK (dst0); 2547 else if (sop == 0 && sopcde == 8) 2548 return DREG_MASK (src0) | DREG_MASK (src1); 2549 #if 0 2550 { 2551 OUTS (outf, "BITMUX ("); 2552 OUTS (outf, dregs (src0)); 2553 OUTS (outf, ", "); 2554 OUTS (outf, dregs (src1)); 2555 OUTS (outf, ", A0) (ASR)"); 2556 } 2557 #endif 2558 else if (sop == 1 && sopcde == 8) 2559 return DREG_MASK (src0) | DREG_MASK (src1); 2560 #if 0 2561 { 2562 OUTS (outf, "BITMUX ("); 2563 OUTS (outf, dregs (src0)); 2564 OUTS (outf, ", "); 2565 OUTS (outf, dregs (src1)); 2566 OUTS (outf, ", A0) (ASL)"); 2567 } 2568 #endif 2569 else if (sopcde == 9) 2570 return sop < 2 ? DREGL_MASK (dst0) : DREG_MASK (dst0); 2571 else if (sopcde == 10) 2572 return DREG_MASK (dst0); 2573 else if (sop == 0 && sopcde == 11) 2574 return DREGL_MASK (dst0); 2575 else if (sop == 1 && sopcde == 11) 2576 return DREGL_MASK (dst0); 2577 else if (sop == 0 && sopcde == 12) 2578 return 0; 2579 else if (sop == 1 && sopcde == 12) 2580 return DREGL_MASK (dst0); 2581 else if (sop == 0 && sopcde == 13) 2582 return DREG_MASK (dst0); 2583 else if (sop == 1 && sopcde == 13) 2584 return DREG_MASK (dst0); 2585 else if (sop == 2 && sopcde == 13) 2586 return DREG_MASK (dst0); 2587 2588 abort (); 2589 } 2590 2591 static int 2592 decode_dsp32shiftimm_0 (int iw0, int iw1) 2593 { 2594 /* dsp32shiftimm 2595 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ 2596 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| 2597 |.sop...|.HLs...|.dst0......|.immag.................|.src1......| 2598 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ 2599 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); 2600 int bit8 = ((iw1 >> 8) & 0x1); 2601 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask); 2602 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask); 2603 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); 2604 2605 2606 if (sop == 0 && sopcde == 0) 2607 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2608 else if (sop == 1 && sopcde == 0 && bit8 == 0) 2609 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2610 else if (sop == 1 && sopcde == 0 && bit8 == 1) 2611 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2612 else if (sop == 2 && sopcde == 0 && bit8 == 0) 2613 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2614 else if (sop == 2 && sopcde == 0 && bit8 == 1) 2615 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0); 2616 else if (sop == 2 && sopcde == 3 && HLs == 1) 2617 return 0; 2618 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0) 2619 return 0; 2620 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1) 2621 return 0; 2622 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0) 2623 return 0; 2624 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1) 2625 return 0; 2626 else if (sop == 1 && sopcde == 3 && HLs == 0) 2627 return 0; 2628 else if (sop == 1 && sopcde == 3 && HLs == 1) 2629 return 0; 2630 else if (sop == 2 && sopcde == 3 && HLs == 0) 2631 return 0; 2632 else if (sop == 1 && sopcde == 1 && bit8 == 0) 2633 return DREG_MASK (dst0); 2634 else if (sop == 1 && sopcde == 1 && bit8 == 1) 2635 return DREG_MASK (dst0); 2636 else if (sop == 2 && sopcde == 1 && bit8 == 1) 2637 return DREG_MASK (dst0); 2638 else if (sop == 2 && sopcde == 1 && bit8 == 0) 2639 return DREG_MASK (dst0); 2640 else if (sop == 0 && sopcde == 1) 2641 return DREG_MASK (dst0); 2642 else if (sop == 1 && sopcde == 2) 2643 return DREG_MASK (dst0); 2644 else if (sop == 2 && sopcde == 2 && bit8 == 1) 2645 return DREG_MASK (dst0); 2646 else if (sop == 2 && sopcde == 2 && bit8 == 0) 2647 return DREG_MASK (dst0); 2648 else if (sop == 3 && sopcde == 2) 2649 return DREG_MASK (dst0); 2650 else if (sop == 0 && sopcde == 2) 2651 return DREG_MASK (dst0); 2652 2653 abort (); 2654 } 2655 2656 int 2657 insn_regmask (int iw0, int iw1) 2658 { 2659 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) 2660 return 0; /* MNOP */ 2661 else if ((iw0 & 0xff00) == 0x0000) 2662 return decode_ProgCtrl_0 (iw0); 2663 else if ((iw0 & 0xffc0) == 0x0240) 2664 abort (); 2665 else if ((iw0 & 0xff80) == 0x0100) 2666 abort (); 2667 else if ((iw0 & 0xfe00) == 0x0400) 2668 abort (); 2669 else if ((iw0 & 0xfe00) == 0x0600) 2670 abort (); 2671 else if ((iw0 & 0xf800) == 0x0800) 2672 abort (); 2673 else if ((iw0 & 0xffe0) == 0x0200) 2674 abort (); 2675 else if ((iw0 & 0xff00) == 0x0300) 2676 abort (); 2677 else if ((iw0 & 0xf000) == 0x1000) 2678 abort (); 2679 else if ((iw0 & 0xf000) == 0x2000) 2680 abort (); 2681 else if ((iw0 & 0xf000) == 0x3000) 2682 abort (); 2683 else if ((iw0 & 0xfc00) == 0x4000) 2684 abort (); 2685 else if ((iw0 & 0xfe00) == 0x4400) 2686 abort (); 2687 else if ((iw0 & 0xf800) == 0x4800) 2688 abort (); 2689 else if ((iw0 & 0xf000) == 0x5000) 2690 abort (); 2691 else if ((iw0 & 0xf800) == 0x6000) 2692 abort (); 2693 else if ((iw0 & 0xf800) == 0x6800) 2694 abort (); 2695 else if ((iw0 & 0xf000) == 0x8000) 2696 return decode_LDSTpmod_0 (iw0); 2697 else if ((iw0 & 0xff60) == 0x9e60) 2698 return decode_dagMODim_0 (iw0); 2699 else if ((iw0 & 0xfff0) == 0x9f60) 2700 return decode_dagMODik_0 (iw0); 2701 else if ((iw0 & 0xfc00) == 0x9c00) 2702 return decode_dspLDST_0 (iw0); 2703 else if ((iw0 & 0xf000) == 0x9000) 2704 return decode_LDST_0 (iw0); 2705 else if ((iw0 & 0xfc00) == 0xb800) 2706 return decode_LDSTiiFP_0 (iw0); 2707 else if ((iw0 & 0xe000) == 0xA000) 2708 return decode_LDSTii_0 (iw0); 2709 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000) 2710 abort (); 2711 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000) 2712 abort (); 2713 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000) 2714 abort (); 2715 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000) 2716 abort (); 2717 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000) 2718 abort (); 2719 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000) 2720 return decode_dsp32mac_0 (iw0, iw1); 2721 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000) 2722 return decode_dsp32mult_0 (iw0, iw1); 2723 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000) 2724 return decode_dsp32alu_0 (iw0, iw1); 2725 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000) 2726 return decode_dsp32shift_0 (iw0, iw1); 2727 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000) 2728 return decode_dsp32shiftimm_0 (iw0, iw1); 2729 else if ((iw0 & 0xff00) == 0xf800) 2730 abort (); 2731 else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000) 2732 abort (); 2733 2734 abort (); 2735 } 2736
