1 @c Copyright (C) 2000-2014 Free Software Foundation, Inc. 2 @c This is part of the GAS manual. 3 @c For copying conditions, see the file as.texinfo. 4 @ifset GENERIC 5 @page 6 @node i860-Dependent 7 @chapter Intel i860 Dependent Features 8 @end ifset 9 @ifclear GENERIC 10 @node Machine Dependencies 11 @chapter Intel i860 Dependent Features 12 @end ifclear 13 14 @ignore 15 @c FIXME: This is basically a stub for i860. There is tons more information 16 that I will add later (jle (a] cygnus.com). 17 @end ignore 18 19 @cindex i860 support 20 @menu 21 * Notes-i860:: i860 Notes 22 * Options-i860:: i860 Command-line Options 23 * Directives-i860:: i860 Machine Directives 24 * Opcodes for i860:: i860 Opcodes 25 * Syntax of i860:: i860 Syntax 26 @end menu 27 28 @node Notes-i860 29 @section i860 Notes 30 This is a fairly complete i860 assembler which is compatible with the 31 UNIX System V/860 Release 4 assembler. However, it does not currently 32 support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}). 33 34 Like the SVR4/860 assembler, the output object format is ELF32. Currently, 35 this is the only supported object format. If there is sufficient interest, 36 other formats such as COFF may be implemented. 37 38 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 39 being the default. One difference is that AT&T syntax requires the '%' 40 prefix on register names while Intel syntax does not. Another difference 41 is in the specification of relocatable expressions. The Intel syntax 42 is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha} 43 (and similarly for the "l" and "h" selectors). 44 @node Options-i860 45 @section i860 Command-line Options 46 @subsection SVR4 compatibility options 47 @table @code 48 @item -V 49 Print assembler version. 50 @item -Qy 51 Ignored. 52 @item -Qn 53 Ignored. 54 @end table 55 @subsection Other options 56 @table @code 57 @item -EL 58 Select little endian output (this is the default). 59 @item -EB 60 Select big endian output. Note that the i860 always reads instructions 61 as little endian data, so this option only effects data and not 62 instructions. 63 @item -mwarn-expand 64 Emit a warning message if any pseudo-instruction expansions occurred. 65 For example, a @code{or} instruction with an immediate larger than 16-bits 66 will be expanded into two instructions. This is a very undesirable feature to 67 rely on, so this flag can help detect any code where it happens. One 68 use of it, for instance, has been to find and eliminate any place 69 where @code{gcc} may emit these pseudo-instructions. 70 @item -mxp 71 Enable support for the i860XP instructions and control registers. By default, 72 this option is disabled so that only the base instruction set (i.e., i860XR) 73 is supported. 74 @item -mintel-syntax 75 The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the 76 Intel syntax. 77 @end table 78 79 @node Directives-i860 80 @section i860 Machine Directives 81 82 @cindex machine directives, i860 83 @cindex i860 machine directives 84 85 @table @code 86 @cindex @code{dual} directive, i860 87 @item .dual 88 Enter dual instruction mode. While this directive is supported, the 89 preferred way to use dual instruction mode is to explicitly code 90 the dual bit with the @code{d.} prefix. 91 @end table 92 93 @table @code 94 @cindex @code{enddual} directive, i860 95 @item .enddual 96 Exit dual instruction mode. While this directive is supported, the 97 preferred way to use dual instruction mode is to explicitly code 98 the dual bit with the @code{d.} prefix. 99 @end table 100 101 @table @code 102 @cindex @code{atmp} directive, i860 103 @item .atmp 104 Change the temporary register used when expanding pseudo operations. The 105 default register is @code{r31}. 106 @end table 107 108 The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode. 109 110 Both syntaxes allow for the standard @code{.align} directive. However, 111 the Intel syntax additionally allows keywords for the alignment 112 parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long}, 113 @code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4, 114 16, 4, and 8, respectively. 115 116 @node Opcodes for i860 117 @section i860 Opcodes 118 119 @cindex opcodes, i860 120 @cindex i860 opcodes 121 All of the Intel i860XR and i860XP machine instructions are supported. Please see 122 either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information. 123 @subsection Other instruction support (pseudo-instructions) 124 For compatibility with some other i860 assemblers, a number of 125 pseudo-instructions are supported. While these are supported, they are 126 a very undesirable feature that should be avoided -- in particular, when 127 they result in an expansion to multiple actual i860 instructions. Below 128 are the pseudo-instructions that result in expansions. 129 @itemize @bullet 130 @item Load large immediate into general register: 131 132 The pseudo-instruction @code{mov imm,%rn} (where the immediate does 133 not fit within a signed 16-bit field) will be expanded into: 134 @smallexample 135 orh large_imm@@h,%r0,%rn 136 or large_imm@@l,%rn,%rn 137 @end smallexample 138 @item Load/store with relocatable address expression: 139 140 For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn} 141 will be expanded into: 142 @smallexample 143 orh addr_exp@@ha,%rx,%r31 144 ld.l addr_exp@@l(%r31),%rn 145 @end smallexample 146 147 The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well. 148 @item Signed large immediate with add/subtract: 149 150 If any of the arithmetic operations @code{adds, addu, subs, subu} are used 151 with an immediate larger than 16-bits (signed), then they will be expanded. 152 For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to: 153 @smallexample 154 orh large_imm@@h,%r0,%r31 155 or large_imm@@l,%r31,%r31 156 adds %r31,%rx,%rn 157 @end smallexample 158 @item Unsigned large immediate with logical operations: 159 160 Logical operations (@code{or, andnot, or, xor}) also result in expansions. 161 The pseudo-instruction @code{or large_imm,%rx,%rn} results in: 162 @smallexample 163 orh large_imm@@h,%rx,%r31 164 or large_imm@@l,%r31,%rn 165 @end smallexample 166 167 Similarly for the others, except for @code{and} which expands to: 168 @smallexample 169 andnot (-1 - large_imm)@@h,%rx,%r31 170 andnot (-1 - large_imm)@@l,%r31,%rn 171 @end smallexample 172 @end itemize 173 174 @node Syntax of i860 175 @section i860 Syntax 176 @menu 177 * i860-Chars:: Special Characters 178 @end menu 179 180 @node i860-Chars 181 @subsection Special Characters 182 183 @cindex line comment character, i860 184 @cindex i860 line comment character 185 The presence of a @samp{#} appearing anywhere on a line indicates the 186 start of a comment that extends to the end of that line. 187 188 If a @samp{#} appears as the first character of a line then the whole 189 line is treated as a comment, but in this case the line can also be a 190 logical line number directive (@pxref{Comments}) or a preprocessor 191 control command (@pxref{Preprocessing}). 192 193 @cindex line separator, i860 194 @cindex statement separator, i860 195 @cindex i860 line separator 196 The @samp{;} character can be used to separate statements on the same 197 line. 198
