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      1 /* ia64.h -- Header file for ia64 opcode table
      2    Copyright (C) 1998-2014 Free Software Foundation, Inc.
      3    Contributed by David Mosberger-Tang <davidm (at) hpl.hp.com>
      4 
      5    This file is part of BFD, the Binary File Descriptor library.
      6 
      7    This program is free software; you can redistribute it and/or modify
      8    it under the terms of the GNU General Public License as published by
      9    the Free Software Foundation; either version 3 of the License, or
     10    (at your option) any later version.
     11 
     12    This program is distributed in the hope that it will be useful,
     13    but WITHOUT ANY WARRANTY; without even the implied warranty of
     14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15    GNU General Public License for more details.
     16 
     17    You should have received a copy of the GNU General Public License
     18    along with this program; if not, write to the Free Software Foundation,
     19    Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
     20 
     21 #ifndef opcode_ia64_h
     22 #define opcode_ia64_h
     23 
     24 #include <sys/types.h>
     25 
     26 #include "bfd.h"
     27 
     28 
     29 typedef BFD_HOST_U_64_BIT ia64_insn;
     30 
     31 enum ia64_insn_type
     32   {
     33     IA64_TYPE_NIL = 0,	/* illegal type */
     34     IA64_TYPE_A,	/* integer alu (I- or M-unit) */
     35     IA64_TYPE_I,	/* non-alu integer (I-unit) */
     36     IA64_TYPE_M,	/* memory (M-unit) */
     37     IA64_TYPE_B,	/* branch (B-unit) */
     38     IA64_TYPE_F,	/* floating-point (F-unit) */
     39     IA64_TYPE_X,	/* long encoding (X-unit) */
     40     IA64_TYPE_DYN,	/* Dynamic opcode */
     41     IA64_NUM_TYPES
     42   };
     43 
     44 enum ia64_unit
     45   {
     46     IA64_UNIT_NIL = 0,	/* illegal unit */
     47     IA64_UNIT_I,	/* integer unit */
     48     IA64_UNIT_M,	/* memory unit */
     49     IA64_UNIT_B,	/* branching unit */
     50     IA64_UNIT_F,	/* floating-point unit */
     51     IA64_UNIT_L,	/* long "unit" */
     52     IA64_UNIT_X,	/* may be integer or branch unit */
     53     IA64_NUM_UNITS
     54   };
     55 
     56 /* Changes to this enumeration must be propagated to the operand table in
     57    bfd/cpu-ia64-opc.c
     58  */
     59 enum ia64_opnd
     60   {
     61     IA64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
     62 
     63     /* constants */
     64     IA64_OPND_AR_CSD,	/* application register csd (ar.csd) */
     65     IA64_OPND_AR_CCV,	/* application register ccv (ar.ccv) */
     66     IA64_OPND_AR_PFS,	/* application register pfs (ar.pfs) */
     67     IA64_OPND_C1,	/* the constant 1 */
     68     IA64_OPND_C8,	/* the constant 8 */
     69     IA64_OPND_C16,	/* the constant 16 */
     70     IA64_OPND_GR0,	/* gr0 */
     71     IA64_OPND_IP,	/* instruction pointer (ip) */
     72     IA64_OPND_PR,	/* predicate register (pr) */
     73     IA64_OPND_PR_ROT,	/* rotating predicate register (pr.rot) */
     74     IA64_OPND_PSR,	/* processor status register (psr) */
     75     IA64_OPND_PSR_L,	/* processor status register L (psr.l) */
     76     IA64_OPND_PSR_UM,	/* processor status register UM (psr.um) */
     77 
     78     /* register operands: */
     79     IA64_OPND_AR3,	/* third application register # (bits 20-26) */
     80     IA64_OPND_B1,	/* branch register # (bits 6-8) */
     81     IA64_OPND_B2,	/* branch register # (bits 13-15) */
     82     IA64_OPND_CR3,	/* third control register # (bits 20-26) */
     83     IA64_OPND_F1,	/* first floating-point register # */
     84     IA64_OPND_F2,	/* second floating-point register # */
     85     IA64_OPND_F3,	/* third floating-point register # */
     86     IA64_OPND_F4,	/* fourth floating-point register # */
     87     IA64_OPND_P1,	/* first predicate # */
     88     IA64_OPND_P2,	/* second predicate # */
     89     IA64_OPND_R1,	/* first register # */
     90     IA64_OPND_R2,	/* second register # */
     91     IA64_OPND_R3,	/* third register # */
     92     IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
     93     IA64_OPND_DAHR3,	/* dahr reg # ( bits 23-25) */
     94 
     95     /* memory operands: */
     96     IA64_OPND_MR3,	/* memory at addr of third register # */
     97 
     98     /* indirect operands: */
     99     IA64_OPND_CPUID_R3,	/* cpuid[reg] */
    100     IA64_OPND_DBR_R3,	/* dbr[reg] */
    101     IA64_OPND_DTR_R3,	/* dtr[reg] */
    102     IA64_OPND_ITR_R3,	/* itr[reg] */
    103     IA64_OPND_IBR_R3,	/* ibr[reg] */
    104     IA64_OPND_MSR_R3,	/* msr[reg] */
    105     IA64_OPND_PKR_R3,	/* pkr[reg] */
    106     IA64_OPND_PMC_R3,	/* pmc[reg] */
    107     IA64_OPND_PMD_R3,	/* pmd[reg] */
    108     IA64_OPND_DAHR_R3,	/* dahr[reg] */
    109     IA64_OPND_RR_R3,	/* rr[reg] */
    110 
    111     /* immediate operands: */
    112     IA64_OPND_CCNT5,	/* 5-bit count (31 - bits 20-24) */
    113     IA64_OPND_CNT2a,	/* 2-bit count (1 + bits 27-28) */
    114     IA64_OPND_CNT2b,	/* 2-bit count (bits 27-28): 1, 2, 3 */
    115     IA64_OPND_CNT2c,	/* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
    116     IA64_OPND_CNT5,	/* 5-bit count (bits 14-18) */
    117     IA64_OPND_CNT6,	/* 6-bit count (bits 27-32) */
    118     IA64_OPND_CPOS6a,	/* 6-bit count (63 - bits 20-25) */
    119     IA64_OPND_CPOS6b,	/* 6-bit count (63 - bits 14-19) */
    120     IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */
    121     IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */
    122     IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */
    123     IA64_OPND_IMMU5b,	/* unsigned 5-bit immediate (32 + bits 14-18) */
    124     IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */
    125     IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */
    126     IA64_OPND_SOF,	/* 8-bit stack frame size */
    127     IA64_OPND_SOL,	/* 8-bit size of locals */
    128     IA64_OPND_SOR,	/* 6-bit number of rotating registers (scaled by 8) */
    129     IA64_OPND_IMM8,	/* signed 8-bit immediate (bits 13-19 & 36) */
    130     IA64_OPND_IMM8U4,	/* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
    131     IA64_OPND_IMM8M1,	/* signed 8-bit immediate -1 (bits 13-19 & 36) */
    132     IA64_OPND_IMM8M1U4,	/* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
    133     IA64_OPND_IMM8M1U8,	/* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
    134     IA64_OPND_IMMU9,	/* unsigned 9-bit immediate (bits 33-34, 20-26) */
    135     IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */
    136     IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */
    137     IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */
    138     IA64_OPND_IMMU16,	/* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */
    139     IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
    140     IA64_OPND_IMMU19,	/* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */
    141     IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */
    142     IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */
    143     IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
    144     IA64_OPND_IMM44,	/* signed 44-bit immediate (2^16*bits 6-32, 36) */
    145     IA64_OPND_IMMU62,	/* unsigned 62-bit immediate */
    146     IA64_OPND_IMMU64,	/* unsigned 64-bit immediate (lotsa bits...) */
    147     IA64_OPND_INC3,	/* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
    148     IA64_OPND_LEN4,	/* 4-bit count (bits 27-30 + 1) */
    149     IA64_OPND_LEN6,	/* 6-bit count (bits 27-32 + 1) */
    150     IA64_OPND_MBTYPE4,	/* 4-bit mux type (bits 20-23) */
    151     IA64_OPND_MHTYPE8,	/* 8-bit mux type (bits 20-27) */
    152     IA64_OPND_POS6,	/* 6-bit count (bits 14-19) */
    153     IA64_OPND_TAG13,	/* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
    154     IA64_OPND_TAG13b,	/* signed 13-bit tag (ip + 16*bits 24-32) */
    155     IA64_OPND_TGT25,	/* signed 25-bit (ip + 16*bits 6-25, 36) */
    156     IA64_OPND_TGT25b,	/* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
    157     IA64_OPND_TGT25c,	/* signed 25-bit (ip + 16*bits 13-32, 36) */
    158     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
    159     IA64_OPND_LDXMOV,	/* any symbol, generates R_IA64_LDXMOV.  */
    160 
    161     IA64_OPND_CNT6a,	/* 6-bit count  (bits 6-11) */
    162     IA64_OPND_STRD5b,	/* 5-bit stride (bits 13-17) */
    163 
    164     IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
    165   };
    166 
    167 enum ia64_dependency_mode
    168 {
    169   IA64_DV_RAW,
    170   IA64_DV_WAW,
    171   IA64_DV_WAR,
    172 };
    173 
    174 enum ia64_dependency_semantics
    175 {
    176   IA64_DVS_NONE,
    177   IA64_DVS_IMPLIED,
    178   IA64_DVS_IMPLIEDF,
    179   IA64_DVS_DATA,
    180   IA64_DVS_INSTR,
    181   IA64_DVS_SPECIFIC,
    182   IA64_DVS_STOP,
    183   IA64_DVS_OTHER,
    184 };
    185 
    186 enum ia64_resource_specifier
    187 {
    188   IA64_RS_ANY,
    189   IA64_RS_AR_K,
    190   IA64_RS_AR_UNAT,
    191   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
    192   IA64_RS_ARb, /* 48-63, 112-127 */
    193   IA64_RS_BR,
    194   IA64_RS_CFM,
    195   IA64_RS_CPUID,
    196   IA64_RS_CR_IIB,
    197   IA64_RS_CR_IRR,
    198   IA64_RS_CR_LRR,
    199   IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
    200   IA64_RS_DAHR,
    201   IA64_RS_DBR,
    202   IA64_RS_FR,
    203   IA64_RS_FRb,
    204   IA64_RS_GR0,
    205   IA64_RS_GR,
    206   IA64_RS_IBR,
    207   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
    208   IA64_RS_MSR,
    209   IA64_RS_PKR,
    210   IA64_RS_PMC,
    211   IA64_RS_PMD,
    212   IA64_RS_PR,  /* non-rotating, 1-15 */
    213   IA64_RS_PRr, /* rotating, 16-62 */
    214   IA64_RS_PR63,
    215   IA64_RS_RR,
    216 
    217   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
    218   IA64_RS_CRX, /* CRs not in RS_CR */
    219   IA64_RS_PSR, /* PSR bits */
    220   IA64_RS_RSE, /* implementation-specific RSE resources */
    221   IA64_RS_AR_FPSR,
    222 
    223 };
    224 
    225 enum ia64_rse_resource
    226 {
    227   IA64_RSE_N_STACKED_PHYS,
    228   IA64_RSE_BOF,
    229   IA64_RSE_STORE_REG,
    230   IA64_RSE_LOAD_REG,
    231   IA64_RSE_BSPLOAD,
    232   IA64_RSE_RNATBITINDEX,
    233   IA64_RSE_CFLE,
    234   IA64_RSE_NDIRTY,
    235 };
    236 
    237 /* Information about a given resource dependency */
    238 struct ia64_dependency
    239 {
    240   /* Name of the resource */
    241   const char *name;
    242   /* Does this dependency need further specification? */
    243   enum ia64_resource_specifier specifier;
    244   /* Mode of dependency */
    245   enum ia64_dependency_mode mode;
    246   /* Dependency semantics */
    247   enum ia64_dependency_semantics semantics;
    248   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
    249 #define REG_NONE (-1)
    250   int regindex;
    251   /* Special info on semantics */
    252   const char *info;
    253 };
    254 
    255 /* Two arrays of indexes into the ia64_dependency table.
    256    chks are dependencies to check for conflicts when an opcode is
    257    encountered; regs are dependencies to register (mark as used) when an
    258    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
    259    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
    260    readers (WAR) of a resource.  */
    261 struct ia64_opcode_dependency
    262 {
    263   int nchks;
    264   const unsigned short *chks;
    265   int nregs;
    266   const unsigned short *regs;
    267 };
    268 
    269 /* encode/extract the note/index for a dependency */
    270 #define RDEP(N,X) (((N)<<11)|(X))
    271 #define NOTE(X) (((X)>>11)&0x1F)
    272 #define DEP(X) ((X)&0x7FF)
    273 
    274 /* A template descriptor describes the execution units that are active
    275    for each of the three slots.  It also specifies the location of
    276    instruction group boundaries that may be present between two slots.  */
    277 struct ia64_templ_desc
    278   {
    279     int group_boundary;	/* 0=no boundary, 1=between slot 0 & 1, etc. */
    280     enum ia64_unit exec_unit[3];
    281     const char *name;
    282   };
    283 
    284 /* The opcode table is an array of struct ia64_opcode.  */
    285 
    286 struct ia64_opcode
    287   {
    288     /* The opcode name.  */
    289     const char *name;
    290 
    291     /* The type of the instruction: */
    292     enum ia64_insn_type type;
    293 
    294     /* Number of output operands: */
    295     int num_outputs;
    296 
    297     /* The opcode itself.  Those bits which will be filled in with
    298        operands are zeroes.  */
    299     ia64_insn opcode;
    300 
    301     /* The opcode mask.  This is used by the disassembler.  This is a
    302        mask containing ones indicating those bits which must match the
    303        opcode field, and zeroes indicating those bits which need not
    304        match (and are presumably filled in by operands).  */
    305     ia64_insn mask;
    306 
    307     /* An array of operand codes.  Each code is an index into the
    308        operand table.  They appear in the order which the operands must
    309        appear in assembly code, and are terminated by a zero.  */
    310     enum ia64_opnd operands[5];
    311 
    312     /* One bit flags for the opcode.  These are primarily used to
    313        indicate specific processors and environments support the
    314        instructions.  The defined values are listed below. */
    315     unsigned int flags;
    316 
    317     /* Used by ia64_find_next_opcode (). */
    318     short ent_index;
    319 
    320     /* Opcode dependencies. */
    321     const struct ia64_opcode_dependency *dependencies;
    322   };
    323 
    324 /* Values defined for the flags field of a struct ia64_opcode.  */
    325 
    326 #define IA64_OPCODE_FIRST	(1<<0)	/* must be first in an insn group */
    327 #define IA64_OPCODE_X_IN_MLX	(1<<1)	/* insn is allowed in X slot of MLX */
    328 #define IA64_OPCODE_LAST	(1<<2)	/* must be last in an insn group */
    329 #define IA64_OPCODE_PRIV	(1<<3)	/* privileged instruct */
    330 #define IA64_OPCODE_SLOT2	(1<<4)	/* insn allowed in slot 2 only */
    331 #define IA64_OPCODE_NO_PRED	(1<<5)	/* insn cannot be predicated */
    332 #define IA64_OPCODE_PSEUDO	(1<<6)	/* insn is a pseudo-op */
    333 #define IA64_OPCODE_F2_EQ_F3	(1<<7)	/* constraint: F2 == F3 */
    334 #define IA64_OPCODE_LEN_EQ_64MCNT	(1<<8)	/* constraint: LEN == 64-CNT */
    335 #define IA64_OPCODE_MOD_RRBS    (1<<9)	/* modifies all rrbs in CFM */
    336 #define IA64_OPCODE_POSTINC	(1<<10)	/* postincrement MR3 operand */
    337 
    338 /* A macro to extract the major opcode from an instruction.  */
    339 #define IA64_OP(i)	(((i) >> 37) & 0xf)
    340 
    341 enum ia64_operand_class
    342   {
    343     IA64_OPND_CLASS_CST,	/* constant */
    344     IA64_OPND_CLASS_REG,	/* register */
    345     IA64_OPND_CLASS_IND,	/* indirect register */
    346     IA64_OPND_CLASS_ABS,	/* absolute value */
    347     IA64_OPND_CLASS_REL,	/* IP-relative value */
    348   };
    349 
    350 /* The operands table is an array of struct ia64_operand.  */
    351 
    352 struct ia64_operand
    353 {
    354   enum ia64_operand_class op_class;
    355 
    356   /* Set VALUE as the operand bits for the operand of type SELF in the
    357      instruction pointed to by CODE.  If an error occurs, *CODE is not
    358      modified and the returned string describes the cause of the
    359      error.  If no error occurs, NULL is returned.  */
    360   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
    361 			 ia64_insn *code);
    362 
    363   /* Extract the operand bits for an operand of type SELF from
    364      instruction CODE store them in *VALUE.  If an error occurs, the
    365      cause of the error is described by the string returned.  If no
    366      error occurs, NULL is returned.  */
    367   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
    368 			  ia64_insn *value);
    369 
    370   /* A string whose meaning depends on the operand class.  */
    371 
    372   const char *str;
    373 
    374   struct bit_field
    375     {
    376       /* The number of bits in the operand.  */
    377       int bits;
    378 
    379       /* How far the operand is left shifted in the instruction.  */
    380       int shift;
    381     }
    382   field[4];		/* no operand has more than this many bit-fields */
    383 
    384   unsigned int flags;
    385 
    386   const char *desc;	/* brief description */
    387 };
    388 
    389 /* Values defined for the flags field of a struct ia64_operand.  */
    390 
    391 /* Disassemble as signed decimal (instead of hex): */
    392 #define IA64_OPND_FLAG_DECIMAL_SIGNED	(1<<0)
    393 /* Disassemble as unsigned decimal (instead of hex): */
    394 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED	(1<<1)
    395 
    396 extern const struct ia64_templ_desc ia64_templ_desc[16];
    397 
    398 /* The tables are sorted by major opcode number and are otherwise in
    399    the order in which the disassembler should consider instructions.  */
    400 extern struct ia64_opcode ia64_opcodes_a[];
    401 extern struct ia64_opcode ia64_opcodes_i[];
    402 extern struct ia64_opcode ia64_opcodes_m[];
    403 extern struct ia64_opcode ia64_opcodes_b[];
    404 extern struct ia64_opcode ia64_opcodes_f[];
    405 extern struct ia64_opcode ia64_opcodes_d[];
    406 
    407 
    408 extern struct ia64_opcode *ia64_find_opcode (const char *);
    409 extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *);
    410 
    411 extern struct ia64_opcode *ia64_dis_opcode (ia64_insn,
    412 					    enum ia64_insn_type);
    413 
    414 extern void ia64_free_opcode (struct ia64_opcode *);
    415 extern const struct ia64_dependency *ia64_find_dependency (int);
    416 
    417 /* To avoid circular library dependencies, this array is implemented
    418    in bfd/cpu-ia64-opc.c: */
    419 extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
    420 
    421 #endif /* opcode_ia64_h */
    422