Lines Matching refs:Scheduled
45 // the instructions cannot be scheduled in a given MII, we increase the MII by
117 cl::desc("Maximum stages allowed in the generated scheduled."),
201 bool Scheduled;
264 Scheduled(false), Loop(L), LIS(lis), RegClassInfo(rci),
270 /// Return true if the loop kernel has been scheduled.
271 bool hasNewSchedule() { return Scheduled; }
273 /// Return the earliest time an instruction may be scheduled.
276 /// Return the latest time an instruction my be scheduled.
280 /// an instruction may be scheduled.
522 /// This class repesents the scheduled code. The main data structure is a
523 /// map from scheduled cycle to instructions. During scheduling, the
541 /// scheduled before the Phi.
597 /// Return the cycle of the earliest scheduled instruction in the dependence
601 /// Return the cycle of the latest scheduled instruction in the dependence
614 /// Return true if the instruction is scheduled at the specified stage.
619 /// Return the stage for a scheduled instruction. Return -1 if
620 /// the instruction has not been scheduled.
628 /// Return the cycle for a scheduled instruction. This function normalizes
632 assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled.");
653 /// This is not the case if the loop value is scheduled prior to the
663 /// Return the instructions that are scheduled at the specified cycle.
887 Scheduled = schedulePipeline(Schedule);
889 if (!Scheduled)
1936 /// Remove nodes that have been scheduled in previous NodeSets.
1961 /// indicates the order that the nodes will be scheduled. This is a
2131 // upon the scheduled time for any predecessors/successors.
2214 // the iteration, or stage, that the instruction is scheduled in. This is
2520 // and the distance from where the Phi is first scheduled.
2524 // state. If the Phi has not been scheduled in current prolog, then we
2537 // been completely scheduled prior to the epilog, and Phi value is not
2544 // are scheduled in different stages.
2548 // If the Phi hasn't been scheduled, then use the initial Phi operand
2549 // value. Otherwise, use the scheduled version of the instruction. This
2553 // Check if the Phi has already been scheduled in a prolog stage.
2557 // Check if the Phi has already been scheduled, but the loop intruction
2593 // instruction is scheduled in the previous block.
2621 scheduled in an
2668 // we need to rename the Phi values in scheduled instructions.
2675 // If the Phi has been scheduled, use the new name for rewriting.
2683 // register to replace depends on whether the Phi is scheduled in the
2709 /// These are new Phis needed because the definition is scheduled after the
2740 assert(StageScheduled != -1 && "Expecting scheduled instruction.");
2743 // An instruction scheduled in stage 0 and is used after the loop
3194 // The loop value hasn't yet been scheduled.
3197 // The loop value is another phi, which has not been scheduled.
3200 // The loop value is another phi, which has been scheduled.
3209 /// from the initial operand. Once the Phi is scheduled, we switch
3243 /// Rewrite a previously scheduled instruction to use the register value
3252 // Rewrite uses that have been scheduled already to use the new
3269 assert(OrigInstr != InstrMap.end() && "Instruction not scheduled.");
3274 // This is the stage for the scheduled instruction.
3285 // The scheduled instruction occurs before the scheduled Phi, and the
3453 /// returns true if the node is scheduled. This routine may search either
3466 // Add the already scheduled instructions at the specified cycle to the DFA.
3478 "These instructions have already been scheduled.");
3505 // Return the cycle of the earliest scheduled instruction in the chain.
3528 // Return the cycle of the latest scheduled instruction in the chain.
3564 /// depends on any predecessor or successor nodes scheduled already.
3568 // Iterate over each instruction that has been scheduled already. The start
3569 // slot computuation depends on whether the previously scheduled instruction
3595 // the dependent instruction is not scheduled past the definition.
3658 // Add the instruction after the scheduled instruction.
3677 // Add the instruction before the scheduled instruction.
3765 /// Return true if the scheduled Phi has a loop carried operand.
3818 // an instruction that uses a physical register is scheduled in a
3828 assert(StageDef != -1 && "Instruction should have been scheduled.");
3890 // remain in the scheduled list, and it contains all the instructions.
