Lines Matching refs:Imm
165 bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
193 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
206 bool LHSIsKill, uint64_t Imm);
210 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
220 uint64_t Imm, bool IsZExt = true);
224 uint64_t Imm, bool IsZExt = true);
228 uint64_t Imm, bool IsZExt = false);
366 int Imm =
368 assert((Imm != -1) && "Cannot encode floating-point constant.");
370 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
1135 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1137 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1140 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1270 bool LHSIsKill, uint64_t Imm,
1278 if (isUInt<12>(Imm))
1280 else if ((Imm & 0xfff000) == Imm) {
1282 Imm >>= 12;
1309 .addImm(Imm)
1427 uint64_t Imm) {
1428 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1479 int64_t Imm) {
1481 if (Imm < 0)
1482 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1484 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1489 unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm);
1544 uint64_t Imm = C->getZExtValue();
1545 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1606 uint64_t Imm) {
1637 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1642 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
1694 uint64_t Imm) {
1695 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
2363 uint64_t Imm = CI->getZExtValue();
2364 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
2681 // Emit a TST instruction (ANDS wzr, reg, #imm).
4259 unsigned Imm = 0;
4271 Imm = 7;
4278 Imm = 15;
4283 Imm = 31;
4302 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
