Lines Matching refs:WZR
345 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
486 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1258 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1303 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1343 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1386 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
2053 if (VTIsi1 && SrcReg != AArch64::WZR) {
2098 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2102 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2454 .addReg(AArch64::WZR, getKillRegState(true));
2494 .addReg(AArch64::WZR, getKillRegState(true))
2495 .addReg(AArch64::WZR, getKillRegState(true))
2500 .addReg(AArch64::WZR, getKillRegState(true))
2513 .addReg(AArch64::WZR, getKillRegState(true))
2514 .addReg(AArch64::WZR, getKillRegState(true))
2681 // Emit a TST instruction (ANDS wzr, reg, #imm).
2683 AArch64::WZR)
3656 AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
3877 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
4800 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
