Lines Matching defs:Opcode
699 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
700 setOperationAction(Opcode, VT, Legal);
704 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
706 setOperationAction(Opcode, VT, Legal);
833 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
834 switch ((AArch64ISD::NodeType)Opcode) {
1223 unsigned Opcode = AArch64ISD::SUBS;
1237 Opcode = AArch64ISD::ADDS;
1244 Opcode = AArch64ISD::ANDS;
1249 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1300 unsigned Opcode = 0;
1307 Opcode = AArch64ISD::FCCMP;
1312 Opcode = AArch64ISD::CCMN;
1316 if (Opcode == 0)
1317 Opcode = AArch64ISD::CCMP;
1323 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1336 unsigned Opcode = Val->getOpcode();
1337 if (Opcode == ISD::SETCC) {
1346 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1356 if (Opcode == ISD::OR) {
1394 unsigned Opcode = Val->getOpcode();
1395 if (Opcode == ISD::SETCC) {
1431 assert((Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) &&
1440 bool NegateOpsAndResult = Opcode == ISD::OR;
2190 unsigned Opcode = N->getOpcode();
2191 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2201 unsigned Opcode = N->getOpcode();
2202 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
3952 unsigned Opcode = AArch64ISD::CSEL;
3992 Opcode = AArch64ISD::CSINV;
3994 Opcode = AArch64ISD::CSNEG;
4005 Opcode = AArch64ISD::CSINC;
4013 Opcode = AArch64ISD::CSINC;
4027 if (Opcode != AArch64ISD::CSEL) {
4038 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
4562 const AArch64TargetLowering::DAGCombinerInfo &DCI, unsigned Opcode,
4570 RecipOp = Opcode == (AArch64ISD::FRECPE) ? "div": "sqrt";
4579 return DCI.DAG.getNode(Opcode, SDLoc(Operand), VT, Operand);
4929 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5440 llvm_unreachable("Unknown shuffle opcode!");
5458 unsigned Opcode;
5460 Opcode = AArch64ISD::DUPLANE8;
5462 Opcode = AArch64ISD::DUPLANE16;
5464 Opcode = AArch64ISD::DUPLANE32;
5466 Opcode = AArch64ISD::DUPLANE64;
5473 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5610 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5625 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5866 unsigned Opcode = N->getOpcode();
5867 switch (Opcode) {
6049 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6354 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6355 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6447 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6481 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6635 llvm_unreachable("unexpected shift opcode");
7675 unsigned Opcode =
7677 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
8465 unsigned Opcode;
8471 Opcode = AArch64ISD::SQSHL_I;
8475 Opcode = AArch64ISD::UQSHL_I;
8479 Opcode = AArch64ISD::SRSHR_I;
8483 Opcode = AArch64ISD::URSHR_I;
8487 Opcode = AArch64ISD::SQSHLU_I;
8494 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8498 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
9008 unsigned Opcode;
9015 Opcode = AArch64ISD::UADDV;
9018 Opcode = AArch64ISD::SMAXV;
9021 Opcode = AArch64ISD::UMAXV;
9024 Opcode = AArch64ISD::SMINV;
9027 Opcode = AArch64ISD::UMINV;
9030 Opcode = Intrinsic::aarch64_neon_fmaxnmv;
9034 Opcode = Intrinsic::aarch64_neon_fminnmv;
9042 DAG.getConstant(Opcode, DL, MVT::i32), PreOp)
9045 DAG.getNode(Opcode, DL, PreOp.getSimpleValueType(), PreOp),
9224 // Find the new opcode for the updating load/store.
