Lines Matching full:v2i64
98 addQRTypeForNEON(MVT::v2i64);
572 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
573 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
580 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
589 setOperationAction(ISD::CTTZ, MVT::v2i64, Expand);
592 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
596 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
643 AddPromotedToType(ISD::LOAD, VT, MVT::v2i64);
646 AddPromotedToType(ISD::STORE, VT, MVT::v2i64);
698 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
820 // Disregard v2i64. Memcpy lowering produces those and splitting
822 VT == MVT::v2i64;
2213 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2247 if (VT == MVT::v2i64)
3777 VecVT = MVT::v2i64;
3804 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
6099 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
6458 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6492 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
7250 // instruction to materialize the v2i64 zero and one store (with restrictive
7727 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
7798 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
7987 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
8051 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
8052 // (v2i16 (truncate (v2i64)))))
8054 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
8055 // (v4i32 (bitcast (v2i64))),
8059 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
8068 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
8070 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
8158 else if (Vec.getValueType() == MVT::v2i64)
8413 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8414 // (extract_high (v2i64 (dup128 scalar)))))
8769 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8771 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
