Lines Matching refs:RegWidth
586 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum);
587 bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidth);
741 static int getRegClass(RegisterKind Is, unsigned RegWidth) {
743 switch (RegWidth) {
753 switch (RegWidth) {
760 switch (RegWidth) {
804 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum)
808 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { Reg = AMDGPU::EXEC; RegWidth = 2; return true; }
809 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { Reg = AMDGPU::FLAT_SCR; RegWidth = 2; return true; }
810 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { Reg = AMDGPU::VCC; RegWidth = 2; return true; }
811 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { Reg = AMDGPU::TBA; RegWidth = 2; return true; }
812 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { Reg = AMDGPU::TMA; RegWidth = 2; return true; }
817 if (Reg1 != Reg + RegWidth) { return false; }
818 RegWidth++;
825 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidth)
852 RegWidth = 1;
880 RegWidth = (RegHi - RegLo) + 1;
886 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
888 if (RegWidth != 1)
905 if (!AddNextRegisterToList(Reg, RegWidth, RegKind1, Reg1, RegNum1)) {
918 RegWidth = 1;
927 Size = std::min(RegWidth, 4u);
932 int RCID = getRegClass(RegKind, RegWidth);
958 unsigned Reg, RegNum, RegWidth;
960 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
