Lines Matching defs:getOpcode
35 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
156 if (isALUInstr(MI.getOpcode()))
158 if (isVector(MI) || isCubeOp(MI.getOpcode()))
160 switch (MI.getOpcode()) {
180 return isTransOnly(MI.getOpcode());
188 return isVectorOnly(MI.getOpcode());
202 usesVertexCache(MI.getOpcode());
212 usesVertexCache(MI.getOpcode())) ||
213 usesTextureCache(MI.getOpcode());
235 if (!isALUInstr(MI.getOpcode())) {
289 if (MI.getOpcode() == AMDGPU::DOT_4) {
303 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
307 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
323 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);
330 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
336 MI.getOperand(getOperandIdx(MI.getOpcode(), AMDGPU::OpName::literal));
557 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
624 if (!isALUInstr(MI.getOpcode()))
669 if (isPredicateSetter(MI.getOpcode()))
700 if (isBranch(I->getOpcode()))
702 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
707 while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
716 unsigned LastOpc = LastInst.getOpcode();
718 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
724 while (!isPredicateSetter(predSet->getOpcode())) {
738 unsigned SecondLastOpc = SecondLastInst.getOpcode();
743 while (!isPredicateSetter(predSet->getOpcode())) {
762 if (It->getOpcode() == AMDGPU::CF_ALU ||
763 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
792 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
808 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
826 switch (I->getOpcode()) {
836 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
850 switch (I->getOpcode()) {
861 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
893 if (MI.getOpcode() == AMDGPU::KILLGT) {
895 } else if (MI.getOpcode() == AMDGPU::CF_ALU) {
980 return isPredicateSetter(MI.getOpcode());
994 if (MI.getOpcode() == AMDGPU::CF_ALU) {
999 if (MI.getOpcode() == AMDGPU::DOT_4) {
1043 switch (MI.getOpcode()) {
1047 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::addr);
1052 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::chan);
1055 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
1069 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::val);
1342 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1350 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1352 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1372 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1379 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1404 return getOperandIdx(MI.getOpcode(), Op);
1424 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1429 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1494 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1515 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1528 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
1532 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
