Lines Matching defs:If
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
81 void If(MachineInstr &MI);
171 if (opcodeEmitsNoInsts(I->getOpcode()))
177 if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
181 if (I->isInlineAsm()) {
193 if (NumInstr >= SkipThreshold)
203 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
215 if (MF->getFunction()->getCallingConv() != CallingConv::AMDGPU_PS ||
224 // If the exec mask is non-zero, skip the next two instructions
248 void SILowerControlFlow::If(MachineInstr &MI) {
281 if (ExecModified) {
378 if (MBB == MI.getParent()->getNextNode())
381 // If these aren't equal, this is probably an infinite loop.
396 // Clear this thread from the exec mask if the operand is negative
397 if ((Op.isImm())) {
399 if (Op.getImm() & 0x80000000) {
423 if (const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val)) {
424 if (!Val->isUndef()) {
431 if (MRI.isAllocatable(Reg))
436 if (!Src->isUndef())
439 if (!IdxReg.isUndef())
468 if (Offset != 0) {
482 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
525 // Returns true if a new block was inserted.
533 if (AMDGPU::SReg_32RegClass.contains(Idx->getReg())) {
534 if (Offset != 0) {
601 if (!SubReg)
612 if (Offset >= NumElts)
616 if (RegIdx < 0) {
627 // Return true if a new block was inserted.
640 if (Idx->getReg() == AMDGPU::NoRegister) {
656 // Return true if a new block was inserted.
669 if (Idx->getReg() == AMDGPU::NoRegister) {
713 if (TII->isFLAT(MI))
716 if (I->modifiesRegister(AMDGPU::EXEC, TRI))
723 If(MI);
748 if (--Depth == 0 && HaveKill) {
751 if (skipIfDead(MI, *NextBB)) {
761 if (Depth == 0) {
762 if (skipIfDead(MI, *NextBB)) {
781 if (indirectSrc(MI)) {
797 if (indirectDst(MI)) {
813 if (BI != --MF.end() || I != MBB.getFirstTerminator()) {
816 if (!EmptyMBBAtEnd) {
832 if (NeedFlat && MFI->IsKernel) {
835 if (NeedFlat)
