Lines Matching defs:MBB
92 MachineBasicBlock *insertSkipBlock(MachineBasicBlock &MBB,
96 splitBlock(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
167 MachineBasicBlock &MBB = *MBBI;
169 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
212 MachineBasicBlock &MBB = *MI.getParent();
213 MachineFunction *MF = MBB.getParent();
216 !shouldSkip(&MBB, &MBB.getParent()->back()))
219 MachineBasicBlock *SkipBB = insertSkipBlock(MBB, MI.getIterator());
225 BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
249 MachineBasicBlock &MBB = *MI.getParent();
254 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
257 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
264 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
272 MachineBasicBlock &MBB = *MI.getParent();
277 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
285 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64), Dst)
290 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
297 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
305 MachineBasicBlock &MBB = *MI.getParent();
311 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
319 MachineBasicBlock &MBB = *MI.getParent();
326 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
334 MachineBasicBlock &MBB = *MI.getParent();
341 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
349 MachineBasicBlock &MBB = *MI.getParent();
353 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
357 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
364 MachineBasicBlock &MBB = *MI.getParent();
368 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
377 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
378 if (MBB == MI.getParent()->getNextNode())
385 MachineBasicBlock &MBB = *MI.getParent();
390 CallingConv::ID CallConv = MBB.getParent()->getFunction()->getCallingConv();
400 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
404 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32))
488 MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
489 MachineFunction *MF = MBB.getParent();
492 MachineFunction::iterator MBBI(MBB);
496 MBB.addSuccessor(SkipBB);
502 SILowerControlFlow::splitBlock(MachineBasicBlock &MBB,
504 MachineFunction *MF = MBB.getParent();
510 MachineFunction::iterator MBBI(MBB);
517 RemainderBB->transferSuccessors(&MBB);
518 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
520 MBB.addSuccessor(LoopBB);
527 MachineBasicBlock &MBB = *MI.getParent();
535 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
539 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
543 MBB.insert(I, MovRel);
557 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64), Save)
562 RemainderLiveRegs.addLiveOuts(MBB);
567 std::tie(LoopBB, RemainderBB) = splitBlock(MBB, I);
572 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
629 MachineBasicBlock &MBB = *MI.getParent();
642 BuildMI(MBB, MI.getIterator(), DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
649 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
658 MachineBasicBlock &MBB = *MI.getParent();
671 BuildMI(MBB, MI.getIterator(), DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
678 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32), Reg)
701 MachineBasicBlock &MBB = *BI;
707 for (I = MBB.begin(); I != MBB.end(); I = Next) {
754 Next = MBB.end();
765 Next = MBB.end();
787 Next = MBB.end();
803 Next = MBB.end();
813 if (BI != --MF.end() || I != MBB.getFirstTerminator()) {
821 MBB.addSuccessor(EmptyMBBAtEnd);
