Lines Matching defs:Opcode
201 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
209 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
217 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
224 /// should be 2, 3 or 4. The opcode array specifies the instructions used
306 // opcode and that it has a immediate integer right operand.
441 unsigned Opcode = MCID.getOpcode();
442 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
457 return TII->isFpMLxInstruction(Opcode);
901 unsigned Opcode = Op->getOpcode();
902 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
937 unsigned Opcode = Op->getOpcode();
938 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
957 unsigned Opcode = Op->getOpcode();
958 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1036 unsigned Opcode = Op->getOpcode();
1037 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1362 unsigned Opcode = Op->getOpcode();
1363 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1480 unsigned Opcode = 0;
1484 Opcode = ARM::LDR_PRE_IMM;
1488 Opcode = ARM::LDR_POST_IMM;
1492 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1498 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1505 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1511 Opcode = ARM::LDRB_PRE_IMM;
1515 Opcode = ARM::LDRB_POST_IMM;
1518 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1524 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1529 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1537 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1556 unsigned Opcode = 0;
1561 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1565 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1567 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1572 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1574 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1587 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1756 // Get the register stride update opcode of a VLD/VST instruction that
2262 // operand. It's implicit in the opcode itself.
2488 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2489 CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2629 Opcode;
2632 Opcode = ARM::CMP_SWAP_8;
2634 Opcode = ARM::CMP_SWAP_16;
2636 Opcode = ARM::CMP_SWAP_32;
2643 Opcode, SDLoc(N),
3970 unsigned Opcode;
3973 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC;
3978 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC;
3985 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops));
4004 // string to find which opcode we need to use.
4005 unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
4016 // If an opcode was found then we can lower the read to a VFP instruction.
4017 if (Opcode) {
4020 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8())
4026 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops));
4091 unsigned Opcode;
4093 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR;
4098 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR;
4107 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
4125 // on the string to find which opcode we need to use.
4126 unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
4134 if (Opcode) {
4139 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
