Lines Matching defs:Opcode
148 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
149 setOperationAction(Opcode, VT, Legal);
1114 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1115 switch ((ARMISD::NodeType)Opcode) {
3661 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3668 // If we have an unordered opcode, we need to swap the operands to the VSEL
4208 default: llvm_unreachable("Invalid opcode!");
4816 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
5587 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
5858 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6138 default: llvm_unreachable("Unknown shuffle opcode!");
6614 unsigned Opcode = N->getOpcode();
6615 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6625 unsigned Opcode = N->getOpcode();
6626 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
7795 /// Return the load opcode for a given load size. If load size >= 8,
7796 /// neon opcode will be returned.
7814 /// Return the store opcode for a given store size. If store size >= 8,
7815 /// neon opcode will be returned.
7840 assert(LdOpc != 0 && "Should have a load opcode");
7872 assert(StOpc != 0 && "Should have a store opcode");
7938 // Select the correct opcode and register class for unit size load/store
8277 default: llvm_unreachable("unexpected opcode!");
8293 // true/false values to select between, and a branch opcode to use.
8407 // true/false values to select between, and a branch opcode to use.
8535 "converted opcode should be the same except for cc_out");
8889 // Figure out the right opcode.
9115 unsigned Opcode = N0.getOpcode();
9116 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
9117 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
9118 Opcode = N1.getOpcode();
9119 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
9120 Opcode != ISD::FADD && Opcode != ISD::FSUB)
9132 return DAG.getNode(Opcode, DL, VT,
9919 // Find the new opcode for the updating load/store.
9960 default: llvm_unreachable("unexpected opcode for Neon base update");
10529 /// operand of a vector shift right operation. For a shift opcode, the value
10631 // Opcode already set above.
10722 default: llvm_unreachable("unexpected shift opcode");
10769 default: llvm_unreachable("unexpected opcode");
12011 "Unhandled Opcode in getDivRemLibcall");
12029 "Unhandled Opcode in getDivRemArgList");
12050 unsigned Opcode = Op->getOpcode();
12051 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
12052 "Invalid opcode for Div/Rem lowering");
12053 bool isSigned = (Opcode == ISD::SDIVREM);
