Lines Matching defs:isSigned
4184 /*isSigned*/ false, SDLoc(Op)).first;
4236 /*isSigned*/ false, SDLoc(Op)).first;
6434 /// element has been zero/sign-extended, depending on the isSigned parameter,
6437 bool isSigned) {
6453 if (isSigned) {
6472 if (isSigned) {
10424 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
10425 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
10482 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
10485 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
10489 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
12012 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
12017 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
12018 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
12019 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
12020 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
12030 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
12039 Entry.isSExt = isSigned;
12040 Entry.isZExt = !isSigned;
12053 bool isSigned = (Opcode == ISD::SDIVREM);
12073 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
12103 bool isSigned = N->getOpcode() == ISD::SREM;
12111 .setSExtResult(isSigned).setZExtResult(!isSigned).setDebugLoc(SDLoc(N));
12154 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
12167 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
