Lines Matching refs:ARMISD
923 // Thumb-1 cannot currently select ARMISD::SUBE.
1025 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1115 switch ((ARMISD::NodeType)Opcode) {
1116 case ARMISD::FIRST_NUMBER: break;
1117 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1118 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1119 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1120 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1121 case ARMISD::CALL: return "ARMISD::CALL";
1122 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1123 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1124 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1125 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1126 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1127 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1128 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1129 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1130 case ARMISD::CMP: return "ARMISD::CMP";
1131 case ARMISD::CMN: return "ARMISD::CMN";
1132 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1133 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1134 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1135 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1136 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1138 case ARMISD::CMOV: return "ARMISD::CMOV";
1140 case ARMISD::SSAT: return "ARMISD::SSAT";
1142 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1143 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1144 case ARMISD::RRX: return "ARMISD::RRX";
1146 case ARMISD::ADDC: return "ARMISD::ADDC";
1147 case ARMISD::ADDE: return "ARMISD::ADDE";
1148 case ARMISD::SUBC: return "ARMISD::SUBC";
1149 case ARMISD::SUBE: return "ARMISD::SUBE";
1151 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1152 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1154 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1155 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1156 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1158 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1160 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1162 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1164 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1166 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1168 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1169 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1171 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1172 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1173 case ARMISD::VCGE: return "ARMISD::VCGE";
1174 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1175 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1176 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1177 case ARMISD::VCGT: return "ARMISD::VCGT";
1178 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1179 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1180 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1181 case ARMISD::VTST: return "ARMISD::VTST";
1183 case ARMISD::VSHL: return "ARMISD::VSHL";
1184 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1185 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1186 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1187 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1188 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1189 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1190 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1191 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1192 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1193 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1194 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1195 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1196 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1197 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1198 case ARMISD::VSLI: return "ARMISD::VSLI";
1199 case ARMISD::VSRI: return "ARMISD::VSRI";
1200 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1201 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1202 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1203 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1204 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1205 case ARMISD::VDUP: return "ARMISD::VDUP";
1206 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1207 case ARMISD::VEXT: return "ARMISD::VEXT";
1208 case ARMISD::VREV64: return "ARMISD::VREV64";
1209 case ARMISD::VREV32: return "ARMISD::VREV32";
1210 case ARMISD::VREV16: return "ARMISD::VREV16";
1211 case ARMISD::VZIP: return "ARMISD::VZIP";
1212 case ARMISD::VUZP: return "ARMISD::VUZP";
1213 case ARMISD::VTRN: return "ARMISD::VTRN";
1214 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1215 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1216 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1217 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1218 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1219 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1220 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1221 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1222 case ARMISD::BFI: return "ARMISD::BFI";
1223 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1224 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1225 case ARMISD::VBSL: return "ARMISD::VBSL";
1226 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1227 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1228 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1229 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1230 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1231 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1232 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1233 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1234 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1235 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1236 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1237 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1238 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1239 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1240 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1241 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1242 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1243 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1244 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1245 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1246 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1486 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1503 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1552 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1572 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1753 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1830 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1845 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1861 ARMISD::WrapperPIC, dl, PtrVt,
1877 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
1893 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1899 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
1909 CallOpc = ARMISD::CALL_NOLINK;
1911 CallOpc = ARMISD::CALL;
1914 CallOpc = ARMISD::CALL_NOLINK;
1919 CallOpc = ARMISD::CALL_NOLINK;
1921 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1961 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2253 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2305 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2327 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2378 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2395 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2443 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2444 UI->getOpcode() != ARMISD::INTRET_FLAG)
2487 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2504 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2531 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2539 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2602 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2644 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2659 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2681 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2689 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2720 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2733 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2741 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2753 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2812 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2819 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2833 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2837 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2857 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2886 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2900 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2908 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2915 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
2933 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2947 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2955 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2962 ? ARMISD::VMULLs : ARMISD::VMULLu;
3009 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3054 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3108 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3401 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3409 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3412 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3463 ARMISD::NodeType CompareType;
3466 CompareType = ARMISD::CMP;
3471 CompareType = ARMISD::CMPZ;
3484 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3486 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3487 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3496 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3499 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3502 if (Opc == ARMISD::CMPFP)
3505 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3508 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3532 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3537 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3542 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3547 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3571 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
3607 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3701 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3703 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3711 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3713 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3716 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3718 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3858 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4040 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4054 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4084 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4105 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4109 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4123 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4131 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4141 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4148 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4250 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4256 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4260 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4268 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4272 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4280 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4300 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4321 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4479 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4487 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4489 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4491 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4511 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4544 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4578 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4619 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4630 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4646 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4650 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4709 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4711 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4767 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4769 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4860 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4863 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4864 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4896 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4900 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4904 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4906 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4908 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4915 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4916 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
4924 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4925 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
4933 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4935 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4937 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4939 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4941 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4945 if (Opc == ARMISD::VCEQ) {
4958 Opc = ARMISD::VTST;
4975 if (Opc == ARMISD::VCGE)
4976 Opc = ARMISD::VCLEZ;
4977 else if (Opc == ARMISD::VCGT)
4978 Opc = ARMISD::VCLTZ;
4985 case ARMISD::VCEQ:
4986 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
4987 case ARMISD::VCGE:
4988 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
4989 case ARMISD::VCLEZ:
4990 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
4991 case ARMISD::VCGT:
4992 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
4993 case ARMISD::VCLTZ:
4994 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5021 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5030 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5201 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
5226 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
5243 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
5587 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
5593 return ARMISD::VTRN;
5595 return ARMISD::VUZP;
5597 return ARMISD::VZIP;
5601 return ARMISD::VTRN;
5603 return ARMISD::VUZP;
5605 return ARMISD::VZIP;
5665 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5676 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5685 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5734 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5762 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5767 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5770 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5801 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5819 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5829 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5985 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
6143 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
6146 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
6149 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
6154 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
6159 return DAG.getNode(ARMISD::VEXT, dl, VT,
6164 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
6168 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
6172 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
6191 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
6194 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
6206 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
6211 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
6239 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
6253 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
6255 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
6264 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
6269 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
6271 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
6273 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
6276 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
6356 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
6374 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
6407 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
6648 NewOpc = ARMISD::VMULLs;
6653 NewOpc = ARMISD::VMULLu;
6658 NewOpc = ARMISD::VMULLs;
6661 NewOpc = ARMISD::VMULLu;
6665 NewOpc = ARMISD::VMULLu;
6899 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6900 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6901 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6902 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
7031 SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other,
7054 DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other, DAG.getEntryNode(), Or);
7226 case ARMISD::WIN__DBZCHK: return SDValue();
8891 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8979 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) {
8982 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) {
9013 SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode),
9028 /// ISD::ADDC, ISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL
9248 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
9290 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
9333 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
9387 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
9415 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
9431 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
9450 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
9482 assert(N->getOpcode() == ARMISD::BFI);
9522 while (V.getOpcode() == ARMISD::BFI) {
9572 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
9575 } else if (N->getOperand(0).getOpcode() == ARMISD::BFI) {
9605 return DCI.DAG.getNode(ARMISD::BFI, dl, VT, N->getOperand(0), From1,
9612 /// ARMISD::VMOVRRD.
9618 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
9656 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
9665 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
9692 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
9720 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
9723 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
9784 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9928 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9930 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9932 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9934 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9936 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9938 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9940 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9942 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9944 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9946 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9948 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9950 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9952 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9954 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9961 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9962 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9963 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9964 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
9966 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
10011 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
10017 // generate non-standard-aligned ARMISD::VLDx nodes.
10128 NewOpc = ARMISD::VLD2DUP;
10131 NewOpc = ARMISD::VLD3DUP;
10134 NewOpc = ARMISD::VLD4DUP;
10149 if (User->getOpcode() != ARMISD::VDUPLANE ||
10190 /// ARMISD::VDUPLANE.
10204 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
10328 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
10584 VShiftOpc = ARMISD::VSHL;
10589 ARMISD::VSHRs : ARMISD::VSHRu);
10634 VShiftOpc = ARMISD::VRSHRs; break;
10636 VShiftOpc = ARMISD::VRSHRu; break;
10638 VShiftOpc = ARMISD::VRSHRN; break;
10640 VShiftOpc = ARMISD::VQSHLs; break;
10642 VShiftOpc = ARMISD::VQSHLu; break;
10644 VShiftOpc = ARMISD::VQSHLsu; break;
10646 VShiftOpc = ARMISD::VQSHRNs; break;
10648 VShiftOpc = ARMISD::VQSHRNu; break;
10650 VShiftOpc = ARMISD::VQSHRNsu; break;
10652 VShiftOpc = ARMISD::VQRSHRNs; break;
10654 VShiftOpc = ARMISD::VQRSHRNu; break;
10656 VShiftOpc = ARMISD::VQRSHRNsu; break;
10670 VShiftOpc = ARMISD::VSLI;
10672 VShiftOpc = ARMISD::VSRI;
10727 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
10736 ARMISD::VSHRs : ARMISD::VSHRu);
10771 Opc = ARMISD::VGETLANEs;
10775 Opc = ARMISD::VGETLANEu;
10787 if (Op.getOpcode() == ARMISD::BFI) {
10800 if (Op.getOpcode() == ARMISD::CMOV) {
10837 assert(CmpZ->getOpcode() == ARMISD::CMPZ);
10896 V = DAG.getNode(ARMISD::BFI, dl, VT, V, X,
10904 /// PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
10908 if (Cmp.getOpcode() != ARMISD::CMPZ)
10925 LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
10936 ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),
10944 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
10948 if (Cmp.getOpcode() != ARMISD::CMPZ)
10988 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
10993 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
10999 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
11006 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
11041 case ARMISD::BFI: return PerformBFICombine(N, DCI);
11042 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
11043 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
11048 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
11061 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
11062 case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG);
11064 case ARMISD::VLD2DUP:
11065 case ARMISD::VLD3DUP:
11066 case ARMISD::VLD4DUP:
11068 case ARMISD::BUILD_VECTOR:
11212 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
11637 case ARMISD::ADDC:
11638 case ARMISD::ADDE:
11639 case ARMISD::SUBC:
11640 case ARMISD::SUBE:
11646 case ARMISD::CMOV: {
12137 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
