Lines Matching full:ldrd
56 STATISTIC(NumLDRDFormed,"Number of ldrd created before allocation");
58 STATISTIC(NumLDRD2LDM, "Number of ldrd instructions turned back into ldm");
60 STATISTIC(NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's");
137 /// Whether the instructions can be merged into a ldrd/strd instruction.
192 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
976 // ARM errata 602117: LDRD with base in list may result in incorrect base
988 // LDRD/STRD do not allow SP/PC. LDM/STM do not support it or have it
1576 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)
1586 // ARM errata 602117: LDRD with base in list may result in incorrect base
1589 (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();
1590 // ARM LDRD/STRD needs consecutive registers.
1591 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&
1598 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1783 // ARMPreAllocLoadStoreOpt has already formed some LDRD/STRD instructions
1835 // Try to fold add/sub into the LDRD/STRD formed by ARMPreAllocLoadStoreOpt.
2063 // Make sure we're allowed to generate LDRD/STRD.
2071 NewOpc = ARM::LDRD;
