Lines Matching refs:Imm
531 unsigned Imm;
548 unsigned Imm;
575 struct ImmOp Imm;
631 return Imm.Val;
636 return Imm.Val;
702 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
703 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
716 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
717 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
729 // with two bits of shift. textually it may be either [pc, #imm], #imm or
734 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1817 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1819 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1825 ShifterImm.Imm));
1847 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1962 unsigned Imm = CE->getValue();
1963 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2005 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2019 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2048 int32_t Imm = Memory.OffsetImm->getValue();
2049 Inst.addOperand(MCOperand::createImm(Imm));
2391 int Imm = CE->getValue();
2392 bool isAdd = Imm >= 0;
2393 if (Imm == INT32_MIN) Imm = 0;
2394 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2395 Inst.addOperand(MCOperand::createImm(Imm));
2402 int Imm = CE->getValue();
2403 bool isAdd = Imm >= 0;
2404 if (Imm == INT32_MIN) Imm = 0;
2406 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2407 Inst.addOperand(MCOperand::createImm(Imm));
2422 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2424 Inst.addOperand(MCOperand::createImm(Imm));
2571 unsigned Imm = 0;
2573 Imm |= (Value & 1) << i;
2575 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2674 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2678 Op->ShifterImm.Imm = Imm;
2684 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2687 Op->RotImm.Imm = Imm;
2706 Op->Imm.Val = Val;
2796 Op->Imm.Val = Val;
2948 << " #" << ShifterImm.Imm << ">";
2963 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3122 int64_t Imm = 0;
3147 // lsl, ror: 0 <= imm <= 31
3148 // lsr, asr: 0 <= imm <= 32
3149 Imm = CE->getValue();
3150 if (Imm < 0 ||
3151 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3152 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3158 if (Imm == 0)
3177 ShiftReg, Imm,
3180 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4689 // | # imm
4690 // | # + imm
4691 // | # - imm
5062 // lsl, ror: 0 <= imm <= 31
5063 // lsr, asr: 0 <= imm <= 32
5067 int64_t Imm = CE->getValue();
5068 if (Imm < 0 ||
5069 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5070 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5073 if (Imm == 0)
5076 if (Imm == 32)
5077 Imm = 0;
5078 Amount = Imm;
5104 // vmov.f32 <sreg>, #imm
5105 // vmov.f64 <dreg>, #imm
5106 // vmov.f32 <dreg>, #imm @ vector f32x2
5107 // vmov.f32 <qreg>, #imm @ vector f32x4
5112 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5253 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5554 // with immediate range in the 'add sp, sp #imm' case.
5606 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5725 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5726 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
6081 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
6826 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6844 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6862 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6899 // Aliases for alternate PC+imm syntax of LDR instructions.
